1 ; RUN: llc < %s -march=x86-64 | FileCheck %s
3 ; This should not generate SSE instructions:
9 define void @without.sse(float* nocapture %a, float* nocapture %b, float* nocapture %c, i32 %n) #0 {
11 %cmp9 = icmp sgt i32 %n, 0
12 br i1 %cmp9, label %for.body, label %for.end
15 %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
16 %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv
17 %0 = load float* %arrayidx, align 4
18 %arrayidx2 = getelementptr inbounds float* %c, i64 %indvars.iv
19 %1 = load float* %arrayidx2, align 4
20 %mul = fmul float %0, %1
21 %arrayidx4 = getelementptr inbounds float* %a, i64 %indvars.iv
22 store float %mul, float* %arrayidx4, align 4
23 %indvars.iv.next = add i64 %indvars.iv, 1
24 %lftr.wideiv = trunc i64 %indvars.iv.next to i32
25 %exitcond = icmp eq i32 %lftr.wideiv, %n
26 br i1 %exitcond, label %for.end, label %for.body
32 ; This should generate SSE instructions:
38 define void @with.sse(float* nocapture %a, float* nocapture %b, float* nocapture %c, i32 %n) #1 {
40 %cmp9 = icmp sgt i32 %n, 0
41 br i1 %cmp9, label %for.body, label %for.end
44 %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
45 %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv
46 %0 = load float* %arrayidx, align 4
47 %arrayidx2 = getelementptr inbounds float* %c, i64 %indvars.iv
48 %1 = load float* %arrayidx2, align 4
49 %mul = fmul float %0, %1
50 %arrayidx4 = getelementptr inbounds float* %a, i64 %indvars.iv
51 store float %mul, float* %arrayidx4, align 4
52 %indvars.iv.next = add i64 %indvars.iv, 1
53 %lftr.wideiv = trunc i64 %indvars.iv.next to i32
54 %exitcond = icmp eq i32 %lftr.wideiv, %n
55 br i1 %exitcond, label %for.end, label %for.body
61 attributes #0 = { nounwind optsize ssp uwtable "target-cpu"="core2" "target-features"="-sse4a,-avx2,-xop,-fma4,-bmi2,-3dnow,-3dnowa,-pclmul,-sse,-avx,-sse41,-ssse3,+mmx,-rtm,-sse42,-lzcnt,-f16c,-popcnt,-bmi,-aes,-fma,-rdrand,-sse2,-sse3" }
62 attributes #1 = { nounwind optsize ssp uwtable "target-cpu"="core2" "target-features"="-sse4a,-avx2,-xop,-fma4,-bmi2,-3dnow,-3dnowa,-pclmul,+sse,-avx,-sse41,+ssse3,+mmx,-rtm,-sse42,-lzcnt,-f16c,-popcnt,-bmi,-aes,-fma,-rdrand,+sse2,+sse3" }