1 ; RUN: llc -march=x86 -mcpu=generic -mattr=+sse < %s | FileCheck %s
2 ; RUN: llc -march=x86 -mcpu=atom -mattr=+sse < %s | FileCheck -check-prefix=ATOM %s
4 %vec = type <6 x float>
9 ; Scheduler causes a different instruction order to be produced on Intel Atom
14 define %vec @vecdiv( %vec %p1, %vec %p2)
16 %result = fdiv %vec %p1, %p2
20 @a = constant %vec < float 2.0, float 4.0, float 8.0, float 16.0, float 32.0, float 64.0 >
21 @b = constant %vec < float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0 >
23 ; Expected result: < 1.0, 2.0, 4.0, ..., 2.0^(n-1) >
24 ; main() returns 0 if the result is expected and 1 otherwise
25 ; to execute, use llvm-as < %s | lli
26 define i32 @main() nounwind {
31 %res = call %vec @vecdiv(%vec %avec, %vec %bvec)
34 %idx = phi i32 [0, %entry], [%nextInd, %looptail]
35 %expected = phi float [1.0, %entry], [%nextExpected, %looptail]
36 %elem = extractelement %vec %res, i32 %idx
37 %expcmp = fcmp oeq float %elem, %expected
38 br i1 %expcmp, label %looptail, label %return
40 %nextExpected = fmul float %expected, 2.0
41 %nextInd = add i32 %idx, 1
42 %cmp = icmp slt i32 %nextInd, 6
43 br i1 %cmp, label %loop, label %return
45 %retval = phi i32 [0, %looptail], [1, %loop]