1 ; RUN: llc < %s -mtriple=x86_64-darwin -x86-experimental-vector-widening-legalization -mattr=+mmx,+sse2 | FileCheck %s
3 define i32 @test0(<1 x i64>* %v4) {
6 ; CHECK-NEXT: pshufw $238, (%rdi), %mm0
7 ; CHECK-NEXT: movq2dq %mm0, %xmm0
8 ; CHECK-NEXT: movd %xmm0, %eax
9 ; CHECK-NEXT: addl $32, %eax
11 %v5 = load <1 x i64>* %v4, align 8
12 %v12 = bitcast <1 x i64> %v5 to <4 x i16>
13 %v13 = bitcast <4 x i16> %v12 to x86_mmx
14 %v14 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %v13, i8 -18)
15 %v15 = bitcast x86_mmx %v14 to <4 x i16>
16 %v16 = bitcast <4 x i16> %v15 to <1 x i64>
17 %v17 = extractelement <1 x i64> %v16, i32 0
18 %v18 = bitcast i64 %v17 to <2 x i32>
19 %v19 = extractelement <2 x i32> %v18, i32 0
20 %v20 = add i32 %v19, 32
24 define i32 @test1(i32* nocapture readonly %ptr) {
26 ; CHECK: ## BB#0: ## %entry
27 ; CHECK-NEXT: movd (%rdi), %xmm0
28 ; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
29 ; CHECK-NEXT: pshufw $232, -{{[0-9]+}}(%rsp), %mm0
30 ; CHECK-NEXT: movq2dq %mm0, %xmm0
31 ; CHECK-NEXT: movd %xmm0, %eax
35 %0 = load i32* %ptr, align 4
36 %1 = insertelement <2 x i32> undef, i32 %0, i32 0
37 %2 = insertelement <2 x i32> %1, i32 0, i32 1
38 %3 = bitcast <2 x i32> %2 to x86_mmx
39 %4 = bitcast x86_mmx %3 to i64
40 %5 = bitcast i64 %4 to <4 x i16>
41 %6 = bitcast <4 x i16> %5 to x86_mmx
42 %7 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %6, i8 -24)
43 %8 = bitcast x86_mmx %7 to <4 x i16>
44 %9 = bitcast <4 x i16> %8 to <1 x i64>
45 %10 = extractelement <1 x i64> %9, i32 0
46 %11 = bitcast i64 %10 to <2 x i32>
47 %12 = extractelement <2 x i32> %11, i32 0
48 tail call void @llvm.x86.mmx.emms()
52 define i32 @test2(i32* nocapture readonly %ptr) {
54 ; CHECK: ## BB#0: ## %entry
55 ; CHECK-NEXT: movq (%rdi), %mm0
56 ; CHECK-NEXT: pshufw $232, %mm0, %mm0
57 ; CHECK-NEXT: movq2dq %mm0, %xmm0
58 ; CHECK-NEXT: movd %xmm0, %eax
62 %0 = bitcast i32* %ptr to x86_mmx*
63 %1 = load x86_mmx* %0, align 8
64 %2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 -24)
65 %3 = bitcast x86_mmx %2 to <4 x i16>
66 %4 = bitcast <4 x i16> %3 to <1 x i64>
67 %5 = extractelement <1 x i64> %4, i32 0
68 %6 = bitcast i64 %5 to <2 x i32>
69 %7 = extractelement <2 x i32> %6, i32 0
70 tail call void @llvm.x86.mmx.emms()
74 declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8)
75 declare void @llvm.x86.mmx.emms()