1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE42
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512F
7 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512BW
13 define <2 x i64> @max_gt_v2i64(<2 x i64> %a, <2 x i64> %b) {
14 ; SSE2-LABEL: max_gt_v2i64:
16 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,0,2147483648,0]
17 ; SSE2-NEXT: movdqa %xmm1, %xmm3
18 ; SSE2-NEXT: pxor %xmm2, %xmm3
19 ; SSE2-NEXT: pxor %xmm0, %xmm2
20 ; SSE2-NEXT: movdqa %xmm2, %xmm4
21 ; SSE2-NEXT: pcmpgtd %xmm3, %xmm4
22 ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
23 ; SSE2-NEXT: pcmpeqd %xmm3, %xmm2
24 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
25 ; SSE2-NEXT: pand %xmm5, %xmm2
26 ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
27 ; SSE2-NEXT: por %xmm2, %xmm3
28 ; SSE2-NEXT: pand %xmm3, %xmm0
29 ; SSE2-NEXT: pandn %xmm1, %xmm3
30 ; SSE2-NEXT: por %xmm3, %xmm0
33 ; SSE41-LABEL: max_gt_v2i64:
35 ; SSE41-NEXT: movdqa %xmm0, %xmm2
36 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,0,2147483648,0]
37 ; SSE41-NEXT: movdqa %xmm1, %xmm3
38 ; SSE41-NEXT: pxor %xmm0, %xmm3
39 ; SSE41-NEXT: pxor %xmm2, %xmm0
40 ; SSE41-NEXT: movdqa %xmm0, %xmm4
41 ; SSE41-NEXT: pcmpgtd %xmm3, %xmm4
42 ; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
43 ; SSE41-NEXT: pcmpeqd %xmm3, %xmm0
44 ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
45 ; SSE41-NEXT: pand %xmm5, %xmm3
46 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
47 ; SSE41-NEXT: por %xmm3, %xmm0
48 ; SSE41-NEXT: blendvpd %xmm2, %xmm1
49 ; SSE41-NEXT: movapd %xmm1, %xmm0
52 ; SSE42-LABEL: max_gt_v2i64:
54 ; SSE42-NEXT: movdqa %xmm0, %xmm2
55 ; SSE42-NEXT: pcmpgtq %xmm1, %xmm0
56 ; SSE42-NEXT: blendvpd %xmm2, %xmm1
57 ; SSE42-NEXT: movapd %xmm1, %xmm0
60 ; AVX-LABEL: max_gt_v2i64:
62 ; AVX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm2
63 ; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
65 %1 = icmp sgt <2 x i64> %a, %b
66 %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b
70 define <4 x i64> @max_gt_v4i64(<4 x i64> %a, <4 x i64> %b) {
71 ; SSE2-LABEL: max_gt_v4i64:
73 ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,0,2147483648,0]
74 ; SSE2-NEXT: movdqa %xmm3, %xmm5
75 ; SSE2-NEXT: pxor %xmm4, %xmm5
76 ; SSE2-NEXT: movdqa %xmm1, %xmm6
77 ; SSE2-NEXT: pxor %xmm4, %xmm6
78 ; SSE2-NEXT: movdqa %xmm6, %xmm7
79 ; SSE2-NEXT: pcmpgtd %xmm5, %xmm7
80 ; SSE2-NEXT: pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
81 ; SSE2-NEXT: pcmpeqd %xmm5, %xmm6
82 ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
83 ; SSE2-NEXT: pand %xmm8, %xmm5
84 ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
85 ; SSE2-NEXT: por %xmm5, %xmm6
86 ; SSE2-NEXT: movdqa %xmm2, %xmm5
87 ; SSE2-NEXT: pxor %xmm4, %xmm5
88 ; SSE2-NEXT: pxor %xmm0, %xmm4
89 ; SSE2-NEXT: movdqa %xmm4, %xmm7
90 ; SSE2-NEXT: pcmpgtd %xmm5, %xmm7
91 ; SSE2-NEXT: pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
92 ; SSE2-NEXT: pcmpeqd %xmm5, %xmm4
93 ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
94 ; SSE2-NEXT: pand %xmm8, %xmm4
95 ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm7[1,1,3,3]
96 ; SSE2-NEXT: por %xmm4, %xmm5
97 ; SSE2-NEXT: pand %xmm5, %xmm0
98 ; SSE2-NEXT: pandn %xmm2, %xmm5
99 ; SSE2-NEXT: por %xmm5, %xmm0
100 ; SSE2-NEXT: pand %xmm6, %xmm1
101 ; SSE2-NEXT: pandn %xmm3, %xmm6
102 ; SSE2-NEXT: por %xmm6, %xmm1
105 ; SSE41-LABEL: max_gt_v4i64:
107 ; SSE41-NEXT: movdqa %xmm0, %xmm8
108 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,0,2147483648,0]
109 ; SSE41-NEXT: movdqa %xmm3, %xmm5
110 ; SSE41-NEXT: pxor %xmm0, %xmm5
111 ; SSE41-NEXT: movdqa %xmm1, %xmm6
112 ; SSE41-NEXT: pxor %xmm0, %xmm6
113 ; SSE41-NEXT: movdqa %xmm6, %xmm7
114 ; SSE41-NEXT: pcmpgtd %xmm5, %xmm7
115 ; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm7[0,0,2,2]
116 ; SSE41-NEXT: pcmpeqd %xmm5, %xmm6
117 ; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
118 ; SSE41-NEXT: pand %xmm4, %xmm6
119 ; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm7[1,1,3,3]
120 ; SSE41-NEXT: por %xmm6, %xmm5
121 ; SSE41-NEXT: movdqa %xmm2, %xmm4
122 ; SSE41-NEXT: pxor %xmm0, %xmm4
123 ; SSE41-NEXT: pxor %xmm8, %xmm0
124 ; SSE41-NEXT: movdqa %xmm0, %xmm6
125 ; SSE41-NEXT: pcmpgtd %xmm4, %xmm6
126 ; SSE41-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
127 ; SSE41-NEXT: pcmpeqd %xmm4, %xmm0
128 ; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
129 ; SSE41-NEXT: pand %xmm7, %xmm4
130 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3]
131 ; SSE41-NEXT: por %xmm4, %xmm0
132 ; SSE41-NEXT: blendvpd %xmm8, %xmm2
133 ; SSE41-NEXT: movdqa %xmm5, %xmm0
134 ; SSE41-NEXT: blendvpd %xmm1, %xmm3
135 ; SSE41-NEXT: movapd %xmm2, %xmm0
136 ; SSE41-NEXT: movapd %xmm3, %xmm1
139 ; SSE42-LABEL: max_gt_v4i64:
141 ; SSE42-NEXT: movdqa %xmm0, %xmm4
142 ; SSE42-NEXT: movdqa %xmm1, %xmm5
143 ; SSE42-NEXT: pcmpgtq %xmm3, %xmm5
144 ; SSE42-NEXT: pcmpgtq %xmm2, %xmm0
145 ; SSE42-NEXT: blendvpd %xmm4, %xmm2
146 ; SSE42-NEXT: movdqa %xmm5, %xmm0
147 ; SSE42-NEXT: blendvpd %xmm1, %xmm3
148 ; SSE42-NEXT: movapd %xmm2, %xmm0
149 ; SSE42-NEXT: movapd %xmm3, %xmm1
152 ; AVX1-LABEL: max_gt_v4i64:
154 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
155 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
156 ; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
157 ; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm3
158 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
159 ; AVX1-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
162 ; AVX2-LABEL: max_gt_v4i64:
164 ; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2
165 ; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
168 ; AVX512-LABEL: max_gt_v4i64:
170 ; AVX512-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2
171 ; AVX512-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
173 %1 = icmp sgt <4 x i64> %a, %b
174 %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b
178 define <4 x i32> @max_gt_v4i32(<4 x i32> %a, <4 x i32> %b) {
179 ; SSE2-LABEL: max_gt_v4i32:
181 ; SSE2-NEXT: movdqa %xmm0, %xmm2
182 ; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
183 ; SSE2-NEXT: pand %xmm2, %xmm0
184 ; SSE2-NEXT: pandn %xmm1, %xmm2
185 ; SSE2-NEXT: por %xmm0, %xmm2
186 ; SSE2-NEXT: movdqa %xmm2, %xmm0
189 ; SSE41-LABEL: max_gt_v4i32:
191 ; SSE41-NEXT: pmaxsd %xmm1, %xmm0
194 ; SSE42-LABEL: max_gt_v4i32:
196 ; SSE42-NEXT: pmaxsd %xmm1, %xmm0
199 ; AVX-LABEL: max_gt_v4i32:
201 ; AVX-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
203 %1 = icmp sgt <4 x i32> %a, %b
204 %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b
208 define <8 x i32> @max_gt_v8i32(<8 x i32> %a, <8 x i32> %b) {
209 ; SSE2-LABEL: max_gt_v8i32:
211 ; SSE2-NEXT: movdqa %xmm1, %xmm4
212 ; SSE2-NEXT: pcmpgtd %xmm3, %xmm4
213 ; SSE2-NEXT: movdqa %xmm0, %xmm5
214 ; SSE2-NEXT: pcmpgtd %xmm2, %xmm5
215 ; SSE2-NEXT: pand %xmm5, %xmm0
216 ; SSE2-NEXT: pandn %xmm2, %xmm5
217 ; SSE2-NEXT: por %xmm0, %xmm5
218 ; SSE2-NEXT: pand %xmm4, %xmm1
219 ; SSE2-NEXT: pandn %xmm3, %xmm4
220 ; SSE2-NEXT: por %xmm1, %xmm4
221 ; SSE2-NEXT: movdqa %xmm5, %xmm0
222 ; SSE2-NEXT: movdqa %xmm4, %xmm1
225 ; SSE41-LABEL: max_gt_v8i32:
227 ; SSE41-NEXT: pmaxsd %xmm2, %xmm0
228 ; SSE41-NEXT: pmaxsd %xmm3, %xmm1
231 ; SSE42-LABEL: max_gt_v8i32:
233 ; SSE42-NEXT: pmaxsd %xmm2, %xmm0
234 ; SSE42-NEXT: pmaxsd %xmm3, %xmm1
237 ; AVX1-LABEL: max_gt_v8i32:
239 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
240 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
241 ; AVX1-NEXT: vpmaxsd %xmm2, %xmm3, %xmm2
242 ; AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
243 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
246 ; AVX2-LABEL: max_gt_v8i32:
248 ; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
251 ; AVX512-LABEL: max_gt_v8i32:
253 ; AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
255 %1 = icmp sgt <8 x i32> %a, %b
256 %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b
260 define <8 x i16> @max_gt_v8i16(<8 x i16> %a, <8 x i16> %b) {
261 ; SSE-LABEL: max_gt_v8i16:
263 ; SSE-NEXT: pmaxsw %xmm1, %xmm0
266 ; AVX-LABEL: max_gt_v8i16:
268 ; AVX-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
270 %1 = icmp sgt <8 x i16> %a, %b
271 %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b
275 define <16 x i16> @max_gt_v16i16(<16 x i16> %a, <16 x i16> %b) {
276 ; SSE-LABEL: max_gt_v16i16:
278 ; SSE-NEXT: pmaxsw %xmm2, %xmm0
279 ; SSE-NEXT: pmaxsw %xmm3, %xmm1
282 ; AVX1-LABEL: max_gt_v16i16:
284 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
285 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
286 ; AVX1-NEXT: vpmaxsw %xmm2, %xmm3, %xmm2
287 ; AVX1-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
288 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
291 ; AVX2-LABEL: max_gt_v16i16:
293 ; AVX2-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
296 ; AVX512-LABEL: max_gt_v16i16:
298 ; AVX512-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
300 %1 = icmp sgt <16 x i16> %a, %b
301 %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
305 define <16 x i8> @max_gt_v16i8(<16 x i8> %a, <16 x i8> %b) {
306 ; SSE2-LABEL: max_gt_v16i8:
308 ; SSE2-NEXT: movdqa %xmm0, %xmm2
309 ; SSE2-NEXT: pcmpgtb %xmm1, %xmm2
310 ; SSE2-NEXT: pand %xmm2, %xmm0
311 ; SSE2-NEXT: pandn %xmm1, %xmm2
312 ; SSE2-NEXT: por %xmm0, %xmm2
313 ; SSE2-NEXT: movdqa %xmm2, %xmm0
316 ; SSE41-LABEL: max_gt_v16i8:
318 ; SSE41-NEXT: pmaxsb %xmm1, %xmm0
321 ; SSE42-LABEL: max_gt_v16i8:
323 ; SSE42-NEXT: pmaxsb %xmm1, %xmm0
326 ; AVX-LABEL: max_gt_v16i8:
328 ; AVX-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
330 %1 = icmp sgt <16 x i8> %a, %b
331 %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b
335 define <32 x i8> @max_gt_v32i8(<32 x i8> %a, <32 x i8> %b) {
336 ; SSE2-LABEL: max_gt_v32i8:
338 ; SSE2-NEXT: movdqa %xmm1, %xmm4
339 ; SSE2-NEXT: pcmpgtb %xmm3, %xmm4
340 ; SSE2-NEXT: movdqa %xmm0, %xmm5
341 ; SSE2-NEXT: pcmpgtb %xmm2, %xmm5
342 ; SSE2-NEXT: pand %xmm5, %xmm0
343 ; SSE2-NEXT: pandn %xmm2, %xmm5
344 ; SSE2-NEXT: por %xmm0, %xmm5
345 ; SSE2-NEXT: pand %xmm4, %xmm1
346 ; SSE2-NEXT: pandn %xmm3, %xmm4
347 ; SSE2-NEXT: por %xmm1, %xmm4
348 ; SSE2-NEXT: movdqa %xmm5, %xmm0
349 ; SSE2-NEXT: movdqa %xmm4, %xmm1
352 ; SSE41-LABEL: max_gt_v32i8:
354 ; SSE41-NEXT: pmaxsb %xmm2, %xmm0
355 ; SSE41-NEXT: pmaxsb %xmm3, %xmm1
358 ; SSE42-LABEL: max_gt_v32i8:
360 ; SSE42-NEXT: pmaxsb %xmm2, %xmm0
361 ; SSE42-NEXT: pmaxsb %xmm3, %xmm1
364 ; AVX1-LABEL: max_gt_v32i8:
366 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
367 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
368 ; AVX1-NEXT: vpmaxsb %xmm2, %xmm3, %xmm2
369 ; AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
370 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
373 ; AVX2-LABEL: max_gt_v32i8:
375 ; AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
378 ; AVX512-LABEL: max_gt_v32i8:
380 ; AVX512-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
382 %1 = icmp sgt <32 x i8> %a, %b
383 %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b
388 ; Signed Maximum (GE)
391 define <2 x i64> @max_ge_v2i64(<2 x i64> %a, <2 x i64> %b) {
392 ; SSE2-LABEL: max_ge_v2i64:
394 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,0,2147483648,0]
395 ; SSE2-NEXT: movdqa %xmm0, %xmm3
396 ; SSE2-NEXT: pxor %xmm2, %xmm3
397 ; SSE2-NEXT: pxor %xmm1, %xmm2
398 ; SSE2-NEXT: movdqa %xmm2, %xmm4
399 ; SSE2-NEXT: pcmpgtd %xmm3, %xmm4
400 ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
401 ; SSE2-NEXT: pcmpeqd %xmm3, %xmm2
402 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
403 ; SSE2-NEXT: pand %xmm5, %xmm2
404 ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
405 ; SSE2-NEXT: por %xmm2, %xmm3
406 ; SSE2-NEXT: pcmpeqd %xmm2, %xmm2
407 ; SSE2-NEXT: pxor %xmm3, %xmm2
408 ; SSE2-NEXT: pandn %xmm0, %xmm3
409 ; SSE2-NEXT: pandn %xmm1, %xmm2
410 ; SSE2-NEXT: por %xmm3, %xmm2
411 ; SSE2-NEXT: movdqa %xmm2, %xmm0
414 ; SSE41-LABEL: max_ge_v2i64:
416 ; SSE41-NEXT: movdqa %xmm0, %xmm2
417 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,0,2147483648,0]
418 ; SSE41-NEXT: movdqa %xmm2, %xmm3
419 ; SSE41-NEXT: pxor %xmm0, %xmm3
420 ; SSE41-NEXT: pxor %xmm1, %xmm0
421 ; SSE41-NEXT: movdqa %xmm0, %xmm4
422 ; SSE41-NEXT: pcmpgtd %xmm3, %xmm4
423 ; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
424 ; SSE41-NEXT: pcmpeqd %xmm3, %xmm0
425 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
426 ; SSE41-NEXT: pand %xmm5, %xmm0
427 ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
428 ; SSE41-NEXT: por %xmm0, %xmm3
429 ; SSE41-NEXT: pcmpeqd %xmm0, %xmm0
430 ; SSE41-NEXT: pxor %xmm3, %xmm0
431 ; SSE41-NEXT: blendvpd %xmm2, %xmm1
432 ; SSE41-NEXT: movapd %xmm1, %xmm0
435 ; SSE42-LABEL: max_ge_v2i64:
437 ; SSE42-NEXT: movdqa %xmm0, %xmm2
438 ; SSE42-NEXT: movdqa %xmm1, %xmm3
439 ; SSE42-NEXT: pcmpgtq %xmm2, %xmm3
440 ; SSE42-NEXT: pcmpeqd %xmm0, %xmm0
441 ; SSE42-NEXT: pxor %xmm3, %xmm0
442 ; SSE42-NEXT: blendvpd %xmm2, %xmm1
443 ; SSE42-NEXT: movapd %xmm1, %xmm0
446 ; AVX-LABEL: max_ge_v2i64:
448 ; AVX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2
449 ; AVX-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
450 ; AVX-NEXT: vpxor %xmm3, %xmm2, %xmm2
451 ; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
453 %1 = icmp sge <2 x i64> %a, %b
454 %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b
458 define <4 x i64> @max_ge_v4i64(<4 x i64> %a, <4 x i64> %b) {
459 ; SSE2-LABEL: max_ge_v4i64:
461 ; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [2147483648,0,2147483648,0]
462 ; SSE2-NEXT: movdqa %xmm1, %xmm4
463 ; SSE2-NEXT: pxor %xmm7, %xmm4
464 ; SSE2-NEXT: movdqa %xmm3, %xmm5
465 ; SSE2-NEXT: pxor %xmm7, %xmm5
466 ; SSE2-NEXT: movdqa %xmm5, %xmm6
467 ; SSE2-NEXT: pcmpgtd %xmm4, %xmm6
468 ; SSE2-NEXT: pshufd {{.*#+}} xmm8 = xmm6[0,0,2,2]
469 ; SSE2-NEXT: pcmpeqd %xmm4, %xmm5
470 ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
471 ; SSE2-NEXT: pand %xmm8, %xmm4
472 ; SSE2-NEXT: pshufd {{.*#+}} xmm8 = xmm6[1,1,3,3]
473 ; SSE2-NEXT: por %xmm4, %xmm8
474 ; SSE2-NEXT: pcmpeqd %xmm4, %xmm4
475 ; SSE2-NEXT: movdqa %xmm8, %xmm9
476 ; SSE2-NEXT: pxor %xmm4, %xmm9
477 ; SSE2-NEXT: movdqa %xmm0, %xmm6
478 ; SSE2-NEXT: pxor %xmm7, %xmm6
479 ; SSE2-NEXT: pxor %xmm2, %xmm7
480 ; SSE2-NEXT: movdqa %xmm7, %xmm5
481 ; SSE2-NEXT: pcmpgtd %xmm6, %xmm5
482 ; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm5[0,0,2,2]
483 ; SSE2-NEXT: pcmpeqd %xmm6, %xmm7
484 ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
485 ; SSE2-NEXT: pand %xmm10, %xmm6
486 ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
487 ; SSE2-NEXT: por %xmm6, %xmm5
488 ; SSE2-NEXT: pxor %xmm5, %xmm4
489 ; SSE2-NEXT: pandn %xmm0, %xmm5
490 ; SSE2-NEXT: pandn %xmm2, %xmm4
491 ; SSE2-NEXT: por %xmm5, %xmm4
492 ; SSE2-NEXT: pandn %xmm1, %xmm8
493 ; SSE2-NEXT: pandn %xmm3, %xmm9
494 ; SSE2-NEXT: por %xmm8, %xmm9
495 ; SSE2-NEXT: movdqa %xmm4, %xmm0
496 ; SSE2-NEXT: movdqa %xmm9, %xmm1
499 ; SSE41-LABEL: max_ge_v4i64:
501 ; SSE41-NEXT: movdqa %xmm0, %xmm8
502 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,0,2147483648,0]
503 ; SSE41-NEXT: movdqa %xmm1, %xmm5
504 ; SSE41-NEXT: pxor %xmm0, %xmm5
505 ; SSE41-NEXT: movdqa %xmm3, %xmm6
506 ; SSE41-NEXT: pxor %xmm0, %xmm6
507 ; SSE41-NEXT: movdqa %xmm6, %xmm7
508 ; SSE41-NEXT: pcmpgtd %xmm5, %xmm7
509 ; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm7[0,0,2,2]
510 ; SSE41-NEXT: pcmpeqd %xmm5, %xmm6
511 ; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
512 ; SSE41-NEXT: pand %xmm4, %xmm6
513 ; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm7[1,1,3,3]
514 ; SSE41-NEXT: por %xmm6, %xmm5
515 ; SSE41-NEXT: pcmpeqd %xmm9, %xmm9
516 ; SSE41-NEXT: pxor %xmm9, %xmm5
517 ; SSE41-NEXT: movdqa %xmm8, %xmm6
518 ; SSE41-NEXT: pxor %xmm0, %xmm6
519 ; SSE41-NEXT: pxor %xmm2, %xmm0
520 ; SSE41-NEXT: movdqa %xmm0, %xmm7
521 ; SSE41-NEXT: pcmpgtd %xmm6, %xmm7
522 ; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm7[0,0,2,2]
523 ; SSE41-NEXT: pcmpeqd %xmm6, %xmm0
524 ; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm0[1,1,3,3]
525 ; SSE41-NEXT: pand %xmm4, %xmm6
526 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm7[1,1,3,3]
527 ; SSE41-NEXT: por %xmm6, %xmm0
528 ; SSE41-NEXT: pxor %xmm9, %xmm0
529 ; SSE41-NEXT: blendvpd %xmm8, %xmm2
530 ; SSE41-NEXT: movdqa %xmm5, %xmm0
531 ; SSE41-NEXT: blendvpd %xmm1, %xmm3
532 ; SSE41-NEXT: movapd %xmm2, %xmm0
533 ; SSE41-NEXT: movapd %xmm3, %xmm1
536 ; SSE42-LABEL: max_ge_v4i64:
538 ; SSE42-NEXT: movdqa %xmm0, %xmm4
539 ; SSE42-NEXT: movdqa %xmm3, %xmm5
540 ; SSE42-NEXT: pcmpgtq %xmm1, %xmm5
541 ; SSE42-NEXT: pcmpeqd %xmm0, %xmm0
542 ; SSE42-NEXT: pxor %xmm0, %xmm5
543 ; SSE42-NEXT: movdqa %xmm2, %xmm6
544 ; SSE42-NEXT: pcmpgtq %xmm4, %xmm6
545 ; SSE42-NEXT: pxor %xmm6, %xmm0
546 ; SSE42-NEXT: blendvpd %xmm4, %xmm2
547 ; SSE42-NEXT: movdqa %xmm5, %xmm0
548 ; SSE42-NEXT: blendvpd %xmm1, %xmm3
549 ; SSE42-NEXT: movapd %xmm2, %xmm0
550 ; SSE42-NEXT: movapd %xmm3, %xmm1
553 ; AVX1-LABEL: max_ge_v4i64:
555 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
556 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
557 ; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
558 ; AVX1-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
559 ; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2
560 ; AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm4
561 ; AVX1-NEXT: vpxor %xmm3, %xmm4, %xmm3
562 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
563 ; AVX1-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
566 ; AVX2-LABEL: max_ge_v4i64:
568 ; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
569 ; AVX2-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3
570 ; AVX2-NEXT: vpxor %ymm3, %ymm2, %ymm2
571 ; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
574 ; AVX512-LABEL: max_ge_v4i64:
576 ; AVX512-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
577 ; AVX512-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3
578 ; AVX512-NEXT: vpxor %ymm3, %ymm2, %ymm2
579 ; AVX512-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
581 %1 = icmp sge <4 x i64> %a, %b
582 %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b
586 define <4 x i32> @max_ge_v4i32(<4 x i32> %a, <4 x i32> %b) {
587 ; SSE2-LABEL: max_ge_v4i32:
589 ; SSE2-NEXT: movdqa %xmm1, %xmm3
590 ; SSE2-NEXT: pcmpgtd %xmm0, %xmm3
591 ; SSE2-NEXT: pcmpeqd %xmm2, %xmm2
592 ; SSE2-NEXT: pxor %xmm3, %xmm2
593 ; SSE2-NEXT: pandn %xmm0, %xmm3
594 ; SSE2-NEXT: pandn %xmm1, %xmm2
595 ; SSE2-NEXT: por %xmm3, %xmm2
596 ; SSE2-NEXT: movdqa %xmm2, %xmm0
599 ; SSE41-LABEL: max_ge_v4i32:
601 ; SSE41-NEXT: pmaxsd %xmm1, %xmm0
604 ; SSE42-LABEL: max_ge_v4i32:
606 ; SSE42-NEXT: pmaxsd %xmm1, %xmm0
609 ; AVX-LABEL: max_ge_v4i32:
611 ; AVX-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
613 %1 = icmp sge <4 x i32> %a, %b
614 %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b
618 define <8 x i32> @max_ge_v8i32(<8 x i32> %a, <8 x i32> %b) {
619 ; SSE2-LABEL: max_ge_v8i32:
621 ; SSE2-NEXT: movdqa %xmm3, %xmm6
622 ; SSE2-NEXT: pcmpgtd %xmm1, %xmm6
623 ; SSE2-NEXT: pcmpeqd %xmm4, %xmm4
624 ; SSE2-NEXT: movdqa %xmm6, %xmm5
625 ; SSE2-NEXT: pxor %xmm4, %xmm5
626 ; SSE2-NEXT: movdqa %xmm2, %xmm7
627 ; SSE2-NEXT: pcmpgtd %xmm0, %xmm7
628 ; SSE2-NEXT: pxor %xmm7, %xmm4
629 ; SSE2-NEXT: pandn %xmm0, %xmm7
630 ; SSE2-NEXT: pandn %xmm2, %xmm4
631 ; SSE2-NEXT: por %xmm7, %xmm4
632 ; SSE2-NEXT: pandn %xmm1, %xmm6
633 ; SSE2-NEXT: pandn %xmm3, %xmm5
634 ; SSE2-NEXT: por %xmm6, %xmm5
635 ; SSE2-NEXT: movdqa %xmm4, %xmm0
636 ; SSE2-NEXT: movdqa %xmm5, %xmm1
639 ; SSE41-LABEL: max_ge_v8i32:
641 ; SSE41-NEXT: pmaxsd %xmm2, %xmm0
642 ; SSE41-NEXT: pmaxsd %xmm3, %xmm1
645 ; SSE42-LABEL: max_ge_v8i32:
647 ; SSE42-NEXT: pmaxsd %xmm2, %xmm0
648 ; SSE42-NEXT: pmaxsd %xmm3, %xmm1
651 ; AVX1-LABEL: max_ge_v8i32:
653 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
654 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
655 ; AVX1-NEXT: vpmaxsd %xmm2, %xmm3, %xmm2
656 ; AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
657 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
660 ; AVX2-LABEL: max_ge_v8i32:
662 ; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
665 ; AVX512-LABEL: max_ge_v8i32:
667 ; AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
669 %1 = icmp sge <8 x i32> %a, %b
670 %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b
674 define <8 x i16> @max_ge_v8i16(<8 x i16> %a, <8 x i16> %b) {
675 ; SSE-LABEL: max_ge_v8i16:
677 ; SSE-NEXT: pmaxsw %xmm1, %xmm0
680 ; AVX-LABEL: max_ge_v8i16:
682 ; AVX-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
684 %1 = icmp sge <8 x i16> %a, %b
685 %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b
689 define <16 x i16> @max_ge_v16i16(<16 x i16> %a, <16 x i16> %b) {
690 ; SSE-LABEL: max_ge_v16i16:
692 ; SSE-NEXT: pmaxsw %xmm2, %xmm0
693 ; SSE-NEXT: pmaxsw %xmm3, %xmm1
696 ; AVX1-LABEL: max_ge_v16i16:
698 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
699 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
700 ; AVX1-NEXT: vpmaxsw %xmm2, %xmm3, %xmm2
701 ; AVX1-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
702 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
705 ; AVX2-LABEL: max_ge_v16i16:
707 ; AVX2-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
710 ; AVX512-LABEL: max_ge_v16i16:
712 ; AVX512-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
714 %1 = icmp sge <16 x i16> %a, %b
715 %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
719 define <16 x i8> @max_ge_v16i8(<16 x i8> %a, <16 x i8> %b) {
720 ; SSE2-LABEL: max_ge_v16i8:
722 ; SSE2-NEXT: movdqa %xmm1, %xmm3
723 ; SSE2-NEXT: pcmpgtb %xmm0, %xmm3
724 ; SSE2-NEXT: pcmpeqd %xmm2, %xmm2
725 ; SSE2-NEXT: pxor %xmm3, %xmm2
726 ; SSE2-NEXT: pandn %xmm0, %xmm3
727 ; SSE2-NEXT: pandn %xmm1, %xmm2
728 ; SSE2-NEXT: por %xmm3, %xmm2
729 ; SSE2-NEXT: movdqa %xmm2, %xmm0
732 ; SSE41-LABEL: max_ge_v16i8:
734 ; SSE41-NEXT: pmaxsb %xmm1, %xmm0
737 ; SSE42-LABEL: max_ge_v16i8:
739 ; SSE42-NEXT: pmaxsb %xmm1, %xmm0
742 ; AVX-LABEL: max_ge_v16i8:
744 ; AVX-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
746 %1 = icmp sge <16 x i8> %a, %b
747 %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b
751 define <32 x i8> @max_ge_v32i8(<32 x i8> %a, <32 x i8> %b) {
752 ; SSE2-LABEL: max_ge_v32i8:
754 ; SSE2-NEXT: movdqa %xmm3, %xmm6
755 ; SSE2-NEXT: pcmpgtb %xmm1, %xmm6
756 ; SSE2-NEXT: pcmpeqd %xmm4, %xmm4
757 ; SSE2-NEXT: movdqa %xmm6, %xmm5
758 ; SSE2-NEXT: pxor %xmm4, %xmm5
759 ; SSE2-NEXT: movdqa %xmm2, %xmm7
760 ; SSE2-NEXT: pcmpgtb %xmm0, %xmm7
761 ; SSE2-NEXT: pxor %xmm7, %xmm4
762 ; SSE2-NEXT: pandn %xmm0, %xmm7
763 ; SSE2-NEXT: pandn %xmm2, %xmm4
764 ; SSE2-NEXT: por %xmm7, %xmm4
765 ; SSE2-NEXT: pandn %xmm1, %xmm6
766 ; SSE2-NEXT: pandn %xmm3, %xmm5
767 ; SSE2-NEXT: por %xmm6, %xmm5
768 ; SSE2-NEXT: movdqa %xmm4, %xmm0
769 ; SSE2-NEXT: movdqa %xmm5, %xmm1
772 ; SSE41-LABEL: max_ge_v32i8:
774 ; SSE41-NEXT: pmaxsb %xmm2, %xmm0
775 ; SSE41-NEXT: pmaxsb %xmm3, %xmm1
778 ; SSE42-LABEL: max_ge_v32i8:
780 ; SSE42-NEXT: pmaxsb %xmm2, %xmm0
781 ; SSE42-NEXT: pmaxsb %xmm3, %xmm1
784 ; AVX1-LABEL: max_ge_v32i8:
786 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
787 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
788 ; AVX1-NEXT: vpmaxsb %xmm2, %xmm3, %xmm2
789 ; AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
790 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
793 ; AVX2-LABEL: max_ge_v32i8:
795 ; AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
798 ; AVX512-LABEL: max_ge_v32i8:
800 ; AVX512-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
802 %1 = icmp sge <32 x i8> %a, %b
803 %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b
808 ; Signed Minimum (LT)
811 define <2 x i64> @min_lt_v2i64(<2 x i64> %a, <2 x i64> %b) {
812 ; SSE2-LABEL: min_lt_v2i64:
814 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,0,2147483648,0]
815 ; SSE2-NEXT: movdqa %xmm0, %xmm3
816 ; SSE2-NEXT: pxor %xmm2, %xmm3
817 ; SSE2-NEXT: pxor %xmm1, %xmm2
818 ; SSE2-NEXT: movdqa %xmm2, %xmm4
819 ; SSE2-NEXT: pcmpgtd %xmm3, %xmm4
820 ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
821 ; SSE2-NEXT: pcmpeqd %xmm3, %xmm2
822 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
823 ; SSE2-NEXT: pand %xmm5, %xmm2
824 ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
825 ; SSE2-NEXT: por %xmm2, %xmm3
826 ; SSE2-NEXT: pand %xmm3, %xmm0
827 ; SSE2-NEXT: pandn %xmm1, %xmm3
828 ; SSE2-NEXT: por %xmm3, %xmm0
831 ; SSE41-LABEL: min_lt_v2i64:
833 ; SSE41-NEXT: movdqa %xmm0, %xmm2
834 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,0,2147483648,0]
835 ; SSE41-NEXT: movdqa %xmm2, %xmm3
836 ; SSE41-NEXT: pxor %xmm0, %xmm3
837 ; SSE41-NEXT: pxor %xmm1, %xmm0
838 ; SSE41-NEXT: movdqa %xmm0, %xmm4
839 ; SSE41-NEXT: pcmpgtd %xmm3, %xmm4
840 ; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
841 ; SSE41-NEXT: pcmpeqd %xmm3, %xmm0
842 ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
843 ; SSE41-NEXT: pand %xmm5, %xmm3
844 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
845 ; SSE41-NEXT: por %xmm3, %xmm0
846 ; SSE41-NEXT: blendvpd %xmm2, %xmm1
847 ; SSE41-NEXT: movapd %xmm1, %xmm0
850 ; SSE42-LABEL: min_lt_v2i64:
852 ; SSE42-NEXT: movdqa %xmm0, %xmm2
853 ; SSE42-NEXT: movdqa %xmm1, %xmm0
854 ; SSE42-NEXT: pcmpgtq %xmm2, %xmm0
855 ; SSE42-NEXT: blendvpd %xmm2, %xmm1
856 ; SSE42-NEXT: movapd %xmm1, %xmm0
859 ; AVX-LABEL: min_lt_v2i64:
861 ; AVX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2
862 ; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
864 %1 = icmp slt <2 x i64> %a, %b
865 %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b
869 define <4 x i64> @min_lt_v4i64(<4 x i64> %a, <4 x i64> %b) {
870 ; SSE2-LABEL: min_lt_v4i64:
872 ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,0,2147483648,0]
873 ; SSE2-NEXT: movdqa %xmm1, %xmm5
874 ; SSE2-NEXT: pxor %xmm4, %xmm5
875 ; SSE2-NEXT: movdqa %xmm3, %xmm6
876 ; SSE2-NEXT: pxor %xmm4, %xmm6
877 ; SSE2-NEXT: movdqa %xmm6, %xmm7
878 ; SSE2-NEXT: pcmpgtd %xmm5, %xmm7
879 ; SSE2-NEXT: pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
880 ; SSE2-NEXT: pcmpeqd %xmm5, %xmm6
881 ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
882 ; SSE2-NEXT: pand %xmm8, %xmm5
883 ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
884 ; SSE2-NEXT: por %xmm5, %xmm6
885 ; SSE2-NEXT: movdqa %xmm0, %xmm5
886 ; SSE2-NEXT: pxor %xmm4, %xmm5
887 ; SSE2-NEXT: pxor %xmm2, %xmm4
888 ; SSE2-NEXT: movdqa %xmm4, %xmm7
889 ; SSE2-NEXT: pcmpgtd %xmm5, %xmm7
890 ; SSE2-NEXT: pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
891 ; SSE2-NEXT: pcmpeqd %xmm5, %xmm4
892 ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
893 ; SSE2-NEXT: pand %xmm8, %xmm4
894 ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm7[1,1,3,3]
895 ; SSE2-NEXT: por %xmm4, %xmm5
896 ; SSE2-NEXT: pand %xmm5, %xmm0
897 ; SSE2-NEXT: pandn %xmm2, %xmm5
898 ; SSE2-NEXT: por %xmm5, %xmm0
899 ; SSE2-NEXT: pand %xmm6, %xmm1
900 ; SSE2-NEXT: pandn %xmm3, %xmm6
901 ; SSE2-NEXT: por %xmm6, %xmm1
904 ; SSE41-LABEL: min_lt_v4i64:
906 ; SSE41-NEXT: movdqa %xmm0, %xmm8
907 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,0,2147483648,0]
908 ; SSE41-NEXT: movdqa %xmm1, %xmm5
909 ; SSE41-NEXT: pxor %xmm0, %xmm5
910 ; SSE41-NEXT: movdqa %xmm3, %xmm6
911 ; SSE41-NEXT: pxor %xmm0, %xmm6
912 ; SSE41-NEXT: movdqa %xmm6, %xmm7
913 ; SSE41-NEXT: pcmpgtd %xmm5, %xmm7
914 ; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm7[0,0,2,2]
915 ; SSE41-NEXT: pcmpeqd %xmm5, %xmm6
916 ; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
917 ; SSE41-NEXT: pand %xmm4, %xmm6
918 ; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm7[1,1,3,3]
919 ; SSE41-NEXT: por %xmm6, %xmm5
920 ; SSE41-NEXT: movdqa %xmm8, %xmm4
921 ; SSE41-NEXT: pxor %xmm0, %xmm4
922 ; SSE41-NEXT: pxor %xmm2, %xmm0
923 ; SSE41-NEXT: movdqa %xmm0, %xmm6
924 ; SSE41-NEXT: pcmpgtd %xmm4, %xmm6
925 ; SSE41-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
926 ; SSE41-NEXT: pcmpeqd %xmm4, %xmm0
927 ; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
928 ; SSE41-NEXT: pand %xmm7, %xmm4
929 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3]
930 ; SSE41-NEXT: por %xmm4, %xmm0
931 ; SSE41-NEXT: blendvpd %xmm8, %xmm2
932 ; SSE41-NEXT: movdqa %xmm5, %xmm0
933 ; SSE41-NEXT: blendvpd %xmm1, %xmm3
934 ; SSE41-NEXT: movapd %xmm2, %xmm0
935 ; SSE41-NEXT: movapd %xmm3, %xmm1
938 ; SSE42-LABEL: min_lt_v4i64:
940 ; SSE42-NEXT: movdqa %xmm0, %xmm4
941 ; SSE42-NEXT: movdqa %xmm3, %xmm5
942 ; SSE42-NEXT: pcmpgtq %xmm1, %xmm5
943 ; SSE42-NEXT: movdqa %xmm2, %xmm0
944 ; SSE42-NEXT: pcmpgtq %xmm4, %xmm0
945 ; SSE42-NEXT: blendvpd %xmm4, %xmm2
946 ; SSE42-NEXT: movdqa %xmm5, %xmm0
947 ; SSE42-NEXT: blendvpd %xmm1, %xmm3
948 ; SSE42-NEXT: movapd %xmm2, %xmm0
949 ; SSE42-NEXT: movapd %xmm3, %xmm1
952 ; AVX1-LABEL: min_lt_v4i64:
954 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
955 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
956 ; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
957 ; AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm3
958 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
959 ; AVX1-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
962 ; AVX2-LABEL: min_lt_v4i64:
964 ; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
965 ; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
968 ; AVX512-LABEL: min_lt_v4i64:
970 ; AVX512-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
971 ; AVX512-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
973 %1 = icmp slt <4 x i64> %a, %b
974 %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b
978 define <4 x i32> @min_lt_v4i32(<4 x i32> %a, <4 x i32> %b) {
979 ; SSE2-LABEL: min_lt_v4i32:
981 ; SSE2-NEXT: movdqa %xmm1, %xmm2
982 ; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
983 ; SSE2-NEXT: pand %xmm2, %xmm0
984 ; SSE2-NEXT: pandn %xmm1, %xmm2
985 ; SSE2-NEXT: por %xmm2, %xmm0
988 ; SSE41-LABEL: min_lt_v4i32:
990 ; SSE41-NEXT: pminsd %xmm1, %xmm0
993 ; SSE42-LABEL: min_lt_v4i32:
995 ; SSE42-NEXT: pminsd %xmm1, %xmm0
998 ; AVX-LABEL: min_lt_v4i32:
1000 ; AVX-NEXT: vpminsd %xmm1, %xmm0, %xmm0
1002 %1 = icmp slt <4 x i32> %a, %b
1003 %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b
1007 define <8 x i32> @min_lt_v8i32(<8 x i32> %a, <8 x i32> %b) {
1008 ; SSE2-LABEL: min_lt_v8i32:
1010 ; SSE2-NEXT: movdqa %xmm3, %xmm4
1011 ; SSE2-NEXT: pcmpgtd %xmm1, %xmm4
1012 ; SSE2-NEXT: movdqa %xmm2, %xmm5
1013 ; SSE2-NEXT: pcmpgtd %xmm0, %xmm5
1014 ; SSE2-NEXT: pand %xmm5, %xmm0
1015 ; SSE2-NEXT: pandn %xmm2, %xmm5
1016 ; SSE2-NEXT: por %xmm5, %xmm0
1017 ; SSE2-NEXT: pand %xmm4, %xmm1
1018 ; SSE2-NEXT: pandn %xmm3, %xmm4
1019 ; SSE2-NEXT: por %xmm4, %xmm1
1022 ; SSE41-LABEL: min_lt_v8i32:
1024 ; SSE41-NEXT: pminsd %xmm2, %xmm0
1025 ; SSE41-NEXT: pminsd %xmm3, %xmm1
1028 ; SSE42-LABEL: min_lt_v8i32:
1030 ; SSE42-NEXT: pminsd %xmm2, %xmm0
1031 ; SSE42-NEXT: pminsd %xmm3, %xmm1
1034 ; AVX1-LABEL: min_lt_v8i32:
1036 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
1037 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
1038 ; AVX1-NEXT: vpminsd %xmm2, %xmm3, %xmm2
1039 ; AVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm0
1040 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
1043 ; AVX2-LABEL: min_lt_v8i32:
1045 ; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
1048 ; AVX512-LABEL: min_lt_v8i32:
1050 ; AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm0
1052 %1 = icmp slt <8 x i32> %a, %b
1053 %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b
1057 define <8 x i16> @min_lt_v8i16(<8 x i16> %a, <8 x i16> %b) {
1058 ; SSE-LABEL: min_lt_v8i16:
1060 ; SSE-NEXT: pminsw %xmm1, %xmm0
1063 ; AVX-LABEL: min_lt_v8i16:
1065 ; AVX-NEXT: vpminsw %xmm1, %xmm0, %xmm0
1067 %1 = icmp slt <8 x i16> %a, %b
1068 %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b
1072 define <16 x i16> @min_lt_v16i16(<16 x i16> %a, <16 x i16> %b) {
1073 ; SSE-LABEL: min_lt_v16i16:
1075 ; SSE-NEXT: pminsw %xmm2, %xmm0
1076 ; SSE-NEXT: pminsw %xmm3, %xmm1
1079 ; AVX1-LABEL: min_lt_v16i16:
1081 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
1082 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
1083 ; AVX1-NEXT: vpminsw %xmm2, %xmm3, %xmm2
1084 ; AVX1-NEXT: vpminsw %xmm1, %xmm0, %xmm0
1085 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
1088 ; AVX2-LABEL: min_lt_v16i16:
1090 ; AVX2-NEXT: vpminsw %ymm1, %ymm0, %ymm0
1093 ; AVX512-LABEL: min_lt_v16i16:
1095 ; AVX512-NEXT: vpminsw %ymm1, %ymm0, %ymm0
1097 %1 = icmp slt <16 x i16> %a, %b
1098 %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
1102 define <16 x i8> @min_lt_v16i8(<16 x i8> %a, <16 x i8> %b) {
1103 ; SSE2-LABEL: min_lt_v16i8:
1105 ; SSE2-NEXT: movdqa %xmm1, %xmm2
1106 ; SSE2-NEXT: pcmpgtb %xmm0, %xmm2
1107 ; SSE2-NEXT: pand %xmm2, %xmm0
1108 ; SSE2-NEXT: pandn %xmm1, %xmm2
1109 ; SSE2-NEXT: por %xmm2, %xmm0
1112 ; SSE41-LABEL: min_lt_v16i8:
1114 ; SSE41-NEXT: pminsb %xmm1, %xmm0
1117 ; SSE42-LABEL: min_lt_v16i8:
1119 ; SSE42-NEXT: pminsb %xmm1, %xmm0
1122 ; AVX-LABEL: min_lt_v16i8:
1124 ; AVX-NEXT: vpminsb %xmm1, %xmm0, %xmm0
1126 %1 = icmp slt <16 x i8> %a, %b
1127 %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b
1131 define <32 x i8> @min_lt_v32i8(<32 x i8> %a, <32 x i8> %b) {
1132 ; SSE2-LABEL: min_lt_v32i8:
1134 ; SSE2-NEXT: movdqa %xmm3, %xmm4
1135 ; SSE2-NEXT: pcmpgtb %xmm1, %xmm4
1136 ; SSE2-NEXT: movdqa %xmm2, %xmm5
1137 ; SSE2-NEXT: pcmpgtb %xmm0, %xmm5
1138 ; SSE2-NEXT: pand %xmm5, %xmm0
1139 ; SSE2-NEXT: pandn %xmm2, %xmm5
1140 ; SSE2-NEXT: por %xmm5, %xmm0
1141 ; SSE2-NEXT: pand %xmm4, %xmm1
1142 ; SSE2-NEXT: pandn %xmm3, %xmm4
1143 ; SSE2-NEXT: por %xmm4, %xmm1
1146 ; SSE41-LABEL: min_lt_v32i8:
1148 ; SSE41-NEXT: pminsb %xmm2, %xmm0
1149 ; SSE41-NEXT: pminsb %xmm3, %xmm1
1152 ; SSE42-LABEL: min_lt_v32i8:
1154 ; SSE42-NEXT: pminsb %xmm2, %xmm0
1155 ; SSE42-NEXT: pminsb %xmm3, %xmm1
1158 ; AVX1-LABEL: min_lt_v32i8:
1160 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
1161 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
1162 ; AVX1-NEXT: vpminsb %xmm2, %xmm3, %xmm2
1163 ; AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm0
1164 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
1167 ; AVX2-LABEL: min_lt_v32i8:
1169 ; AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm0
1172 ; AVX512-LABEL: min_lt_v32i8:
1174 ; AVX512-NEXT: vpminsb %ymm1, %ymm0, %ymm0
1176 %1 = icmp slt <32 x i8> %a, %b
1177 %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b
1182 ; Signed Minimum (LE)
1185 define <2 x i64> @min_le_v2i64(<2 x i64> %a, <2 x i64> %b) {
1186 ; SSE2-LABEL: min_le_v2i64:
1188 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,0,2147483648,0]
1189 ; SSE2-NEXT: movdqa %xmm1, %xmm3
1190 ; SSE2-NEXT: pxor %xmm2, %xmm3
1191 ; SSE2-NEXT: pxor %xmm0, %xmm2
1192 ; SSE2-NEXT: movdqa %xmm2, %xmm4
1193 ; SSE2-NEXT: pcmpgtd %xmm3, %xmm4
1194 ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
1195 ; SSE2-NEXT: pcmpeqd %xmm3, %xmm2
1196 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
1197 ; SSE2-NEXT: pand %xmm5, %xmm2
1198 ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
1199 ; SSE2-NEXT: por %xmm2, %xmm3
1200 ; SSE2-NEXT: pcmpeqd %xmm2, %xmm2
1201 ; SSE2-NEXT: pxor %xmm3, %xmm2
1202 ; SSE2-NEXT: pandn %xmm0, %xmm3
1203 ; SSE2-NEXT: pandn %xmm1, %xmm2
1204 ; SSE2-NEXT: por %xmm3, %xmm2
1205 ; SSE2-NEXT: movdqa %xmm2, %xmm0
1208 ; SSE41-LABEL: min_le_v2i64:
1210 ; SSE41-NEXT: movdqa %xmm0, %xmm2
1211 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,0,2147483648,0]
1212 ; SSE41-NEXT: movdqa %xmm1, %xmm3
1213 ; SSE41-NEXT: pxor %xmm0, %xmm3
1214 ; SSE41-NEXT: pxor %xmm2, %xmm0
1215 ; SSE41-NEXT: movdqa %xmm0, %xmm4
1216 ; SSE41-NEXT: pcmpgtd %xmm3, %xmm4
1217 ; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
1218 ; SSE41-NEXT: pcmpeqd %xmm3, %xmm0
1219 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
1220 ; SSE41-NEXT: pand %xmm5, %xmm0
1221 ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
1222 ; SSE41-NEXT: por %xmm0, %xmm3
1223 ; SSE41-NEXT: pcmpeqd %xmm0, %xmm0
1224 ; SSE41-NEXT: pxor %xmm3, %xmm0
1225 ; SSE41-NEXT: blendvpd %xmm2, %xmm1
1226 ; SSE41-NEXT: movapd %xmm1, %xmm0
1229 ; SSE42-LABEL: min_le_v2i64:
1231 ; SSE42-NEXT: movdqa %xmm0, %xmm2
1232 ; SSE42-NEXT: pcmpgtq %xmm1, %xmm0
1233 ; SSE42-NEXT: pcmpeqd %xmm3, %xmm3
1234 ; SSE42-NEXT: pxor %xmm3, %xmm0
1235 ; SSE42-NEXT: blendvpd %xmm2, %xmm1
1236 ; SSE42-NEXT: movapd %xmm1, %xmm0
1239 ; AVX-LABEL: min_le_v2i64:
1241 ; AVX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm2
1242 ; AVX-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
1243 ; AVX-NEXT: vpxor %xmm3, %xmm2, %xmm2
1244 ; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
1246 %1 = icmp sle <2 x i64> %a, %b
1247 %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b
1251 define <4 x i64> @min_le_v4i64(<4 x i64> %a, <4 x i64> %b) {
1252 ; SSE2-LABEL: min_le_v4i64:
1254 ; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [2147483648,0,2147483648,0]
1255 ; SSE2-NEXT: movdqa %xmm3, %xmm4
1256 ; SSE2-NEXT: pxor %xmm7, %xmm4
1257 ; SSE2-NEXT: movdqa %xmm1, %xmm5
1258 ; SSE2-NEXT: pxor %xmm7, %xmm5
1259 ; SSE2-NEXT: movdqa %xmm5, %xmm6
1260 ; SSE2-NEXT: pcmpgtd %xmm4, %xmm6
1261 ; SSE2-NEXT: pshufd {{.*#+}} xmm8 = xmm6[0,0,2,2]
1262 ; SSE2-NEXT: pcmpeqd %xmm4, %xmm5
1263 ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
1264 ; SSE2-NEXT: pand %xmm8, %xmm4
1265 ; SSE2-NEXT: pshufd {{.*#+}} xmm8 = xmm6[1,1,3,3]
1266 ; SSE2-NEXT: por %xmm4, %xmm8
1267 ; SSE2-NEXT: pcmpeqd %xmm4, %xmm4
1268 ; SSE2-NEXT: movdqa %xmm8, %xmm9
1269 ; SSE2-NEXT: pxor %xmm4, %xmm9
1270 ; SSE2-NEXT: movdqa %xmm2, %xmm6
1271 ; SSE2-NEXT: pxor %xmm7, %xmm6
1272 ; SSE2-NEXT: pxor %xmm0, %xmm7
1273 ; SSE2-NEXT: movdqa %xmm7, %xmm5
1274 ; SSE2-NEXT: pcmpgtd %xmm6, %xmm5
1275 ; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm5[0,0,2,2]
1276 ; SSE2-NEXT: pcmpeqd %xmm6, %xmm7
1277 ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
1278 ; SSE2-NEXT: pand %xmm10, %xmm6
1279 ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
1280 ; SSE2-NEXT: por %xmm6, %xmm5
1281 ; SSE2-NEXT: pxor %xmm5, %xmm4
1282 ; SSE2-NEXT: pandn %xmm0, %xmm5
1283 ; SSE2-NEXT: pandn %xmm2, %xmm4
1284 ; SSE2-NEXT: por %xmm5, %xmm4
1285 ; SSE2-NEXT: pandn %xmm1, %xmm8
1286 ; SSE2-NEXT: pandn %xmm3, %xmm9
1287 ; SSE2-NEXT: por %xmm8, %xmm9
1288 ; SSE2-NEXT: movdqa %xmm4, %xmm0
1289 ; SSE2-NEXT: movdqa %xmm9, %xmm1
1292 ; SSE41-LABEL: min_le_v4i64:
1294 ; SSE41-NEXT: movdqa %xmm0, %xmm8
1295 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,0,2147483648,0]
1296 ; SSE41-NEXT: movdqa %xmm3, %xmm5
1297 ; SSE41-NEXT: pxor %xmm0, %xmm5
1298 ; SSE41-NEXT: movdqa %xmm1, %xmm6
1299 ; SSE41-NEXT: pxor %xmm0, %xmm6
1300 ; SSE41-NEXT: movdqa %xmm6, %xmm7
1301 ; SSE41-NEXT: pcmpgtd %xmm5, %xmm7
1302 ; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm7[0,0,2,2]
1303 ; SSE41-NEXT: pcmpeqd %xmm5, %xmm6
1304 ; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
1305 ; SSE41-NEXT: pand %xmm4, %xmm6
1306 ; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm7[1,1,3,3]
1307 ; SSE41-NEXT: por %xmm6, %xmm5
1308 ; SSE41-NEXT: pcmpeqd %xmm9, %xmm9
1309 ; SSE41-NEXT: pxor %xmm9, %xmm5
1310 ; SSE41-NEXT: movdqa %xmm2, %xmm6
1311 ; SSE41-NEXT: pxor %xmm0, %xmm6
1312 ; SSE41-NEXT: pxor %xmm8, %xmm0
1313 ; SSE41-NEXT: movdqa %xmm0, %xmm7
1314 ; SSE41-NEXT: pcmpgtd %xmm6, %xmm7
1315 ; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm7[0,0,2,2]
1316 ; SSE41-NEXT: pcmpeqd %xmm6, %xmm0
1317 ; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm0[1,1,3,3]
1318 ; SSE41-NEXT: pand %xmm4, %xmm6
1319 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm7[1,1,3,3]
1320 ; SSE41-NEXT: por %xmm6, %xmm0
1321 ; SSE41-NEXT: pxor %xmm9, %xmm0
1322 ; SSE41-NEXT: blendvpd %xmm8, %xmm2
1323 ; SSE41-NEXT: movdqa %xmm5, %xmm0
1324 ; SSE41-NEXT: blendvpd %xmm1, %xmm3
1325 ; SSE41-NEXT: movapd %xmm2, %xmm0
1326 ; SSE41-NEXT: movapd %xmm3, %xmm1
1329 ; SSE42-LABEL: min_le_v4i64:
1331 ; SSE42-NEXT: movdqa %xmm0, %xmm4
1332 ; SSE42-NEXT: movdqa %xmm1, %xmm5
1333 ; SSE42-NEXT: pcmpgtq %xmm3, %xmm5
1334 ; SSE42-NEXT: pcmpeqd %xmm6, %xmm6
1335 ; SSE42-NEXT: pxor %xmm6, %xmm5
1336 ; SSE42-NEXT: pcmpgtq %xmm2, %xmm0
1337 ; SSE42-NEXT: pxor %xmm6, %xmm0
1338 ; SSE42-NEXT: blendvpd %xmm4, %xmm2
1339 ; SSE42-NEXT: movdqa %xmm5, %xmm0
1340 ; SSE42-NEXT: blendvpd %xmm1, %xmm3
1341 ; SSE42-NEXT: movapd %xmm2, %xmm0
1342 ; SSE42-NEXT: movapd %xmm3, %xmm1
1345 ; AVX1-LABEL: min_le_v4i64:
1347 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
1348 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
1349 ; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
1350 ; AVX1-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
1351 ; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2
1352 ; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm4
1353 ; AVX1-NEXT: vpxor %xmm3, %xmm4, %xmm3
1354 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
1355 ; AVX1-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
1358 ; AVX2-LABEL: min_le_v4i64:
1360 ; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2
1361 ; AVX2-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3
1362 ; AVX2-NEXT: vpxor %ymm3, %ymm2, %ymm2
1363 ; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
1366 ; AVX512-LABEL: min_le_v4i64:
1368 ; AVX512-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2
1369 ; AVX512-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3
1370 ; AVX512-NEXT: vpxor %ymm3, %ymm2, %ymm2
1371 ; AVX512-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
1373 %1 = icmp sle <4 x i64> %a, %b
1374 %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b
1378 define <4 x i32> @min_le_v4i32(<4 x i32> %a, <4 x i32> %b) {
1379 ; SSE2-LABEL: min_le_v4i32:
1381 ; SSE2-NEXT: movdqa %xmm0, %xmm2
1382 ; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
1383 ; SSE2-NEXT: pcmpeqd %xmm3, %xmm3
1384 ; SSE2-NEXT: pxor %xmm2, %xmm3
1385 ; SSE2-NEXT: pandn %xmm0, %xmm2
1386 ; SSE2-NEXT: pandn %xmm1, %xmm3
1387 ; SSE2-NEXT: por %xmm3, %xmm2
1388 ; SSE2-NEXT: movdqa %xmm2, %xmm0
1391 ; SSE41-LABEL: min_le_v4i32:
1393 ; SSE41-NEXT: pminsd %xmm1, %xmm0
1396 ; SSE42-LABEL: min_le_v4i32:
1398 ; SSE42-NEXT: pminsd %xmm1, %xmm0
1401 ; AVX-LABEL: min_le_v4i32:
1403 ; AVX-NEXT: vpminsd %xmm1, %xmm0, %xmm0
1405 %1 = icmp sle <4 x i32> %a, %b
1406 %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b
1410 define <8 x i32> @min_le_v8i32(<8 x i32> %a, <8 x i32> %b) {
1411 ; SSE2-LABEL: min_le_v8i32:
1413 ; SSE2-NEXT: movdqa %xmm1, %xmm6
1414 ; SSE2-NEXT: pcmpgtd %xmm3, %xmm6
1415 ; SSE2-NEXT: pcmpeqd %xmm7, %xmm7
1416 ; SSE2-NEXT: movdqa %xmm6, %xmm4
1417 ; SSE2-NEXT: pxor %xmm7, %xmm4
1418 ; SSE2-NEXT: movdqa %xmm0, %xmm5
1419 ; SSE2-NEXT: pcmpgtd %xmm2, %xmm5
1420 ; SSE2-NEXT: pxor %xmm5, %xmm7
1421 ; SSE2-NEXT: pandn %xmm0, %xmm5
1422 ; SSE2-NEXT: pandn %xmm2, %xmm7
1423 ; SSE2-NEXT: por %xmm7, %xmm5
1424 ; SSE2-NEXT: pandn %xmm1, %xmm6
1425 ; SSE2-NEXT: pandn %xmm3, %xmm4
1426 ; SSE2-NEXT: por %xmm6, %xmm4
1427 ; SSE2-NEXT: movdqa %xmm5, %xmm0
1428 ; SSE2-NEXT: movdqa %xmm4, %xmm1
1431 ; SSE41-LABEL: min_le_v8i32:
1433 ; SSE41-NEXT: pminsd %xmm2, %xmm0
1434 ; SSE41-NEXT: pminsd %xmm3, %xmm1
1437 ; SSE42-LABEL: min_le_v8i32:
1439 ; SSE42-NEXT: pminsd %xmm2, %xmm0
1440 ; SSE42-NEXT: pminsd %xmm3, %xmm1
1443 ; AVX1-LABEL: min_le_v8i32:
1445 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
1446 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
1447 ; AVX1-NEXT: vpminsd %xmm2, %xmm3, %xmm2
1448 ; AVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm0
1449 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
1452 ; AVX2-LABEL: min_le_v8i32:
1454 ; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
1457 ; AVX512-LABEL: min_le_v8i32:
1459 ; AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm0
1461 %1 = icmp sle <8 x i32> %a, %b
1462 %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b
1466 define <8 x i16> @min_le_v8i16(<8 x i16> %a, <8 x i16> %b) {
1467 ; SSE-LABEL: min_le_v8i16:
1469 ; SSE-NEXT: pminsw %xmm1, %xmm0
1472 ; AVX-LABEL: min_le_v8i16:
1474 ; AVX-NEXT: vpminsw %xmm1, %xmm0, %xmm0
1476 %1 = icmp sle <8 x i16> %a, %b
1477 %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b
1481 define <16 x i16> @min_le_v16i16(<16 x i16> %a, <16 x i16> %b) {
1482 ; SSE-LABEL: min_le_v16i16:
1484 ; SSE-NEXT: pminsw %xmm2, %xmm0
1485 ; SSE-NEXT: pminsw %xmm3, %xmm1
1488 ; AVX1-LABEL: min_le_v16i16:
1490 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
1491 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
1492 ; AVX1-NEXT: vpminsw %xmm2, %xmm3, %xmm2
1493 ; AVX1-NEXT: vpminsw %xmm1, %xmm0, %xmm0
1494 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
1497 ; AVX2-LABEL: min_le_v16i16:
1499 ; AVX2-NEXT: vpminsw %ymm1, %ymm0, %ymm0
1502 ; AVX512-LABEL: min_le_v16i16:
1504 ; AVX512-NEXT: vpminsw %ymm1, %ymm0, %ymm0
1506 %1 = icmp sle <16 x i16> %a, %b
1507 %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
1511 define <16 x i8> @min_le_v16i8(<16 x i8> %a, <16 x i8> %b) {
1512 ; SSE2-LABEL: min_le_v16i8:
1514 ; SSE2-NEXT: movdqa %xmm0, %xmm2
1515 ; SSE2-NEXT: pcmpgtb %xmm1, %xmm2
1516 ; SSE2-NEXT: pcmpeqd %xmm3, %xmm3
1517 ; SSE2-NEXT: pxor %xmm2, %xmm3
1518 ; SSE2-NEXT: pandn %xmm0, %xmm2
1519 ; SSE2-NEXT: pandn %xmm1, %xmm3
1520 ; SSE2-NEXT: por %xmm3, %xmm2
1521 ; SSE2-NEXT: movdqa %xmm2, %xmm0
1524 ; SSE41-LABEL: min_le_v16i8:
1526 ; SSE41-NEXT: pminsb %xmm1, %xmm0
1529 ; SSE42-LABEL: min_le_v16i8:
1531 ; SSE42-NEXT: pminsb %xmm1, %xmm0
1534 ; AVX-LABEL: min_le_v16i8:
1536 ; AVX-NEXT: vpminsb %xmm1, %xmm0, %xmm0
1538 %1 = icmp sle <16 x i8> %a, %b
1539 %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b
1543 define <32 x i8> @min_le_v32i8(<32 x i8> %a, <32 x i8> %b) {
1544 ; SSE2-LABEL: min_le_v32i8:
1546 ; SSE2-NEXT: movdqa %xmm1, %xmm6
1547 ; SSE2-NEXT: pcmpgtb %xmm3, %xmm6
1548 ; SSE2-NEXT: pcmpeqd %xmm7, %xmm7
1549 ; SSE2-NEXT: movdqa %xmm6, %xmm4
1550 ; SSE2-NEXT: pxor %xmm7, %xmm4
1551 ; SSE2-NEXT: movdqa %xmm0, %xmm5
1552 ; SSE2-NEXT: pcmpgtb %xmm2, %xmm5
1553 ; SSE2-NEXT: pxor %xmm5, %xmm7
1554 ; SSE2-NEXT: pandn %xmm0, %xmm5
1555 ; SSE2-NEXT: pandn %xmm2, %xmm7
1556 ; SSE2-NEXT: por %xmm7, %xmm5
1557 ; SSE2-NEXT: pandn %xmm1, %xmm6
1558 ; SSE2-NEXT: pandn %xmm3, %xmm4
1559 ; SSE2-NEXT: por %xmm6, %xmm4
1560 ; SSE2-NEXT: movdqa %xmm5, %xmm0
1561 ; SSE2-NEXT: movdqa %xmm4, %xmm1
1564 ; SSE41-LABEL: min_le_v32i8:
1566 ; SSE41-NEXT: pminsb %xmm2, %xmm0
1567 ; SSE41-NEXT: pminsb %xmm3, %xmm1
1570 ; SSE42-LABEL: min_le_v32i8:
1572 ; SSE42-NEXT: pminsb %xmm2, %xmm0
1573 ; SSE42-NEXT: pminsb %xmm3, %xmm1
1576 ; AVX1-LABEL: min_le_v32i8:
1578 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
1579 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
1580 ; AVX1-NEXT: vpminsb %xmm2, %xmm3, %xmm2
1581 ; AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm0
1582 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
1585 ; AVX2-LABEL: min_le_v32i8:
1587 ; AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm0
1590 ; AVX512-LABEL: min_le_v32i8:
1592 ; AVX512-NEXT: vpminsb %ymm1, %ymm0, %ymm0
1594 %1 = icmp sle <32 x i8> %a, %b
1595 %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b
1603 define <2 x i64> @max_gt_v2i64c() {
1604 ; SSE-LABEL: max_gt_v2i64c:
1606 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551615,7]
1609 ; AVX-LABEL: max_gt_v2i64c:
1611 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
1613 %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
1614 %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
1615 %3 = icmp sgt <2 x i64> %1, %2
1616 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1620 define <4 x i64> @max_gt_v4i64c() {
1621 ; SSE-LABEL: max_gt_v4i64c:
1623 ; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7]
1624 ; SSE-NEXT: pcmpeqd %xmm0, %xmm0
1627 ; AVX-LABEL: max_gt_v4i64c:
1629 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
1631 %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
1632 %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
1633 %3 = icmp sgt <4 x i64> %1, %2
1634 %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
1638 define <4 x i32> @max_gt_v4i32c() {
1639 ; SSE-LABEL: max_gt_v4i32c:
1641 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
1644 ; AVX-LABEL: max_gt_v4i32c:
1646 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
1648 %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
1649 %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
1650 %3 = icmp sgt <4 x i32> %1, %2
1651 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1655 define <8 x i32> @max_gt_v8i32c() {
1656 ; SSE-LABEL: max_gt_v8i32c:
1658 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
1659 ; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
1662 ; AVX-LABEL: max_gt_v8i32c:
1664 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
1666 %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
1667 %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
1668 %3 = icmp sgt <8 x i32> %1, %2
1669 %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
1673 define <8 x i16> @max_gt_v8i16c() {
1674 ; SSE-LABEL: max_gt_v8i16c:
1676 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
1679 ; AVX-LABEL: max_gt_v8i16c:
1681 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
1683 %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
1684 %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
1685 %3 = icmp sgt <8 x i16> %1, %2
1686 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1690 define <16 x i16> @max_gt_v16i16c() {
1691 ; SSE-LABEL: max_gt_v16i16c:
1693 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
1694 ; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
1697 ; AVX-LABEL: max_gt_v16i16c:
1699 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8]
1701 %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
1702 %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
1703 %3 = icmp sgt <16 x i16> %1, %2
1704 %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
1708 define <16 x i8> @max_gt_v16i8c() {
1709 ; SSE-LABEL: max_gt_v16i8c:
1711 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
1714 ; AVX-LABEL: max_gt_v16i8c:
1716 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
1718 %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
1719 %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
1720 %3 = icmp sgt <16 x i8> %1, %2
1721 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1725 define <2 x i64> @max_ge_v2i64c() {
1726 ; SSE-LABEL: max_ge_v2i64c:
1728 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551615,7]
1731 ; AVX-LABEL: max_ge_v2i64c:
1733 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
1735 %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
1736 %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
1737 %3 = icmp sge <2 x i64> %1, %2
1738 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1742 define <4 x i64> @max_ge_v4i64c() {
1743 ; SSE-LABEL: max_ge_v4i64c:
1745 ; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7]
1746 ; SSE-NEXT: pcmpeqd %xmm0, %xmm0
1749 ; AVX-LABEL: max_ge_v4i64c:
1751 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
1753 %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
1754 %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
1755 %3 = icmp sge <4 x i64> %1, %2
1756 %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
1760 define <4 x i32> @max_ge_v4i32c() {
1761 ; SSE-LABEL: max_ge_v4i32c:
1763 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
1766 ; AVX-LABEL: max_ge_v4i32c:
1768 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
1770 %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
1771 %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
1772 %3 = icmp sge <4 x i32> %1, %2
1773 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1777 define <8 x i32> @max_ge_v8i32c() {
1778 ; SSE-LABEL: max_ge_v8i32c:
1780 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
1781 ; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
1784 ; AVX-LABEL: max_ge_v8i32c:
1786 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
1788 %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
1789 %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
1790 %3 = icmp sge <8 x i32> %1, %2
1791 %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
1795 define <8 x i16> @max_ge_v8i16c() {
1796 ; SSE-LABEL: max_ge_v8i16c:
1798 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
1801 ; AVX-LABEL: max_ge_v8i16c:
1803 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
1805 %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
1806 %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
1807 %3 = icmp sge <8 x i16> %1, %2
1808 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1812 define <16 x i16> @max_ge_v16i16c() {
1813 ; SSE-LABEL: max_ge_v16i16c:
1815 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
1816 ; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
1819 ; AVX-LABEL: max_ge_v16i16c:
1821 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8]
1823 %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
1824 %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
1825 %3 = icmp sge <16 x i16> %1, %2
1826 %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
1830 define <16 x i8> @max_ge_v16i8c() {
1831 ; SSE-LABEL: max_ge_v16i8c:
1833 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
1836 ; AVX-LABEL: max_ge_v16i8c:
1838 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
1840 %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
1841 %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
1842 %3 = icmp sge <16 x i8> %1, %2
1843 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1847 define <2 x i64> @min_lt_v2i64c() {
1848 ; SSE-LABEL: min_lt_v2i64c:
1850 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551609,1]
1853 ; AVX-LABEL: min_lt_v2i64c:
1855 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
1857 %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
1858 %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
1859 %3 = icmp slt <2 x i64> %1, %2
1860 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1864 define <4 x i64> @min_lt_v4i64c() {
1865 ; SSE-LABEL: min_lt_v4i64c:
1867 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551609,18446744073709551609]
1868 ; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,1]
1871 ; AVX-LABEL: min_lt_v4i64c:
1873 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
1875 %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
1876 %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
1877 %3 = icmp slt <4 x i64> %1, %2
1878 %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
1882 define <4 x i32> @min_lt_v4i32c() {
1883 ; SSE-LABEL: min_lt_v4i32c:
1885 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
1888 ; AVX-LABEL: min_lt_v4i32c:
1890 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
1892 %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
1893 %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
1894 %3 = icmp slt <4 x i32> %1, %2
1895 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1899 define <8 x i32> @min_lt_v8i32c() {
1900 ; SSE-LABEL: min_lt_v8i32c:
1902 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
1903 ; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
1906 ; AVX-LABEL: min_lt_v8i32c:
1908 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
1910 %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
1911 %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
1912 %3 = icmp slt <8 x i32> %1, %2
1913 %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
1917 define <8 x i16> @min_lt_v8i16c() {
1918 ; SSE-LABEL: min_lt_v8i16c:
1920 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
1923 ; AVX-LABEL: min_lt_v8i16c:
1925 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
1927 %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
1928 %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
1929 %3 = icmp slt <8 x i16> %1, %2
1930 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1934 define <16 x i16> @min_lt_v16i16c() {
1935 ; SSE-LABEL: min_lt_v16i16c:
1937 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0]
1938 ; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
1941 ; AVX-LABEL: min_lt_v16i16c:
1943 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65529,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0]
1945 %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
1946 %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
1947 %3 = icmp slt <16 x i16> %1, %2
1948 %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
1952 define <16 x i8> @min_lt_v16i8c() {
1953 ; SSE-LABEL: min_lt_v16i8c:
1955 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
1958 ; AVX-LABEL: min_lt_v16i8c:
1960 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
1962 %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
1963 %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
1964 %3 = icmp slt <16 x i8> %1, %2
1965 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1969 define <2 x i64> @min_le_v2i64c() {
1970 ; SSE-LABEL: min_le_v2i64c:
1972 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551609,1]
1975 ; AVX-LABEL: min_le_v2i64c:
1977 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
1979 %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
1980 %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
1981 %3 = icmp sle <2 x i64> %1, %2
1982 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1986 define <4 x i64> @min_le_v4i64c() {
1987 ; SSE-LABEL: min_le_v4i64c:
1989 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551609,18446744073709551609]
1990 ; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,1]
1993 ; AVX-LABEL: min_le_v4i64c:
1995 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
1997 %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
1998 %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
1999 %3 = icmp sle <4 x i64> %1, %2
2000 %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
2004 define <4 x i32> @min_le_v4i32c() {
2005 ; SSE-LABEL: min_le_v4i32c:
2007 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
2010 ; AVX-LABEL: min_le_v4i32c:
2012 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
2014 %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
2015 %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
2016 %3 = icmp sle <4 x i32> %1, %2
2017 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
2021 define <8 x i32> @min_le_v8i32c() {
2022 ; SSE-LABEL: min_le_v8i32c:
2024 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
2025 ; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
2028 ; AVX-LABEL: min_le_v8i32c:
2030 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
2032 %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
2033 %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
2034 %3 = icmp sle <8 x i32> %1, %2
2035 %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
2039 define <8 x i16> @min_le_v8i16c() {
2040 ; SSE-LABEL: min_le_v8i16c:
2042 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
2045 ; AVX-LABEL: min_le_v8i16c:
2047 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
2049 %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
2050 %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
2051 %3 = icmp sle <8 x i16> %1, %2
2052 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
2056 define <16 x i16> @min_le_v16i16c() {
2057 ; SSE-LABEL: min_le_v16i16c:
2059 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0]
2060 ; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
2063 ; AVX-LABEL: min_le_v16i16c:
2065 ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65529,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0]
2067 %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
2068 %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
2069 %3 = icmp sle <16 x i16> %1, %2
2070 %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
2074 define <16 x i8> @min_le_v16i8c() {
2075 ; SSE-LABEL: min_le_v16i8c:
2077 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
2080 ; AVX-LABEL: min_le_v16i8c:
2082 ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
2084 %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
2085 %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
2086 %3 = icmp sle <16 x i8> %1, %2
2087 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2