1 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s -check-prefix=CHECK -check-prefix=SSE
2 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core-avx2 | FileCheck %s -check-prefix=CHECK -check-prefix=AVX2 -check-prefix=AVX2ONLY
3 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=knl | FileCheck %s -check-prefix=CHECK -check-prefix=AVX2 -check-prefix=AVX512
6 ; Verify that we don't scalarize a packed vector shift left of 16-bit
7 ; signed integers if the amount is a constant build_vector.
8 ; Check that we produce a SSE2 packed integer multiply (pmullw) instead.
10 define <8 x i16> @test1(<8 x i16> %a) {
11 %shl = shl <8 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
19 define <8 x i16> @test2(<8 x i16> %a) {
20 %shl = shl <8 x i16> %a, <i16 0, i16 undef, i16 0, i16 0, i16 1, i16 undef, i16 -1, i16 1>
28 ; Verify that a vector shift left of 32-bit signed integers is simply expanded
29 ; into a SSE4.1 pmulld (instead of cvttps2dq + pmulld) if the vector of shift
30 ; counts is a constant build_vector.
32 define <4 x i32> @test3(<4 x i32> %a) {
33 %shl = shl <4 x i32> %a, <i32 1, i32 -1, i32 2, i32 -3>
37 ; CHECK-NOT: cvttps2dq
43 define <4 x i32> @test4(<4 x i32> %a) {
44 %shl = shl <4 x i32> %a, <i32 0, i32 0, i32 1, i32 1>
48 ; CHECK-NOT: cvttps2dq
54 ; If we have AVX/SSE2 but not AVX2, verify that the following shift is split
55 ; into two pmullw instructions. With AVX2, the test case below would produce
58 define <16 x i16> @test5(<16 x i16> %a) {
59 %shl = shl <16 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
70 ; If we have AVX/SSE4.1 but not AVX2, verify that the following shift is split
71 ; into two pmulld instructions. With AVX2, the test case below would produce
72 ; a single vpsllvd instead.
74 define <8 x i32> @test6(<8 x i32> %a) {
75 %shl = shl <8 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
85 ; With AVX2 and AVX512, the test case below should produce a sequence of
86 ; two vpmullw instructions. On SSE2 instead, we split the shift in four
87 ; parts and then we convert each part into a pmullw.
89 define <32 x i16> @test7(<32 x i16> %a) {
90 %shl = shl <32 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
103 ; Similar to test7; the difference is that with AVX512 support
104 ; we only produce a single vpsllvd/vpsllvq instead of a pair of vpsllvd/vpsllvq.
106 define <16 x i32> @test8(<16 x i32> %a) {
107 %shl = shl <16 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
116 ; AVX2ONLY-NEXT: vpsllvd
118 ; AVX512-NOT: vpsllvd
122 ; The shift from 'test9' gets scalarized if we don't have AVX2/AVX512f support.
124 define <8 x i64> @test9(<8 x i64> %a) {
125 %shl = shl <8 x i64> %a, <i64 1, i64 1, i64 2, i64 3, i64 1, i64 1, i64 2, i64 3>
130 ; AVX2ONLY-NEXT: vpsllvq
132 ; AVX512-NOT: vpsllvq