1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
5 define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
6 ; CHECK-LABEL: vsel_float:
8 ; CHECK-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
10 %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %v1, <4 x float> %v2
14 define <4 x float> @vsel_float2(<4 x float> %v1, <4 x float> %v2) {
15 ; CHECK-LABEL: vsel_float2:
17 ; CHECK-NEXT: vmovss %xmm0, %xmm1, %xmm0
19 %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
23 define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
24 ; CHECK-LABEL: vsel_i32:
26 ; CHECK-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
28 %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> %v1, <4 x i32> %v2
32 define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
33 ; CHECK-LABEL: vsel_double:
35 ; CHECK-NEXT: vmovsd %xmm0, %xmm1, %xmm0
37 %vsel = select <2 x i1> <i1 true, i1 false>, <2 x double> %v1, <2 x double> %v2
38 ret <2 x double> %vsel
41 define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
42 ; CHECK-LABEL: vsel_i64:
44 ; CHECK-NEXT: vmovsd %xmm0, %xmm1, %xmm0
46 %vsel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %v1, <2 x i64> %v2
50 define <8 x i16> @vsel_8xi16(<8 x i16> %v1, <8 x i16> %v2) {
51 ; CHECK-LABEL: vsel_8xi16:
53 ; CHECK-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3],xmm0[4],xmm1[5,6,7]
55 %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i16> %v1, <8 x i16> %v2
59 define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
60 ; CHECK-LABEL: vsel_i8:
62 ; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
63 ; CHECK-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
65 %vsel = select <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <16 x i8> %v1, <16 x i8> %v2
72 define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {
73 ; CHECK-LABEL: vsel_float8:
75 ; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7]
77 %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x float> %v1, <8 x float> %v2
81 define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) {
82 ; CHECK-LABEL: vsel_i328:
84 ; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7]
86 %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i32> %v1, <8 x i32> %v2
90 define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
91 ; CHECK-LABEL: vsel_double8:
93 ; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm2[1,2,3]
94 ; CHECK-NEXT: vblendpd {{.*#+}} ymm1 = ymm1[0],ymm3[1,2,3]
96 %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x double> %v1, <8 x double> %v2
97 ret <8 x double> %vsel
100 define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {
101 ; CHECK-LABEL: vsel_i648:
103 ; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm2[1,2,3]
104 ; CHECK-NEXT: vblendpd {{.*#+}} ymm1 = ymm1[0],ymm3[1,2,3]
106 %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i64> %v1, <8 x i64> %v2
110 define <4 x double> @vsel_double4(<4 x double> %v1, <4 x double> %v2) {
111 ; CHECK-LABEL: vsel_double4:
113 ; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3]
115 %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x double> %v1, <4 x double> %v2
116 ret <4 x double> %vsel
119 define <2 x double> @testa(<2 x double> %x, <2 x double> %y) {
120 ; CHECK-LABEL: testa:
122 ; CHECK-NEXT: vcmplepd %xmm0, %xmm1, %xmm2
123 ; CHECK-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
125 %max_is_x = fcmp oge <2 x double> %x, %y
126 %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
127 ret <2 x double> %max
130 define <2 x double> @testb(<2 x double> %x, <2 x double> %y) {
131 ; CHECK-LABEL: testb:
133 ; CHECK-NEXT: vcmpnlepd %xmm0, %xmm1, %xmm2
134 ; CHECK-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
136 %min_is_x = fcmp ult <2 x double> %x, %y
137 %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y
138 ret <2 x double> %min
141 ; If we can figure out a blend has a constant mask, we should emit the
142 ; blend instruction with an immediate mask
143 define <4 x double> @constant_blendvpd_avx(<4 x double> %xy, <4 x double> %ab) {
144 ; CHECK-LABEL: constant_blendvpd_avx:
146 ; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3]
148 %1 = select <4 x i1> <i1 false, i1 false, i1 true, i1 false>, <4 x double> %xy, <4 x double> %ab
152 define <8 x float> @constant_blendvps_avx(<8 x float> %xyzw, <8 x float> %abcd) {
153 ; CHECK-LABEL: constant_blendvps_avx:
155 ; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5,6],ymm0[7]
157 %1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true>, <8 x float> %xyzw, <8 x float> %abcd
161 declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>)
162 declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>)
164 ;; 4 tests for shufflevectors that optimize to blend + immediate
165 define <4 x float> @blend_shufflevector_4xfloat(<4 x float> %a, <4 x float> %b) {
166 ; CHECK-LABEL: blend_shufflevector_4xfloat:
168 ; CHECK-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
170 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
174 define <8 x float> @blend_shufflevector_8xfloat(<8 x float> %a, <8 x float> %b) {
175 ; CHECK-LABEL: blend_shufflevector_8xfloat:
177 ; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5],ymm0[6],ymm1[7]
179 %1 = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 12, i32 13, i32 6, i32 15>
183 define <4 x double> @blend_shufflevector_4xdouble(<4 x double> %a, <4 x double> %b) {
184 ; CHECK-LABEL: blend_shufflevector_4xdouble:
186 ; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3]
188 %1 = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
192 define <4 x i64> @blend_shufflevector_4xi64(<4 x i64> %a, <4 x i64> %b) {
193 ; CHECK-LABEL: blend_shufflevector_4xi64:
195 ; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2,3]
197 %1 = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>