1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
5 define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
6 ; CHECK-LABEL: vsel_float:
8 ; CHECK-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
10 %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %v1, <4 x float> %v2
14 define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
15 ; CHECK-LABEL: vsel_i32:
17 ; CHECK-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
19 %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> %v1, <4 x i32> %v2
23 define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
24 ; CHECK-LABEL: vsel_double:
26 ; CHECK-NEXT: vmovsd %xmm0, %xmm1, %xmm0
28 %vsel = select <2 x i1> <i1 true, i1 false>, <2 x double> %v1, <2 x double> %v2
29 ret <2 x double> %vsel
32 define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
33 ; CHECK-LABEL: vsel_i64:
35 ; CHECK-NEXT: vmovsd %xmm0, %xmm1, %xmm0
37 %vsel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %v1, <2 x i64> %v2
41 define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
42 ; CHECK-LABEL: vsel_i8:
44 ; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
45 ; CHECK-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
47 %vsel = select <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <16 x i8> %v1, <16 x i8> %v2
54 define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {
55 ; CHECK-LABEL: vsel_float8:
57 ; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7]
59 %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x float> %v1, <8 x float> %v2
63 define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) {
64 ; CHECK-LABEL: vsel_i328:
66 ; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7]
68 %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i32> %v1, <8 x i32> %v2
72 define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
73 ; CHECK-LABEL: vsel_double8:
75 ; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm2[1,2,3]
76 ; CHECK-NEXT: vblendpd {{.*#+}} ymm1 = ymm1[0],ymm3[1,2,3]
78 %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x double> %v1, <8 x double> %v2
79 ret <8 x double> %vsel
82 define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {
83 ; CHECK-LABEL: vsel_i648:
85 ; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm2[1,2,3]
86 ; CHECK-NEXT: vblendpd {{.*#+}} ymm1 = ymm1[0],ymm3[1,2,3]
88 %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i64> %v1, <8 x i64> %v2
92 define <4 x double> @vsel_double4(<4 x double> %v1, <4 x double> %v2) {
93 ; CHECK-LABEL: vsel_double4:
95 ; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3]
97 %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x double> %v1, <4 x double> %v2
98 ret <4 x double> %vsel
101 define <2 x double> @testa(<2 x double> %x, <2 x double> %y) {
102 ; CHECK-LABEL: testa:
104 ; CHECK-NEXT: vcmplepd %xmm0, %xmm1, %xmm2
105 ; CHECK-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
107 %max_is_x = fcmp oge <2 x double> %x, %y
108 %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
109 ret <2 x double> %max
112 define <2 x double> @testb(<2 x double> %x, <2 x double> %y) {
113 ; CHECK-LABEL: testb:
115 ; CHECK-NEXT: vcmpnlepd %xmm0, %xmm1, %xmm2
116 ; CHECK-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
118 %min_is_x = fcmp ult <2 x double> %x, %y
119 %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y
120 ret <2 x double> %min
123 ; If we can figure out a blend has a constant mask, we should emit the
124 ; blend instruction with an immediate mask
125 define <4 x double> @constant_blendvpd_avx(<4 x double> %xy, <4 x double> %ab) {
126 ; CHECK-LABEL: constant_blendvpd_avx:
128 ; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3]
130 %1 = select <4 x i1> <i1 false, i1 false, i1 true, i1 false>, <4 x double> %xy, <4 x double> %ab
134 define <8 x float> @constant_blendvps_avx(<8 x float> %xyzw, <8 x float> %abcd) {
135 ; CHECK-LABEL: constant_blendvps_avx:
137 ; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5,6],ymm0[7]
139 %1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true>, <8 x float> %xyzw, <8 x float> %abcd
143 declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>)
144 declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>)
146 ;; 4 tests for shufflevectors that optimize to blend + immediate
147 define <4 x float> @blend_shufflevector_4xfloat(<4 x float> %a, <4 x float> %b) {
148 ; CHECK-LABEL: blend_shufflevector_4xfloat:
150 ; CHECK-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
152 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
156 define <8 x float> @blend_shufflevector_8xfloat(<8 x float> %a, <8 x float> %b) {
157 ; CHECK-LABEL: blend_shufflevector_8xfloat:
159 ; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5],ymm0[6],ymm1[7]
161 %1 = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 12, i32 13, i32 6, i32 15>
165 define <4 x double> @blend_shufflevector_4xdouble(<4 x double> %a, <4 x double> %b) {
166 ; CHECK-LABEL: blend_shufflevector_4xdouble:
168 ; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3]
170 %1 = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
174 define <4 x i64> @blend_shufflevector_4xi64(<4 x i64> %a, <4 x i64> %b) {
175 ; CHECK-LABEL: blend_shufflevector_4xi64:
177 ; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2,3]
179 %1 = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>