1 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
2 ; RUN: llc < %s -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
3 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
5 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
7 ; Verify that the DAG combiner correctly folds bitwise operations across
8 ; shuffles, nested shuffles with undef, pairs of nested shuffles, and other
9 ; basic and always-safe patterns. Also test that the DAG combiner will combine
10 ; target-specific shuffle instructions where reasonable.
12 target triple = "x86_64-unknown-unknown"
14 declare <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32>, i8)
15 declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8)
16 declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8)
18 define <4 x i32> @combine_pshufd1(<4 x i32> %a) {
19 ; ALL-LABEL: combine_pshufd1:
20 ; ALL: # BB#0: # %entry
23 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
24 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 27)
28 define <4 x i32> @combine_pshufd2(<4 x i32> %a) {
29 ; ALL-LABEL: combine_pshufd2:
30 ; ALL: # BB#0: # %entry
33 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
34 %b.cast = bitcast <4 x i32> %b to <8 x i16>
35 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 -28)
36 %c.cast = bitcast <8 x i16> %c to <4 x i32>
37 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
41 define <4 x i32> @combine_pshufd3(<4 x i32> %a) {
42 ; ALL-LABEL: combine_pshufd3:
43 ; ALL: # BB#0: # %entry
46 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
47 %b.cast = bitcast <4 x i32> %b to <8 x i16>
48 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 -28)
49 %c.cast = bitcast <8 x i16> %c to <4 x i32>
50 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
54 define <4 x i32> @combine_pshufd4(<4 x i32> %a) {
55 ; SSE-LABEL: combine_pshufd4:
56 ; SSE: # BB#0: # %entry
57 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
60 ; AVX-LABEL: combine_pshufd4:
61 ; AVX: # BB#0: # %entry
62 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
65 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -31)
66 %b.cast = bitcast <4 x i32> %b to <8 x i16>
67 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 27)
68 %c.cast = bitcast <8 x i16> %c to <4 x i32>
69 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -31)
73 define <4 x i32> @combine_pshufd5(<4 x i32> %a) {
74 ; SSE-LABEL: combine_pshufd5:
75 ; SSE: # BB#0: # %entry
76 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
79 ; AVX-LABEL: combine_pshufd5:
80 ; AVX: # BB#0: # %entry
81 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
84 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -76)
85 %b.cast = bitcast <4 x i32> %b to <8 x i16>
86 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 27)
87 %c.cast = bitcast <8 x i16> %c to <4 x i32>
88 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -76)
92 define <4 x i32> @combine_pshufd6(<4 x i32> %a) {
93 ; SSE-LABEL: combine_pshufd6:
94 ; SSE: # BB#0: # %entry
95 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
98 ; AVX-LABEL: combine_pshufd6:
99 ; AVX: # BB#0: # %entry
100 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
103 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 0)
104 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 8)
108 define <8 x i16> @combine_pshuflw1(<8 x i16> %a) {
109 ; ALL-LABEL: combine_pshuflw1:
110 ; ALL: # BB#0: # %entry
113 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
114 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
118 define <8 x i16> @combine_pshuflw2(<8 x i16> %a) {
119 ; ALL-LABEL: combine_pshuflw2:
120 ; ALL: # BB#0: # %entry
123 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
124 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 -28)
125 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
129 define <8 x i16> @combine_pshuflw3(<8 x i16> %a) {
130 ; SSE-LABEL: combine_pshuflw3:
131 ; SSE: # BB#0: # %entry
132 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
135 ; AVX-LABEL: combine_pshuflw3:
136 ; AVX: # BB#0: # %entry
137 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
140 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
141 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 27)
142 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
146 define <8 x i16> @combine_pshufhw1(<8 x i16> %a) {
147 ; SSE-LABEL: combine_pshufhw1:
148 ; SSE: # BB#0: # %entry
149 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
152 ; AVX-LABEL: combine_pshufhw1:
153 ; AVX: # BB#0: # %entry
154 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
157 %b = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27)
158 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
159 %d = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %c, i8 27)
163 define <4 x i32> @combine_bitwise_ops_test1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
164 ; SSE-LABEL: combine_bitwise_ops_test1:
166 ; SSE-NEXT: pand %xmm1, %xmm0
167 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
170 ; AVX-LABEL: combine_bitwise_ops_test1:
172 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
173 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
175 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
176 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
177 %and = and <4 x i32> %shuf1, %shuf2
181 define <4 x i32> @combine_bitwise_ops_test2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
182 ; SSE-LABEL: combine_bitwise_ops_test2:
184 ; SSE-NEXT: por %xmm1, %xmm0
185 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
188 ; AVX-LABEL: combine_bitwise_ops_test2:
190 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
191 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
193 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
194 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
195 %or = or <4 x i32> %shuf1, %shuf2
199 define <4 x i32> @combine_bitwise_ops_test3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
200 ; SSE-LABEL: combine_bitwise_ops_test3:
202 ; SSE-NEXT: pxor %xmm1, %xmm0
203 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
206 ; AVX-LABEL: combine_bitwise_ops_test3:
208 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
209 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
211 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
212 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
213 %xor = xor <4 x i32> %shuf1, %shuf2
217 define <4 x i32> @combine_bitwise_ops_test4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
218 ; SSE-LABEL: combine_bitwise_ops_test4:
220 ; SSE-NEXT: pand %xmm1, %xmm0
221 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
224 ; AVX-LABEL: combine_bitwise_ops_test4:
226 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
227 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
229 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
230 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
231 %and = and <4 x i32> %shuf1, %shuf2
235 define <4 x i32> @combine_bitwise_ops_test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
236 ; SSE-LABEL: combine_bitwise_ops_test5:
238 ; SSE-NEXT: por %xmm1, %xmm0
239 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
242 ; AVX-LABEL: combine_bitwise_ops_test5:
244 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
245 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
247 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
248 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
249 %or = or <4 x i32> %shuf1, %shuf2
253 define <4 x i32> @combine_bitwise_ops_test6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
254 ; SSE-LABEL: combine_bitwise_ops_test6:
256 ; SSE-NEXT: pxor %xmm1, %xmm0
257 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
260 ; AVX-LABEL: combine_bitwise_ops_test6:
262 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
263 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
265 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
266 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
267 %xor = xor <4 x i32> %shuf1, %shuf2
272 ; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles
273 ; are not performing a swizzle operations.
275 define <4 x i32> @combine_bitwise_ops_test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
276 ; SSE2-LABEL: combine_bitwise_ops_test1b:
278 ; SSE2-NEXT: andps %xmm1, %xmm0
279 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
280 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
283 ; SSSE3-LABEL: combine_bitwise_ops_test1b:
285 ; SSSE3-NEXT: andps %xmm1, %xmm0
286 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
287 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
290 ; SSE41-LABEL: combine_bitwise_ops_test1b:
292 ; SSE41-NEXT: pand %xmm1, %xmm0
293 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
296 ; AVX1-LABEL: combine_bitwise_ops_test1b:
298 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
299 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
302 ; AVX2-LABEL: combine_bitwise_ops_test1b:
304 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
305 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
307 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
308 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
309 %and = and <4 x i32> %shuf1, %shuf2
313 define <4 x i32> @combine_bitwise_ops_test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
314 ; SSE2-LABEL: combine_bitwise_ops_test2b:
316 ; SSE2-NEXT: orps %xmm1, %xmm0
317 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
318 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
321 ; SSSE3-LABEL: combine_bitwise_ops_test2b:
323 ; SSSE3-NEXT: orps %xmm1, %xmm0
324 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
325 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
328 ; SSE41-LABEL: combine_bitwise_ops_test2b:
330 ; SSE41-NEXT: por %xmm1, %xmm0
331 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
334 ; AVX1-LABEL: combine_bitwise_ops_test2b:
336 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
337 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
340 ; AVX2-LABEL: combine_bitwise_ops_test2b:
342 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
343 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
345 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
346 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
347 %or = or <4 x i32> %shuf1, %shuf2
351 define <4 x i32> @combine_bitwise_ops_test3b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
352 ; SSE2-LABEL: combine_bitwise_ops_test3b:
354 ; SSE2-NEXT: xorps %xmm1, %xmm0
355 ; SSE2-NEXT: xorps %xmm1, %xmm1
356 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
357 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
360 ; SSSE3-LABEL: combine_bitwise_ops_test3b:
362 ; SSSE3-NEXT: xorps %xmm1, %xmm0
363 ; SSSE3-NEXT: xorps %xmm1, %xmm1
364 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
365 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
368 ; SSE41-LABEL: combine_bitwise_ops_test3b:
370 ; SSE41-NEXT: pxor %xmm1, %xmm0
371 ; SSE41-NEXT: pxor %xmm1, %xmm1
372 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
375 ; AVX1-LABEL: combine_bitwise_ops_test3b:
377 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
378 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
379 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
382 ; AVX2-LABEL: combine_bitwise_ops_test3b:
384 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
385 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
386 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
388 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
389 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
390 %xor = xor <4 x i32> %shuf1, %shuf2
394 define <4 x i32> @combine_bitwise_ops_test4b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
395 ; SSE2-LABEL: combine_bitwise_ops_test4b:
397 ; SSE2-NEXT: andps %xmm1, %xmm0
398 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
399 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
400 ; SSE2-NEXT: movaps %xmm2, %xmm0
403 ; SSSE3-LABEL: combine_bitwise_ops_test4b:
405 ; SSSE3-NEXT: andps %xmm1, %xmm0
406 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
407 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
408 ; SSSE3-NEXT: movaps %xmm2, %xmm0
411 ; SSE41-LABEL: combine_bitwise_ops_test4b:
413 ; SSE41-NEXT: pand %xmm1, %xmm0
414 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
417 ; AVX1-LABEL: combine_bitwise_ops_test4b:
419 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
420 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
423 ; AVX2-LABEL: combine_bitwise_ops_test4b:
425 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
426 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
428 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
429 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
430 %and = and <4 x i32> %shuf1, %shuf2
434 define <4 x i32> @combine_bitwise_ops_test5b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
435 ; SSE2-LABEL: combine_bitwise_ops_test5b:
437 ; SSE2-NEXT: orps %xmm1, %xmm0
438 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
439 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
440 ; SSE2-NEXT: movaps %xmm2, %xmm0
443 ; SSSE3-LABEL: combine_bitwise_ops_test5b:
445 ; SSSE3-NEXT: orps %xmm1, %xmm0
446 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
447 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
448 ; SSSE3-NEXT: movaps %xmm2, %xmm0
451 ; SSE41-LABEL: combine_bitwise_ops_test5b:
453 ; SSE41-NEXT: por %xmm1, %xmm0
454 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
457 ; AVX1-LABEL: combine_bitwise_ops_test5b:
459 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
460 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
463 ; AVX2-LABEL: combine_bitwise_ops_test5b:
465 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
466 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
468 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
469 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
470 %or = or <4 x i32> %shuf1, %shuf2
474 define <4 x i32> @combine_bitwise_ops_test6b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
475 ; SSE2-LABEL: combine_bitwise_ops_test6b:
477 ; SSE2-NEXT: xorps %xmm1, %xmm0
478 ; SSE2-NEXT: xorps %xmm1, %xmm1
479 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
480 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
481 ; SSE2-NEXT: movaps %xmm1, %xmm0
484 ; SSSE3-LABEL: combine_bitwise_ops_test6b:
486 ; SSSE3-NEXT: xorps %xmm1, %xmm0
487 ; SSSE3-NEXT: xorps %xmm1, %xmm1
488 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
489 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
490 ; SSSE3-NEXT: movaps %xmm1, %xmm0
493 ; SSE41-LABEL: combine_bitwise_ops_test6b:
495 ; SSE41-NEXT: pxor %xmm1, %xmm0
496 ; SSE41-NEXT: pxor %xmm1, %xmm1
497 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
500 ; AVX1-LABEL: combine_bitwise_ops_test6b:
502 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
503 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
504 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
507 ; AVX2-LABEL: combine_bitwise_ops_test6b:
509 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
510 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
511 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
513 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
514 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
515 %xor = xor <4 x i32> %shuf1, %shuf2
519 define <4 x i32> @combine_bitwise_ops_test1c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
520 ; SSE-LABEL: combine_bitwise_ops_test1c:
522 ; SSE-NEXT: andps %xmm1, %xmm0
523 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
526 ; AVX-LABEL: combine_bitwise_ops_test1c:
528 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
529 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
531 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
532 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
533 %and = and <4 x i32> %shuf1, %shuf2
537 define <4 x i32> @combine_bitwise_ops_test2c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
538 ; SSE-LABEL: combine_bitwise_ops_test2c:
540 ; SSE-NEXT: orps %xmm1, %xmm0
541 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
544 ; AVX-LABEL: combine_bitwise_ops_test2c:
546 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
547 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
549 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
550 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
551 %or = or <4 x i32> %shuf1, %shuf2
555 define <4 x i32> @combine_bitwise_ops_test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
556 ; SSE2-LABEL: combine_bitwise_ops_test3c:
558 ; SSE2-NEXT: xorps %xmm1, %xmm0
559 ; SSE2-NEXT: xorps %xmm1, %xmm1
560 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
563 ; SSSE3-LABEL: combine_bitwise_ops_test3c:
565 ; SSSE3-NEXT: xorps %xmm1, %xmm0
566 ; SSSE3-NEXT: xorps %xmm1, %xmm1
567 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
570 ; SSE41-LABEL: combine_bitwise_ops_test3c:
572 ; SSE41-NEXT: xorps %xmm1, %xmm0
573 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero
576 ; AVX-LABEL: combine_bitwise_ops_test3c:
578 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
579 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero
581 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
582 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
583 %xor = xor <4 x i32> %shuf1, %shuf2
587 define <4 x i32> @combine_bitwise_ops_test4c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
588 ; SSE-LABEL: combine_bitwise_ops_test4c:
590 ; SSE-NEXT: andps %xmm1, %xmm0
591 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
592 ; SSE-NEXT: movaps %xmm2, %xmm0
595 ; AVX-LABEL: combine_bitwise_ops_test4c:
597 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
598 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
600 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
601 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
602 %and = and <4 x i32> %shuf1, %shuf2
606 define <4 x i32> @combine_bitwise_ops_test5c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
607 ; SSE-LABEL: combine_bitwise_ops_test5c:
609 ; SSE-NEXT: orps %xmm1, %xmm0
610 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
611 ; SSE-NEXT: movaps %xmm2, %xmm0
614 ; AVX-LABEL: combine_bitwise_ops_test5c:
616 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
617 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
619 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
620 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
621 %or = or <4 x i32> %shuf1, %shuf2
625 define <4 x i32> @combine_bitwise_ops_test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
626 ; SSE-LABEL: combine_bitwise_ops_test6c:
628 ; SSE-NEXT: xorps %xmm1, %xmm0
629 ; SSE-NEXT: xorps %xmm1, %xmm1
630 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
631 ; SSE-NEXT: movaps %xmm1, %xmm0
634 ; AVX-LABEL: combine_bitwise_ops_test6c:
636 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
637 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
638 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[1,3]
640 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
641 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
642 %xor = xor <4 x i32> %shuf1, %shuf2
646 define <4 x i32> @combine_nested_undef_test1(<4 x i32> %A, <4 x i32> %B) {
647 ; SSE-LABEL: combine_nested_undef_test1:
649 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
652 ; AVX-LABEL: combine_nested_undef_test1:
654 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
656 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
657 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
661 define <4 x i32> @combine_nested_undef_test2(<4 x i32> %A, <4 x i32> %B) {
662 ; SSE-LABEL: combine_nested_undef_test2:
664 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
667 ; AVX-LABEL: combine_nested_undef_test2:
669 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
671 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
672 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
676 define <4 x i32> @combine_nested_undef_test3(<4 x i32> %A, <4 x i32> %B) {
677 ; SSE-LABEL: combine_nested_undef_test3:
679 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
682 ; AVX-LABEL: combine_nested_undef_test3:
684 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
686 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
687 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
691 define <4 x i32> @combine_nested_undef_test4(<4 x i32> %A, <4 x i32> %B) {
692 ; SSE-LABEL: combine_nested_undef_test4:
694 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
697 ; AVX1-LABEL: combine_nested_undef_test4:
699 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
702 ; AVX2-LABEL: combine_nested_undef_test4:
704 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
706 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 7, i32 1>
707 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 3>
711 define <4 x i32> @combine_nested_undef_test5(<4 x i32> %A, <4 x i32> %B) {
712 ; SSE-LABEL: combine_nested_undef_test5:
714 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
717 ; AVX-LABEL: combine_nested_undef_test5:
719 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
721 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 5, i32 5, i32 2, i32 3>
722 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 4, i32 3>
726 define <4 x i32> @combine_nested_undef_test6(<4 x i32> %A, <4 x i32> %B) {
727 ; SSE-LABEL: combine_nested_undef_test6:
729 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
732 ; AVX-LABEL: combine_nested_undef_test6:
734 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
736 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
737 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 4>
741 define <4 x i32> @combine_nested_undef_test7(<4 x i32> %A, <4 x i32> %B) {
742 ; SSE-LABEL: combine_nested_undef_test7:
744 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
747 ; AVX-LABEL: combine_nested_undef_test7:
749 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
751 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
752 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
756 define <4 x i32> @combine_nested_undef_test8(<4 x i32> %A, <4 x i32> %B) {
757 ; SSE-LABEL: combine_nested_undef_test8:
759 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
762 ; AVX-LABEL: combine_nested_undef_test8:
764 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
766 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
767 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
771 define <4 x i32> @combine_nested_undef_test9(<4 x i32> %A, <4 x i32> %B) {
772 ; SSE-LABEL: combine_nested_undef_test9:
774 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
777 ; AVX-LABEL: combine_nested_undef_test9:
779 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
781 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 2, i32 5>
782 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
786 define <4 x i32> @combine_nested_undef_test10(<4 x i32> %A, <4 x i32> %B) {
787 ; SSE-LABEL: combine_nested_undef_test10:
789 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
792 ; AVX-LABEL: combine_nested_undef_test10:
794 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
796 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 5>
797 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 4>
801 define <4 x i32> @combine_nested_undef_test11(<4 x i32> %A, <4 x i32> %B) {
802 ; SSE-LABEL: combine_nested_undef_test11:
804 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
807 ; AVX-LABEL: combine_nested_undef_test11:
809 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
811 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 2, i32 5, i32 4>
812 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 0>
816 define <4 x i32> @combine_nested_undef_test12(<4 x i32> %A, <4 x i32> %B) {
817 ; SSE-LABEL: combine_nested_undef_test12:
819 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
822 ; AVX1-LABEL: combine_nested_undef_test12:
824 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
827 ; AVX2-LABEL: combine_nested_undef_test12:
829 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
831 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 0, i32 2, i32 4>
832 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 0, i32 4>
836 ; The following pair of shuffles is folded into vector %A.
837 define <4 x i32> @combine_nested_undef_test13(<4 x i32> %A, <4 x i32> %B) {
838 ; ALL-LABEL: combine_nested_undef_test13:
841 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 4, i32 2, i32 6>
842 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 0, i32 2, i32 4>
846 ; The following pair of shuffles is folded into vector %B.
847 define <4 x i32> @combine_nested_undef_test14(<4 x i32> %A, <4 x i32> %B) {
848 ; SSE-LABEL: combine_nested_undef_test14:
850 ; SSE-NEXT: movaps %xmm1, %xmm0
853 ; AVX-LABEL: combine_nested_undef_test14:
855 ; AVX-NEXT: vmovaps %xmm1, %xmm0
857 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
858 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 4, i32 1, i32 4>
863 ; Verify that we don't optimize the following cases. We expect more than one shuffle.
865 ; FIXME: Many of these already don't make sense, and the rest should stop
866 ; making sense with th enew vector shuffle lowering. Revisit at least testing for
869 define <4 x i32> @combine_nested_undef_test15(<4 x i32> %A, <4 x i32> %B) {
870 ; SSE-LABEL: combine_nested_undef_test15:
872 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
873 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,1]
874 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
877 ; AVX-LABEL: combine_nested_undef_test15:
879 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
880 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[3,1]
881 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
883 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
884 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
888 define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
889 ; SSE2-LABEL: combine_nested_undef_test16:
891 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
892 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
893 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
896 ; SSSE3-LABEL: combine_nested_undef_test16:
898 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
899 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
900 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
903 ; SSE41-LABEL: combine_nested_undef_test16:
905 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
906 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
909 ; AVX1-LABEL: combine_nested_undef_test16:
911 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
912 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
915 ; AVX2-LABEL: combine_nested_undef_test16:
917 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
918 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
920 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
921 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
925 define <4 x i32> @combine_nested_undef_test17(<4 x i32> %A, <4 x i32> %B) {
926 ; SSE-LABEL: combine_nested_undef_test17:
928 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
929 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
930 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
933 ; AVX-LABEL: combine_nested_undef_test17:
935 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
936 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
937 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
939 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
940 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
944 define <4 x i32> @combine_nested_undef_test18(<4 x i32> %A, <4 x i32> %B) {
945 ; SSE-LABEL: combine_nested_undef_test18:
947 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
950 ; AVX-LABEL: combine_nested_undef_test18:
952 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
954 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
955 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 3>
959 define <4 x i32> @combine_nested_undef_test19(<4 x i32> %A, <4 x i32> %B) {
960 ; SSE-LABEL: combine_nested_undef_test19:
962 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
963 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
964 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
967 ; AVX-LABEL: combine_nested_undef_test19:
969 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
970 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
971 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
973 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
974 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
978 define <4 x i32> @combine_nested_undef_test20(<4 x i32> %A, <4 x i32> %B) {
979 ; SSE-LABEL: combine_nested_undef_test20:
981 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
982 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
985 ; AVX-LABEL: combine_nested_undef_test20:
987 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
988 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
990 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
991 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
995 define <4 x i32> @combine_nested_undef_test21(<4 x i32> %A, <4 x i32> %B) {
996 ; SSE-LABEL: combine_nested_undef_test21:
998 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
999 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
1000 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1003 ; AVX-LABEL: combine_nested_undef_test21:
1005 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
1006 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
1007 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,3]
1009 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
1010 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1015 ; Test that we correctly combine shuffles according to rule
1016 ; shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
1018 define <4 x i32> @combine_nested_undef_test22(<4 x i32> %A, <4 x i32> %B) {
1019 ; SSE-LABEL: combine_nested_undef_test22:
1021 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1024 ; AVX-LABEL: combine_nested_undef_test22:
1026 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1028 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1029 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 3>
1033 define <4 x i32> @combine_nested_undef_test23(<4 x i32> %A, <4 x i32> %B) {
1034 ; SSE-LABEL: combine_nested_undef_test23:
1036 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1039 ; AVX-LABEL: combine_nested_undef_test23:
1041 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1043 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1044 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1048 define <4 x i32> @combine_nested_undef_test24(<4 x i32> %A, <4 x i32> %B) {
1049 ; SSE-LABEL: combine_nested_undef_test24:
1051 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1054 ; AVX-LABEL: combine_nested_undef_test24:
1056 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1058 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1059 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 4>
1063 define <4 x i32> @combine_nested_undef_test25(<4 x i32> %A, <4 x i32> %B) {
1064 ; SSE-LABEL: combine_nested_undef_test25:
1066 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1069 ; AVX1-LABEL: combine_nested_undef_test25:
1071 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1074 ; AVX2-LABEL: combine_nested_undef_test25:
1076 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1078 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 5, i32 2, i32 4>
1079 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 3, i32 1>
1083 define <4 x i32> @combine_nested_undef_test26(<4 x i32> %A, <4 x i32> %B) {
1084 ; SSE-LABEL: combine_nested_undef_test26:
1086 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1089 ; AVX-LABEL: combine_nested_undef_test26:
1091 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1093 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 6, i32 7>
1094 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
1098 define <4 x i32> @combine_nested_undef_test27(<4 x i32> %A, <4 x i32> %B) {
1099 ; SSE-LABEL: combine_nested_undef_test27:
1101 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1104 ; AVX1-LABEL: combine_nested_undef_test27:
1106 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1109 ; AVX2-LABEL: combine_nested_undef_test27:
1111 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1113 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 2, i32 1, i32 5, i32 4>
1114 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
1118 define <4 x i32> @combine_nested_undef_test28(<4 x i32> %A, <4 x i32> %B) {
1119 ; SSE-LABEL: combine_nested_undef_test28:
1121 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1124 ; AVX-LABEL: combine_nested_undef_test28:
1126 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1128 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
1129 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 3, i32 2>
1133 define <4 x float> @combine_test1(<4 x float> %a, <4 x float> %b) {
1134 ; SSE-LABEL: combine_test1:
1136 ; SSE-NEXT: movaps %xmm1, %xmm0
1139 ; AVX-LABEL: combine_test1:
1141 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1143 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1144 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1148 define <4 x float> @combine_test2(<4 x float> %a, <4 x float> %b) {
1149 ; SSE2-LABEL: combine_test2:
1151 ; SSE2-NEXT: movss %xmm0, %xmm1
1152 ; SSE2-NEXT: movaps %xmm1, %xmm0
1155 ; SSSE3-LABEL: combine_test2:
1157 ; SSSE3-NEXT: movss %xmm0, %xmm1
1158 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1161 ; SSE41-LABEL: combine_test2:
1163 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1166 ; AVX-LABEL: combine_test2:
1168 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1170 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1171 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1175 define <4 x float> @combine_test3(<4 x float> %a, <4 x float> %b) {
1176 ; SSE-LABEL: combine_test3:
1178 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1181 ; AVX-LABEL: combine_test3:
1183 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1185 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1186 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1190 define <4 x float> @combine_test4(<4 x float> %a, <4 x float> %b) {
1191 ; SSE-LABEL: combine_test4:
1193 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1194 ; SSE-NEXT: movapd %xmm1, %xmm0
1197 ; AVX-LABEL: combine_test4:
1199 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1201 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1202 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1206 define <4 x float> @combine_test5(<4 x float> %a, <4 x float> %b) {
1207 ; SSE2-LABEL: combine_test5:
1209 ; SSE2-NEXT: movaps %xmm1, %xmm2
1210 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1211 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1212 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1213 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1214 ; SSE2-NEXT: movaps %xmm2, %xmm0
1217 ; SSSE3-LABEL: combine_test5:
1219 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1220 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1221 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1222 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1223 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1224 ; SSSE3-NEXT: movaps %xmm2, %xmm0
1227 ; SSE41-LABEL: combine_test5:
1229 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1232 ; AVX-LABEL: combine_test5:
1234 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1236 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1237 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1241 define <4 x i32> @combine_test6(<4 x i32> %a, <4 x i32> %b) {
1242 ; SSE-LABEL: combine_test6:
1244 ; SSE-NEXT: movaps %xmm1, %xmm0
1247 ; AVX-LABEL: combine_test6:
1249 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1251 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1252 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1256 define <4 x i32> @combine_test7(<4 x i32> %a, <4 x i32> %b) {
1257 ; SSE2-LABEL: combine_test7:
1259 ; SSE2-NEXT: movss %xmm0, %xmm1
1260 ; SSE2-NEXT: movaps %xmm1, %xmm0
1263 ; SSSE3-LABEL: combine_test7:
1265 ; SSSE3-NEXT: movss %xmm0, %xmm1
1266 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1269 ; SSE41-LABEL: combine_test7:
1271 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1274 ; AVX1-LABEL: combine_test7:
1276 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1279 ; AVX2-LABEL: combine_test7:
1281 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1283 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1284 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1288 define <4 x i32> @combine_test8(<4 x i32> %a, <4 x i32> %b) {
1289 ; SSE-LABEL: combine_test8:
1291 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1294 ; AVX-LABEL: combine_test8:
1296 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1298 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1299 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1303 define <4 x i32> @combine_test9(<4 x i32> %a, <4 x i32> %b) {
1304 ; SSE-LABEL: combine_test9:
1306 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1307 ; SSE-NEXT: movdqa %xmm1, %xmm0
1310 ; AVX-LABEL: combine_test9:
1312 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1314 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1315 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1319 define <4 x i32> @combine_test10(<4 x i32> %a, <4 x i32> %b) {
1320 ; SSE2-LABEL: combine_test10:
1322 ; SSE2-NEXT: movaps %xmm1, %xmm2
1323 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1324 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1325 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1326 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1327 ; SSE2-NEXT: movaps %xmm2, %xmm0
1330 ; SSSE3-LABEL: combine_test10:
1332 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1333 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1334 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1335 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1336 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1337 ; SSSE3-NEXT: movaps %xmm2, %xmm0
1340 ; SSE41-LABEL: combine_test10:
1342 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1345 ; AVX1-LABEL: combine_test10:
1347 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1350 ; AVX2-LABEL: combine_test10:
1352 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1354 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1355 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1359 define <4 x float> @combine_test11(<4 x float> %a, <4 x float> %b) {
1360 ; ALL-LABEL: combine_test11:
1363 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1364 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1368 define <4 x float> @combine_test12(<4 x float> %a, <4 x float> %b) {
1369 ; SSE2-LABEL: combine_test12:
1371 ; SSE2-NEXT: movss %xmm0, %xmm1
1372 ; SSE2-NEXT: movaps %xmm1, %xmm0
1375 ; SSSE3-LABEL: combine_test12:
1377 ; SSSE3-NEXT: movss %xmm0, %xmm1
1378 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1381 ; SSE41-LABEL: combine_test12:
1383 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1386 ; AVX-LABEL: combine_test12:
1388 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1390 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1391 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1395 define <4 x float> @combine_test13(<4 x float> %a, <4 x float> %b) {
1396 ; SSE-LABEL: combine_test13:
1398 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1401 ; AVX-LABEL: combine_test13:
1403 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1405 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1406 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1410 define <4 x float> @combine_test14(<4 x float> %a, <4 x float> %b) {
1411 ; SSE-LABEL: combine_test14:
1413 ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1416 ; AVX-LABEL: combine_test14:
1418 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1420 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1421 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1425 define <4 x float> @combine_test15(<4 x float> %a, <4 x float> %b) {
1426 ; SSE2-LABEL: combine_test15:
1428 ; SSE2-NEXT: movaps %xmm0, %xmm2
1429 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1430 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1431 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1432 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1435 ; SSSE3-LABEL: combine_test15:
1437 ; SSSE3-NEXT: movaps %xmm0, %xmm2
1438 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1439 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1440 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1441 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1444 ; SSE41-LABEL: combine_test15:
1446 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1449 ; AVX-LABEL: combine_test15:
1451 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1453 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1454 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1458 define <4 x i32> @combine_test16(<4 x i32> %a, <4 x i32> %b) {
1459 ; ALL-LABEL: combine_test16:
1462 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1463 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1467 define <4 x i32> @combine_test17(<4 x i32> %a, <4 x i32> %b) {
1468 ; SSE2-LABEL: combine_test17:
1470 ; SSE2-NEXT: movss %xmm0, %xmm1
1471 ; SSE2-NEXT: movaps %xmm1, %xmm0
1474 ; SSSE3-LABEL: combine_test17:
1476 ; SSSE3-NEXT: movss %xmm0, %xmm1
1477 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1480 ; SSE41-LABEL: combine_test17:
1482 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1485 ; AVX1-LABEL: combine_test17:
1487 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1490 ; AVX2-LABEL: combine_test17:
1492 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1494 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1495 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1499 define <4 x i32> @combine_test18(<4 x i32> %a, <4 x i32> %b) {
1500 ; SSE-LABEL: combine_test18:
1502 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1505 ; AVX-LABEL: combine_test18:
1507 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1509 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1510 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1514 define <4 x i32> @combine_test19(<4 x i32> %a, <4 x i32> %b) {
1515 ; SSE-LABEL: combine_test19:
1517 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1520 ; AVX-LABEL: combine_test19:
1522 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1524 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1525 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1529 define <4 x i32> @combine_test20(<4 x i32> %a, <4 x i32> %b) {
1530 ; SSE2-LABEL: combine_test20:
1532 ; SSE2-NEXT: movaps %xmm0, %xmm2
1533 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1534 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1535 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1536 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1539 ; SSSE3-LABEL: combine_test20:
1541 ; SSSE3-NEXT: movaps %xmm0, %xmm2
1542 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1543 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1544 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1545 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1548 ; SSE41-LABEL: combine_test20:
1550 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1553 ; AVX1-LABEL: combine_test20:
1555 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1558 ; AVX2-LABEL: combine_test20:
1560 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1562 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1563 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1567 define <4 x i32> @combine_test21(<8 x i32> %a, <4 x i32>* %ptr) {
1568 ; SSE-LABEL: combine_test21:
1570 ; SSE-NEXT: movdqa %xmm0, %xmm2
1571 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
1572 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1573 ; SSE-NEXT: movdqa %xmm2,
1576 ; AVX1-LABEL: combine_test21:
1578 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
1579 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm0[0],xmm1[0]
1580 ; AVX1-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1581 ; AVX1-NEXT: movdqa %xmm2,
1582 ; AVX1-NEXT: vzeroupper
1585 ; AVX2-LABEL: combine_test21:
1587 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
1588 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm0[0],xmm1[0]
1589 ; AVX2-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1590 ; AVX2-NEXT: movdqa %xmm2,
1591 ; AVX2-NEXT: vzeroupper
1593 %1 = shufflevector <8 x i32> %a, <8 x i32> %a, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1594 %2 = shufflevector <8 x i32> %a, <8 x i32> %a, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
1595 store <4 x i32> %1, <4 x i32>* %ptr, align 16
1599 define <8 x float> @combine_test22(<2 x float>* %a, <2 x float>* %b) {
1600 ; SSE-LABEL: combine_test22:
1602 ; SSE-NEXT: movq (%rdi), %xmm0
1603 ; SSE-NEXT: movhpd (%rsi), %xmm0
1606 ; AVX1-LABEL: combine_test22:
1608 ; AVX1-NEXT: vmovq (%rdi), %xmm0
1609 ; AVX1-NEXT: vmovhpd (%rsi), %xmm0, %xmm0
1612 ; Current AVX2 lowering of this is still awful, not adding a test case.
1613 %1 = load <2 x float>* %a, align 8
1614 %2 = load <2 x float>* %b, align 8
1615 %3 = shufflevector <2 x float> %1, <2 x float> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
1619 ; Check some negative cases.
1620 ; FIXME: Do any of these really make sense? Are they redundant with the above tests?
1622 define <4 x float> @combine_test1b(<4 x float> %a, <4 x float> %b) {
1623 ; SSE-LABEL: combine_test1b:
1625 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1,2,0]
1626 ; SSE-NEXT: movaps %xmm1, %xmm0
1629 ; AVX-LABEL: combine_test1b:
1631 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm1[0,1,2,0]
1633 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1634 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 0>
1638 define <4 x float> @combine_test2b(<4 x float> %a, <4 x float> %b) {
1639 ; SSE2-LABEL: combine_test2b:
1641 ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0,0]
1642 ; SSE2-NEXT: movaps %xmm1, %xmm0
1645 ; SSSE3-LABEL: combine_test2b:
\r
1647 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
\r
1648 ; SSSE3-NEXT: retq
\r
1650 ; SSE41-LABEL: combine_test2b:
\r
1652 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
\r
1653 ; SSE41-NEXT: retq
\r
1655 ; AVX-LABEL: combine_test2b:
\r
1657 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm1[0,0]
\r
1659 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
\r
1660 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 0, i32 5>
\r
1664 define <4 x float> @combine_test3b(<4 x float> %a, <4 x float> %b) {
1665 ; SSE-LABEL: combine_test3b:
1667 ; SSE-NEXT: movaps %xmm1, %xmm2
1668 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[3,0]
1669 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,2]
1670 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[3,3]
1671 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1674 ; AVX-LABEL: combine_test3b:
1676 ; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[2,0],xmm0[3,0]
1677 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,2]
1678 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[3,3]
1679 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1681 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 6, i32 3>
1682 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 7>
1686 define <4 x float> @combine_test4b(<4 x float> %a, <4 x float> %b) {
1687 ; SSE-LABEL: combine_test4b:
1689 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
1690 ; SSE-NEXT: movaps %xmm1, %xmm0
1693 ; AVX-LABEL: combine_test4b:
1695 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm1[1,1,2,3]
1697 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1698 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 5, i32 5, i32 2, i32 7>
1703 ; Verify that we correctly fold shuffles even when we use illegal vector types.
1705 define <4 x i8> @combine_test1c(<4 x i8>* %a, <4 x i8>* %b) {
1706 ; SSE2-LABEL: combine_test1c:
1708 ; SSE2-NEXT: movd (%rdi), %xmm1
1709 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1710 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1711 ; SSE2-NEXT: movd (%rsi), %xmm0
1712 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1713 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1714 ; SSE2-NEXT: movss %xmm1, %xmm0
1717 ; SSSE3-LABEL: combine_test1c:
1719 ; SSSE3-NEXT: movd (%rdi), %xmm1
1720 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1721 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1722 ; SSSE3-NEXT: movd (%rsi), %xmm0
1723 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1724 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1725 ; SSSE3-NEXT: movss %xmm1, %xmm0
1728 ; SSE41-LABEL: combine_test1c:
1730 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1731 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1732 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
1735 ; AVX1-LABEL: combine_test1c:
1737 ; AVX1-NEXT: vpmovzxbd (%rdi), %xmm0
1738 ; AVX1-NEXT: vpmovzxbd (%rsi), %xmm1
1739 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1742 ; AVX2-LABEL: combine_test1c:
1744 ; AVX2-NEXT: vpmovzxbd (%rdi), %xmm0
1745 ; AVX2-NEXT: vpmovzxbd (%rsi), %xmm1
1746 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1748 %A = load <4 x i8>* %a
1749 %B = load <4 x i8>* %b
1750 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1751 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1755 define <4 x i8> @combine_test2c(<4 x i8>* %a, <4 x i8>* %b) {
1756 ; SSE2-LABEL: combine_test2c:
1758 ; SSE2-NEXT: movd (%rdi), %xmm0
1759 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1760 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1761 ; SSE2-NEXT: movd (%rsi), %xmm1
1762 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1763 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1764 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1767 ; SSSE3-LABEL: combine_test2c:
1769 ; SSSE3-NEXT: movd (%rdi), %xmm0
1770 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1771 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1772 ; SSSE3-NEXT: movd (%rsi), %xmm1
1773 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1774 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1775 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1778 ; SSE41-LABEL: combine_test2c:
1780 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm0
1781 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm1
1782 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1785 ; AVX-LABEL: combine_test2c:
1787 ; AVX-NEXT: vpmovzxbd (%rdi), %xmm0
1788 ; AVX-NEXT: vpmovzxbd (%rsi), %xmm1
1789 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1791 %A = load <4 x i8>* %a
1792 %B = load <4 x i8>* %b
1793 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 1, i32 5>
1794 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1798 define <4 x i8> @combine_test3c(<4 x i8>* %a, <4 x i8>* %b) {
1799 ; SSE2-LABEL: combine_test3c:
1801 ; SSE2-NEXT: movd (%rdi), %xmm1
1802 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1803 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1804 ; SSE2-NEXT: movd (%rsi), %xmm0
1805 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1806 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1807 ; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1810 ; SSSE3-LABEL: combine_test3c:
1812 ; SSSE3-NEXT: movd (%rdi), %xmm1
1813 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1814 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1815 ; SSSE3-NEXT: movd (%rsi), %xmm0
1816 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1817 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1818 ; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1821 ; SSE41-LABEL: combine_test3c:
1823 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1824 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1825 ; SSE41-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1828 ; AVX-LABEL: combine_test3c:
1830 ; AVX-NEXT: vpmovzxbd (%rdi), %xmm0
1831 ; AVX-NEXT: vpmovzxbd (%rsi), %xmm1
1832 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1834 %A = load <4 x i8>* %a
1835 %B = load <4 x i8>* %b
1836 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1837 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1841 define <4 x i8> @combine_test4c(<4 x i8>* %a, <4 x i8>* %b) {
1842 ; SSE2-LABEL: combine_test4c:
1844 ; SSE2-NEXT: movd (%rdi), %xmm1
1845 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1846 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1847 ; SSE2-NEXT: movd (%rsi), %xmm2
1848 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
1849 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
1850 ; SSE2-NEXT: movdqa %xmm2, %xmm0
1851 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1852 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1853 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm0[2,0]
1854 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
1857 ; SSSE3-LABEL: combine_test4c:
1859 ; SSSE3-NEXT: movd (%rdi), %xmm1
1860 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1861 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1862 ; SSSE3-NEXT: movd (%rsi), %xmm2
1863 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
1864 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
1865 ; SSSE3-NEXT: movdqa %xmm2, %xmm0
1866 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1867 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1868 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm0[2,0]
1869 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
1872 ; SSE41-LABEL: combine_test4c:
1874 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1875 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1876 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1879 ; AVX1-LABEL: combine_test4c:
1881 ; AVX1-NEXT: vpmovzxbd (%rdi), %xmm0
1882 ; AVX1-NEXT: vpmovzxbd (%rsi), %xmm1
1883 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1886 ; AVX2-LABEL: combine_test4c:
1888 ; AVX2-NEXT: vpmovzxbd (%rdi), %xmm0
1889 ; AVX2-NEXT: vpmovzxbd (%rsi), %xmm1
1890 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1892 %A = load <4 x i8>* %a
1893 %B = load <4 x i8>* %b
1894 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1895 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1900 ; The following test cases are generated from this C++ code
1902 ;__m128 blend_01(__m128 a, __m128 b)
1905 ; s = _mm_blend_ps( s, b, 1<<0 );
1906 ; s = _mm_blend_ps( s, b, 1<<1 );
1910 ;__m128 blend_02(__m128 a, __m128 b)
1913 ; s = _mm_blend_ps( s, b, 1<<0 );
1914 ; s = _mm_blend_ps( s, b, 1<<2 );
1918 ;__m128 blend_123(__m128 a, __m128 b)
1921 ; s = _mm_blend_ps( s, b, 1<<1 );
1922 ; s = _mm_blend_ps( s, b, 1<<2 );
1923 ; s = _mm_blend_ps( s, b, 1<<3 );
1927 ; Ideally, we should collapse the following shuffles into a single one.
1929 define <4 x float> @combine_blend_01(<4 x float> %a, <4 x float> %b) {
1930 ; SSE2-LABEL: combine_blend_01:
1932 ; SSE2-NEXT: movsd %xmm1, %xmm0
1935 ; SSSE3-LABEL: combine_blend_01:
1937 ; SSSE3-NEXT: movsd %xmm1, %xmm0
1940 ; SSE41-LABEL: combine_blend_01:
1942 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1945 ; AVX-LABEL: combine_blend_01:
1947 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1949 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 undef, i32 2, i32 3>
1950 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1951 ret <4 x float> %shuffle6
1954 define <4 x float> @combine_blend_02(<4 x float> %a, <4 x float> %b) {
1955 ; SSE2-LABEL: combine_blend_02:
1957 ; SSE2-NEXT: movss %xmm1, %xmm0
1958 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1959 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1962 ; SSSE3-LABEL: combine_blend_02:
1964 ; SSSE3-NEXT: movss %xmm1, %xmm0
1965 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1966 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1969 ; SSE41-LABEL: combine_blend_02:
1971 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1974 ; AVX-LABEL: combine_blend_02:
1976 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1978 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 undef, i32 3>
1979 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1980 ret <4 x float> %shuffle6
1983 define <4 x float> @combine_blend_123(<4 x float> %a, <4 x float> %b) {
1984 ; SSE2-LABEL: combine_blend_123:
1986 ; SSE2-NEXT: movss %xmm0, %xmm1
1987 ; SSE2-NEXT: movaps %xmm1, %xmm0
1990 ; SSSE3-LABEL: combine_blend_123:
1992 ; SSSE3-NEXT: movss %xmm0, %xmm1
1993 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1996 ; SSE41-LABEL: combine_blend_123:
1998 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
2001 ; AVX-LABEL: combine_blend_123:
2003 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
2005 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
2006 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
2007 %shuffle12 = shufflevector <4 x float> %shuffle6, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
2008 ret <4 x float> %shuffle12
2011 define <4 x i32> @combine_test_movhl_1(<4 x i32> %a, <4 x i32> %b) {
2012 ; SSE-LABEL: combine_test_movhl_1:
2014 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2015 ; SSE-NEXT: movdqa %xmm1, %xmm0
2018 ; AVX-LABEL: combine_test_movhl_1:
2020 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2022 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 7, i32 5, i32 3>
2023 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 0, i32 3>
2027 define <4 x i32> @combine_test_movhl_2(<4 x i32> %a, <4 x i32> %b) {
2028 ; SSE-LABEL: combine_test_movhl_2:
2030 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2031 ; SSE-NEXT: movdqa %xmm1, %xmm0
2034 ; AVX-LABEL: combine_test_movhl_2:
2036 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2038 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 0, i32 3, i32 6>
2039 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 3, i32 7, i32 0, i32 2>
2043 define <4 x i32> @combine_test_movhl_3(<4 x i32> %a, <4 x i32> %b) {
2044 ; SSE-LABEL: combine_test_movhl_3:
2046 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2047 ; SSE-NEXT: movdqa %xmm1, %xmm0
2050 ; AVX-LABEL: combine_test_movhl_3:
2052 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2054 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 6, i32 3, i32 2>
2055 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 0, i32 3, i32 2>
2060 ; Verify that we fold shuffles according to rule:
2061 ; (shuffle(shuffle A, Undef, M0), B, M1) -> (shuffle A, B, M2)
2063 define <4 x float> @combine_undef_input_test1(<4 x float> %a, <4 x float> %b) {
2064 ; SSE2-LABEL: combine_undef_input_test1:
2066 ; SSE2-NEXT: movsd %xmm1, %xmm0
2069 ; SSSE3-LABEL: combine_undef_input_test1:
2071 ; SSSE3-NEXT: movsd %xmm1, %xmm0
2074 ; SSE41-LABEL: combine_undef_input_test1:
2076 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2079 ; AVX-LABEL: combine_undef_input_test1:
2081 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2083 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2084 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2088 define <4 x float> @combine_undef_input_test2(<4 x float> %a, <4 x float> %b) {
2089 ; SSE-LABEL: combine_undef_input_test2:
2091 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2094 ; AVX-LABEL: combine_undef_input_test2:
2096 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2098 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2099 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2103 define <4 x float> @combine_undef_input_test3(<4 x float> %a, <4 x float> %b) {
2104 ; SSE-LABEL: combine_undef_input_test3:
2106 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2109 ; AVX-LABEL: combine_undef_input_test3:
2111 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2113 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2114 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2118 define <4 x float> @combine_undef_input_test4(<4 x float> %a, <4 x float> %b) {
2119 ; SSE-LABEL: combine_undef_input_test4:
2121 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2122 ; SSE-NEXT: movapd %xmm1, %xmm0
2125 ; AVX-LABEL: combine_undef_input_test4:
2127 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2129 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2130 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2134 define <4 x float> @combine_undef_input_test5(<4 x float> %a, <4 x float> %b) {
2135 ; SSE2-LABEL: combine_undef_input_test5:
2137 ; SSE2-NEXT: movsd %xmm0, %xmm1
2138 ; SSE2-NEXT: movaps %xmm1, %xmm0
2141 ; SSSE3-LABEL: combine_undef_input_test5:
2143 ; SSSE3-NEXT: movsd %xmm0, %xmm1
2144 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2147 ; SSE41-LABEL: combine_undef_input_test5:
2149 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2152 ; AVX-LABEL: combine_undef_input_test5:
2154 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2156 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2157 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2162 ; Verify that we fold shuffles according to rule:
2163 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2165 define <4 x float> @combine_undef_input_test6(<4 x float> %a) {
2166 ; ALL-LABEL: combine_undef_input_test6:
2169 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2170 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2174 define <4 x float> @combine_undef_input_test7(<4 x float> %a) {
2175 ; SSE2-LABEL: combine_undef_input_test7:
2177 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2180 ; SSSE3-LABEL: combine_undef_input_test7:
\r
2182 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
\r
2183 ; SSSE3-NEXT: retq
\r
2185 ; SSE41-LABEL: combine_undef_input_test7:
\r
2187 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
\r
2188 ; SSE41-NEXT: retq
\r
2190 ; AVX-LABEL: combine_undef_input_test7:
\r
2192 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
\r
2194 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
\r
2195 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
\r
2199 define <4 x float> @combine_undef_input_test8(<4 x float> %a) {
2200 ; SSE2-LABEL: combine_undef_input_test8:
2202 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2205 ; SSSE3-LABEL: combine_undef_input_test8:
\r
2207 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
\r
2208 ; SSSE3-NEXT: retq
\r
2210 ; SSE41-LABEL: combine_undef_input_test8:
\r
2212 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
\r
2213 ; SSE41-NEXT: retq
\r
2215 ; AVX-LABEL: combine_undef_input_test8:
\r
2217 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
\r
2219 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
\r
2220 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
\r
2224 define <4 x float> @combine_undef_input_test9(<4 x float> %a) {
2225 ; SSE-LABEL: combine_undef_input_test9:
2227 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2230 ; AVX-LABEL: combine_undef_input_test9:
2232 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2234 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2235 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2239 define <4 x float> @combine_undef_input_test10(<4 x float> %a) {
2240 ; ALL-LABEL: combine_undef_input_test10:
2243 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2244 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2248 define <4 x float> @combine_undef_input_test11(<4 x float> %a, <4 x float> %b) {
2249 ; SSE2-LABEL: combine_undef_input_test11:
2251 ; SSE2-NEXT: movsd %xmm1, %xmm0
2254 ; SSSE3-LABEL: combine_undef_input_test11:
2256 ; SSSE3-NEXT: movsd %xmm1, %xmm0
2259 ; SSE41-LABEL: combine_undef_input_test11:
2261 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2264 ; AVX-LABEL: combine_undef_input_test11:
2266 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2268 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2269 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 6>
2273 define <4 x float> @combine_undef_input_test12(<4 x float> %a, <4 x float> %b) {
2274 ; SSE-LABEL: combine_undef_input_test12:
2276 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2279 ; AVX-LABEL: combine_undef_input_test12:
2281 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2283 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2284 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2288 define <4 x float> @combine_undef_input_test13(<4 x float> %a, <4 x float> %b) {
2289 ; SSE-LABEL: combine_undef_input_test13:
2291 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2294 ; AVX-LABEL: combine_undef_input_test13:
2296 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2298 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2299 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 5, i32 0, i32 5>
2303 define <4 x float> @combine_undef_input_test14(<4 x float> %a, <4 x float> %b) {
2304 ; SSE-LABEL: combine_undef_input_test14:
2306 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2307 ; SSE-NEXT: movapd %xmm1, %xmm0
2310 ; AVX-LABEL: combine_undef_input_test14:
2312 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2314 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2315 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2319 define <4 x float> @combine_undef_input_test15(<4 x float> %a, <4 x float> %b) {
2320 ; SSE2-LABEL: combine_undef_input_test15:
2322 ; SSE2-NEXT: movsd %xmm0, %xmm1
2323 ; SSE2-NEXT: movaps %xmm1, %xmm0
2326 ; SSSE3-LABEL: combine_undef_input_test15:
2328 ; SSSE3-NEXT: movsd %xmm0, %xmm1
2329 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2332 ; SSE41-LABEL: combine_undef_input_test15:
2334 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2337 ; AVX-LABEL: combine_undef_input_test15:
2339 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2341 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2342 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2347 ; Verify that shuffles are canonicalized according to rules:
2348 ; shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
2350 ; This allows to trigger the following combine rule:
2351 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2353 ; As a result, all the shuffle pairs in each function below should be
2354 ; combined into a single legal shuffle operation.
2356 define <4 x float> @combine_undef_input_test16(<4 x float> %a) {
2357 ; ALL-LABEL: combine_undef_input_test16:
2360 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2361 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
2365 define <4 x float> @combine_undef_input_test17(<4 x float> %a) {
2366 ; SSE2-LABEL: combine_undef_input_test17:
2368 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2371 ; SSSE3-LABEL: combine_undef_input_test17:
\r
2373 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
\r
2374 ; SSSE3-NEXT: retq
\r
2376 ; SSE41-LABEL: combine_undef_input_test17:
\r
2378 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
\r
2379 ; SSE41-NEXT: retq
\r
2381 ; AVX-LABEL: combine_undef_input_test17:
\r
2383 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
\r
2385 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
\r
2386 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
\r
2390 define <4 x float> @combine_undef_input_test18(<4 x float> %a) {
2391 ; SSE2-LABEL: combine_undef_input_test18:
2393 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2396 ; SSSE3-LABEL: combine_undef_input_test18:
\r
2398 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
\r
2399 ; SSSE3-NEXT: retq
\r
2401 ; SSE41-LABEL: combine_undef_input_test18:
\r
2403 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
\r
2404 ; SSE41-NEXT: retq
\r
2406 ; AVX-LABEL: combine_undef_input_test18:
\r
2408 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
\r
2410 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
\r
2411 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 0, i32 5>
\r
2415 define <4 x float> @combine_undef_input_test19(<4 x float> %a) {
2416 ; SSE-LABEL: combine_undef_input_test19:
2418 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2421 ; AVX-LABEL: combine_undef_input_test19:
2423 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2425 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2426 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2430 define <4 x float> @combine_undef_input_test20(<4 x float> %a) {
2431 ; ALL-LABEL: combine_undef_input_test20:
2434 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2435 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2439 ; These tests are designed to test the ability to combine away unnecessary
2440 ; operations feeding into a shuffle. The AVX cases are the important ones as
2441 ; they leverage operations which cannot be done naturally on the entire vector
2442 ; and thus are decomposed into multiple smaller operations.
2444 define <8 x i32> @combine_unneeded_subvector1(<8 x i32> %a) {
2445 ; SSE-LABEL: combine_unneeded_subvector1:
2447 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2448 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,2,1,0]
2449 ; SSE-NEXT: movdqa %xmm0, %xmm1
2452 ; AVX1-LABEL: combine_unneeded_subvector1:
2454 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2455 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2456 ; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
2457 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2460 ; AVX2-LABEL: combine_unneeded_subvector1:
2462 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2463 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [7,6,5,4,7,6,5,4]
2464 ; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
2466 %b = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2467 %c = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 7, i32 6, i32 5, i32 4>
2471 define <8 x i32> @combine_unneeded_subvector2(<8 x i32> %a, <8 x i32> %b) {
2472 ; SSE-LABEL: combine_unneeded_subvector2:
2474 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2475 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[3,2,1,0]
2476 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
2479 ; AVX1-LABEL: combine_unneeded_subvector2:
2481 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2482 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2483 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2484 ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
2485 ; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2488 ; AVX2-LABEL: combine_unneeded_subvector2:
2490 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2491 ; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
2492 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2494 %c = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2495 %d = shufflevector <8 x i32> %b, <8 x i32> %c, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 15, i32 14, i32 13, i32 12>
2499 define <4 x float> @combine_insertps1(<4 x float> %a, <4 x float> %b) {
2500 ; SSE41-LABEL: combine_insertps1:
2502 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
2505 ; AVX-LABEL: combine_insertps1:
2507 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
2510 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 6, i32 2, i32 4>
2511 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32> <i32 5, i32 1, i32 6, i32 3>
2515 define <4 x float> @combine_insertps2(<4 x float> %a, <4 x float> %b) {
2516 ; SSE41-LABEL: combine_insertps2:
2518 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
2521 ; AVX-LABEL: combine_insertps2:
2523 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
2526 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 1, i32 6, i32 7>
2527 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2531 define <4 x float> @combine_insertps3(<4 x float> %a, <4 x float> %b) {
2532 ; SSE41-LABEL: combine_insertps3:
2534 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
2537 ; AVX-LABEL: combine_insertps3:
2539 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
2542 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
2543 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 5, i32 3>
2547 define <4 x float> @combine_insertps4(<4 x float> %a, <4 x float> %b) {
2548 ; SSE41-LABEL: combine_insertps4:
2550 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
2553 ; AVX-LABEL: combine_insertps4:
2555 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
2558 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
2559 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 6, i32 5>