1 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse2 -x86-experimental-vector-shuffle-legality | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
2 ; RUN: llc < %s -mcpu=x86-64 -mattr=+ssse3 -x86-experimental-vector-shuffle-legality | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
3 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse4.1 -x86-experimental-vector-shuffle-legality | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx -x86-experimental-vector-shuffle-legality | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
5 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 -x86-experimental-vector-shuffle-legality | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
7 ; Verify that the DAG combiner correctly folds bitwise operations across
8 ; shuffles, nested shuffles with undef, pairs of nested shuffles, and other
9 ; basic and always-safe patterns. Also test that the DAG combiner will combine
10 ; target-specific shuffle instructions where reasonable.
12 target triple = "x86_64-unknown-unknown"
14 declare <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32>, i8)
15 declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8)
16 declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8)
18 define <4 x i32> @combine_pshufd1(<4 x i32> %a) {
19 ; ALL-LABEL: combine_pshufd1:
20 ; ALL: # BB#0: # %entry
23 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
24 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 27)
28 define <4 x i32> @combine_pshufd2(<4 x i32> %a) {
29 ; ALL-LABEL: combine_pshufd2:
30 ; ALL: # BB#0: # %entry
33 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
34 %b.cast = bitcast <4 x i32> %b to <8 x i16>
35 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 -28)
36 %c.cast = bitcast <8 x i16> %c to <4 x i32>
37 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
41 define <4 x i32> @combine_pshufd3(<4 x i32> %a) {
42 ; ALL-LABEL: combine_pshufd3:
43 ; ALL: # BB#0: # %entry
46 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
47 %b.cast = bitcast <4 x i32> %b to <8 x i16>
48 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 -28)
49 %c.cast = bitcast <8 x i16> %c to <4 x i32>
50 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
54 define <4 x i32> @combine_pshufd4(<4 x i32> %a) {
55 ; SSE-LABEL: combine_pshufd4:
56 ; SSE: # BB#0: # %entry
57 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
60 ; AVX-LABEL: combine_pshufd4:
61 ; AVX: # BB#0: # %entry
62 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
65 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -31)
66 %b.cast = bitcast <4 x i32> %b to <8 x i16>
67 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 27)
68 %c.cast = bitcast <8 x i16> %c to <4 x i32>
69 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -31)
73 define <4 x i32> @combine_pshufd5(<4 x i32> %a) {
74 ; SSE-LABEL: combine_pshufd5:
75 ; SSE: # BB#0: # %entry
76 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
79 ; AVX-LABEL: combine_pshufd5:
80 ; AVX: # BB#0: # %entry
81 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
84 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -76)
85 %b.cast = bitcast <4 x i32> %b to <8 x i16>
86 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 27)
87 %c.cast = bitcast <8 x i16> %c to <4 x i32>
88 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -76)
92 define <4 x i32> @combine_pshufd6(<4 x i32> %a) {
93 ; SSE-LABEL: combine_pshufd6:
94 ; SSE: # BB#0: # %entry
95 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
98 ; AVX-LABEL: combine_pshufd6:
99 ; AVX: # BB#0: # %entry
100 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
103 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 0)
104 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 8)
108 define <8 x i16> @combine_pshuflw1(<8 x i16> %a) {
109 ; ALL-LABEL: combine_pshuflw1:
110 ; ALL: # BB#0: # %entry
113 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
114 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
118 define <8 x i16> @combine_pshuflw2(<8 x i16> %a) {
119 ; ALL-LABEL: combine_pshuflw2:
120 ; ALL: # BB#0: # %entry
123 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
124 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 -28)
125 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
129 define <8 x i16> @combine_pshuflw3(<8 x i16> %a) {
130 ; SSE-LABEL: combine_pshuflw3:
131 ; SSE: # BB#0: # %entry
132 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
135 ; AVX-LABEL: combine_pshuflw3:
136 ; AVX: # BB#0: # %entry
137 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
140 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
141 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 27)
142 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
146 define <8 x i16> @combine_pshufhw1(<8 x i16> %a) {
147 ; SSE-LABEL: combine_pshufhw1:
148 ; SSE: # BB#0: # %entry
149 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
152 ; AVX-LABEL: combine_pshufhw1:
153 ; AVX: # BB#0: # %entry
154 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
157 %b = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27)
158 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
159 %d = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %c, i8 27)
163 define <4 x i32> @combine_bitwise_ops_test1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
164 ; SSE-LABEL: combine_bitwise_ops_test1:
166 ; SSE-NEXT: pand %xmm1, %xmm0
167 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
170 ; AVX-LABEL: combine_bitwise_ops_test1:
172 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
173 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
175 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
176 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
177 %and = and <4 x i32> %shuf1, %shuf2
181 define <4 x i32> @combine_bitwise_ops_test2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
182 ; SSE-LABEL: combine_bitwise_ops_test2:
184 ; SSE-NEXT: por %xmm1, %xmm0
185 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
188 ; AVX-LABEL: combine_bitwise_ops_test2:
190 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
191 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
193 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
194 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
195 %or = or <4 x i32> %shuf1, %shuf2
199 define <4 x i32> @combine_bitwise_ops_test3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
200 ; SSE-LABEL: combine_bitwise_ops_test3:
202 ; SSE-NEXT: pxor %xmm1, %xmm0
203 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
206 ; AVX-LABEL: combine_bitwise_ops_test3:
208 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
209 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
211 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
212 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
213 %xor = xor <4 x i32> %shuf1, %shuf2
217 define <4 x i32> @combine_bitwise_ops_test4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
218 ; SSE-LABEL: combine_bitwise_ops_test4:
220 ; SSE-NEXT: pand %xmm1, %xmm0
221 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
224 ; AVX-LABEL: combine_bitwise_ops_test4:
226 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
227 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
229 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
230 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
231 %and = and <4 x i32> %shuf1, %shuf2
235 define <4 x i32> @combine_bitwise_ops_test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
236 ; SSE-LABEL: combine_bitwise_ops_test5:
238 ; SSE-NEXT: por %xmm1, %xmm0
239 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
242 ; AVX-LABEL: combine_bitwise_ops_test5:
244 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
245 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
247 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
248 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
249 %or = or <4 x i32> %shuf1, %shuf2
253 define <4 x i32> @combine_bitwise_ops_test6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
254 ; SSE-LABEL: combine_bitwise_ops_test6:
256 ; SSE-NEXT: pxor %xmm1, %xmm0
257 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
260 ; AVX-LABEL: combine_bitwise_ops_test6:
262 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
263 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
265 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
266 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
267 %xor = xor <4 x i32> %shuf1, %shuf2
272 ; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles
273 ; are not performing a swizzle operations.
275 define <4 x i32> @combine_bitwise_ops_test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
276 ; SSE2-LABEL: combine_bitwise_ops_test1b:
278 ; SSE2-NEXT: andps %xmm1, %xmm0
279 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
280 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
283 ; SSSE3-LABEL: combine_bitwise_ops_test1b:
285 ; SSSE3-NEXT: andps %xmm1, %xmm0
286 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
287 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
290 ; SSE41-LABEL: combine_bitwise_ops_test1b:
292 ; SSE41-NEXT: pand %xmm1, %xmm0
293 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
296 ; AVX1-LABEL: combine_bitwise_ops_test1b:
298 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
299 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
302 ; AVX2-LABEL: combine_bitwise_ops_test1b:
304 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
305 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
307 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
308 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
309 %and = and <4 x i32> %shuf1, %shuf2
313 define <4 x i32> @combine_bitwise_ops_test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
314 ; SSE2-LABEL: combine_bitwise_ops_test2b:
316 ; SSE2-NEXT: orps %xmm1, %xmm0
317 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
318 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
321 ; SSSE3-LABEL: combine_bitwise_ops_test2b:
323 ; SSSE3-NEXT: orps %xmm1, %xmm0
324 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
325 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
328 ; SSE41-LABEL: combine_bitwise_ops_test2b:
330 ; SSE41-NEXT: por %xmm1, %xmm0
331 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
334 ; AVX1-LABEL: combine_bitwise_ops_test2b:
336 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
337 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
340 ; AVX2-LABEL: combine_bitwise_ops_test2b:
342 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
343 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
345 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
346 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
347 %or = or <4 x i32> %shuf1, %shuf2
351 define <4 x i32> @combine_bitwise_ops_test3b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
352 ; SSE2-LABEL: combine_bitwise_ops_test3b:
354 ; SSE2-NEXT: xorps %xmm1, %xmm0
355 ; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
358 ; SSSE3-LABEL: combine_bitwise_ops_test3b:
360 ; SSSE3-NEXT: xorps %xmm1, %xmm0
361 ; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
364 ; SSE41-LABEL: combine_bitwise_ops_test3b:
366 ; SSE41-NEXT: pxor %xmm1, %xmm0
367 ; SSE41-NEXT: pxor %xmm1, %xmm1
368 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
371 ; AVX1-LABEL: combine_bitwise_ops_test3b:
373 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
374 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
375 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
378 ; AVX2-LABEL: combine_bitwise_ops_test3b:
380 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
381 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
382 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
384 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
385 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
386 %xor = xor <4 x i32> %shuf1, %shuf2
390 define <4 x i32> @combine_bitwise_ops_test4b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
391 ; SSE2-LABEL: combine_bitwise_ops_test4b:
393 ; SSE2-NEXT: andps %xmm1, %xmm0
394 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
395 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
396 ; SSE2-NEXT: movaps %xmm2, %xmm0
399 ; SSSE3-LABEL: combine_bitwise_ops_test4b:
401 ; SSSE3-NEXT: andps %xmm1, %xmm0
402 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
403 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
404 ; SSSE3-NEXT: movaps %xmm2, %xmm0
407 ; SSE41-LABEL: combine_bitwise_ops_test4b:
409 ; SSE41-NEXT: pand %xmm1, %xmm0
410 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
413 ; AVX1-LABEL: combine_bitwise_ops_test4b:
415 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
416 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
419 ; AVX2-LABEL: combine_bitwise_ops_test4b:
421 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
422 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
424 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
425 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
426 %and = and <4 x i32> %shuf1, %shuf2
430 define <4 x i32> @combine_bitwise_ops_test5b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
431 ; SSE2-LABEL: combine_bitwise_ops_test5b:
433 ; SSE2-NEXT: orps %xmm1, %xmm0
434 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
435 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
436 ; SSE2-NEXT: movaps %xmm2, %xmm0
439 ; SSSE3-LABEL: combine_bitwise_ops_test5b:
441 ; SSSE3-NEXT: orps %xmm1, %xmm0
442 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
443 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
444 ; SSSE3-NEXT: movaps %xmm2, %xmm0
447 ; SSE41-LABEL: combine_bitwise_ops_test5b:
449 ; SSE41-NEXT: por %xmm1, %xmm0
450 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
453 ; AVX1-LABEL: combine_bitwise_ops_test5b:
455 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
456 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
459 ; AVX2-LABEL: combine_bitwise_ops_test5b:
461 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
462 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
464 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
465 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
466 %or = or <4 x i32> %shuf1, %shuf2
470 define <4 x i32> @combine_bitwise_ops_test6b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
471 ; SSE2-LABEL: combine_bitwise_ops_test6b:
473 ; SSE2-NEXT: xorps %xmm1, %xmm0
474 ; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
477 ; SSSE3-LABEL: combine_bitwise_ops_test6b:
479 ; SSSE3-NEXT: xorps %xmm1, %xmm0
480 ; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
483 ; SSE41-LABEL: combine_bitwise_ops_test6b:
485 ; SSE41-NEXT: pxor %xmm1, %xmm0
486 ; SSE41-NEXT: pxor %xmm1, %xmm1
487 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
490 ; AVX1-LABEL: combine_bitwise_ops_test6b:
492 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
493 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
494 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
497 ; AVX2-LABEL: combine_bitwise_ops_test6b:
499 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
500 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
501 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
503 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
504 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
505 %xor = xor <4 x i32> %shuf1, %shuf2
509 define <4 x i32> @combine_bitwise_ops_test1c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
510 ; SSE-LABEL: combine_bitwise_ops_test1c:
512 ; SSE-NEXT: andps %xmm1, %xmm0
513 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
516 ; AVX-LABEL: combine_bitwise_ops_test1c:
518 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
519 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
521 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
522 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
523 %and = and <4 x i32> %shuf1, %shuf2
527 define <4 x i32> @combine_bitwise_ops_test2c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
528 ; SSE-LABEL: combine_bitwise_ops_test2c:
530 ; SSE-NEXT: orps %xmm1, %xmm0
531 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
534 ; AVX-LABEL: combine_bitwise_ops_test2c:
536 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
537 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
539 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
540 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
541 %or = or <4 x i32> %shuf1, %shuf2
545 define <4 x i32> @combine_bitwise_ops_test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
546 ; SSE2-LABEL: combine_bitwise_ops_test3c:
548 ; SSE2-NEXT: xorps %xmm1, %xmm0
549 ; SSE2-NEXT: xorps %xmm1, %xmm1
550 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
553 ; SSSE3-LABEL: combine_bitwise_ops_test3c:
555 ; SSSE3-NEXT: xorps %xmm1, %xmm0
556 ; SSSE3-NEXT: xorps %xmm1, %xmm1
557 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
560 ; SSE41-LABEL: combine_bitwise_ops_test3c:
562 ; SSE41-NEXT: xorps %xmm1, %xmm0
563 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero
566 ; AVX-LABEL: combine_bitwise_ops_test3c:
568 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
569 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero
571 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
572 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
573 %xor = xor <4 x i32> %shuf1, %shuf2
577 define <4 x i32> @combine_bitwise_ops_test4c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
578 ; SSE-LABEL: combine_bitwise_ops_test4c:
580 ; SSE-NEXT: andps %xmm1, %xmm0
581 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
582 ; SSE-NEXT: movaps %xmm2, %xmm0
585 ; AVX-LABEL: combine_bitwise_ops_test4c:
587 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
588 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
590 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
591 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
592 %and = and <4 x i32> %shuf1, %shuf2
596 define <4 x i32> @combine_bitwise_ops_test5c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
597 ; SSE-LABEL: combine_bitwise_ops_test5c:
599 ; SSE-NEXT: orps %xmm1, %xmm0
600 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
601 ; SSE-NEXT: movaps %xmm2, %xmm0
604 ; AVX-LABEL: combine_bitwise_ops_test5c:
606 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
607 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
609 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
610 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
611 %or = or <4 x i32> %shuf1, %shuf2
615 define <4 x i32> @combine_bitwise_ops_test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
616 ; SSE-LABEL: combine_bitwise_ops_test6c:
618 ; SSE-NEXT: xorps %xmm1, %xmm0
619 ; SSE-NEXT: xorps %xmm1, %xmm1
620 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,3]
621 ; SSE-NEXT: movaps %xmm1, %xmm0
624 ; AVX-LABEL: combine_bitwise_ops_test6c:
626 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
627 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
628 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,1],xmm0[1,3]
630 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
631 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
632 %xor = xor <4 x i32> %shuf1, %shuf2
636 define <4 x i32> @combine_nested_undef_test1(<4 x i32> %A, <4 x i32> %B) {
637 ; SSE-LABEL: combine_nested_undef_test1:
639 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
642 ; AVX-LABEL: combine_nested_undef_test1:
644 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
646 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
647 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
651 define <4 x i32> @combine_nested_undef_test2(<4 x i32> %A, <4 x i32> %B) {
652 ; SSE-LABEL: combine_nested_undef_test2:
654 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
657 ; AVX-LABEL: combine_nested_undef_test2:
659 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
661 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
662 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
666 define <4 x i32> @combine_nested_undef_test3(<4 x i32> %A, <4 x i32> %B) {
667 ; SSE-LABEL: combine_nested_undef_test3:
669 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
672 ; AVX-LABEL: combine_nested_undef_test3:
674 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
676 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
677 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
681 define <4 x i32> @combine_nested_undef_test4(<4 x i32> %A, <4 x i32> %B) {
682 ; SSE-LABEL: combine_nested_undef_test4:
684 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
687 ; AVX1-LABEL: combine_nested_undef_test4:
689 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
692 ; AVX2-LABEL: combine_nested_undef_test4:
694 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
696 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 7, i32 1>
697 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 3>
701 define <4 x i32> @combine_nested_undef_test5(<4 x i32> %A, <4 x i32> %B) {
702 ; SSE-LABEL: combine_nested_undef_test5:
704 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
707 ; AVX-LABEL: combine_nested_undef_test5:
709 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
711 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 5, i32 5, i32 2, i32 3>
712 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 4, i32 3>
716 define <4 x i32> @combine_nested_undef_test6(<4 x i32> %A, <4 x i32> %B) {
717 ; SSE-LABEL: combine_nested_undef_test6:
719 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
722 ; AVX-LABEL: combine_nested_undef_test6:
724 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
726 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
727 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 4>
731 define <4 x i32> @combine_nested_undef_test7(<4 x i32> %A, <4 x i32> %B) {
732 ; SSE-LABEL: combine_nested_undef_test7:
734 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
737 ; AVX-LABEL: combine_nested_undef_test7:
739 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
741 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
742 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
746 define <4 x i32> @combine_nested_undef_test8(<4 x i32> %A, <4 x i32> %B) {
747 ; SSE-LABEL: combine_nested_undef_test8:
749 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
752 ; AVX-LABEL: combine_nested_undef_test8:
754 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
756 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
757 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
761 define <4 x i32> @combine_nested_undef_test9(<4 x i32> %A, <4 x i32> %B) {
762 ; SSE-LABEL: combine_nested_undef_test9:
764 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
767 ; AVX-LABEL: combine_nested_undef_test9:
769 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
771 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 2, i32 5>
772 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
776 define <4 x i32> @combine_nested_undef_test10(<4 x i32> %A, <4 x i32> %B) {
777 ; SSE-LABEL: combine_nested_undef_test10:
779 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
782 ; AVX-LABEL: combine_nested_undef_test10:
784 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
786 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 5>
787 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 4>
791 define <4 x i32> @combine_nested_undef_test11(<4 x i32> %A, <4 x i32> %B) {
792 ; SSE-LABEL: combine_nested_undef_test11:
794 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
797 ; AVX-LABEL: combine_nested_undef_test11:
799 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
801 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 2, i32 5, i32 4>
802 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 0>
806 define <4 x i32> @combine_nested_undef_test12(<4 x i32> %A, <4 x i32> %B) {
807 ; SSE-LABEL: combine_nested_undef_test12:
809 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
812 ; AVX1-LABEL: combine_nested_undef_test12:
814 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
817 ; AVX2-LABEL: combine_nested_undef_test12:
819 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
821 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 0, i32 2, i32 4>
822 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 0, i32 4>
826 ; The following pair of shuffles is folded into vector %A.
827 define <4 x i32> @combine_nested_undef_test13(<4 x i32> %A, <4 x i32> %B) {
828 ; ALL-LABEL: combine_nested_undef_test13:
831 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 4, i32 2, i32 6>
832 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 0, i32 2, i32 4>
836 ; The following pair of shuffles is folded into vector %B.
837 define <4 x i32> @combine_nested_undef_test14(<4 x i32> %A, <4 x i32> %B) {
838 ; SSE-LABEL: combine_nested_undef_test14:
840 ; SSE-NEXT: movaps %xmm1, %xmm0
843 ; AVX-LABEL: combine_nested_undef_test14:
845 ; AVX-NEXT: vmovaps %xmm1, %xmm0
847 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
848 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 4, i32 1, i32 4>
853 ; Verify that we don't optimize the following cases. We expect more than one shuffle.
855 ; FIXME: Many of these already don't make sense, and the rest should stop
856 ; making sense with th enew vector shuffle lowering. Revisit at least testing for
859 define <4 x i32> @combine_nested_undef_test15(<4 x i32> %A, <4 x i32> %B) {
860 ; SSE-LABEL: combine_nested_undef_test15:
862 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
863 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,1]
864 ; SSE-NEXT: movaps %xmm1, %xmm0
867 ; AVX-LABEL: combine_nested_undef_test15:
869 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
870 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[0,1]
872 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
873 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
877 define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
878 ; SSE2-LABEL: combine_nested_undef_test16:
880 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[1,3]
881 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
884 ; SSSE3-LABEL: combine_nested_undef_test16:
886 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[1,3]
887 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
890 ; SSE41-LABEL: combine_nested_undef_test16:
892 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
893 ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,1,0,3]
896 ; AVX-LABEL: combine_nested_undef_test16:
898 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
899 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,1,0,3]
901 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
902 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
906 define <4 x i32> @combine_nested_undef_test17(<4 x i32> %A, <4 x i32> %B) {
907 ; SSE2-LABEL: combine_nested_undef_test17:
909 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
910 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1],xmm1[0,2]
913 ; SSSE3-LABEL: combine_nested_undef_test17:
915 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
916 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1],xmm1[0,2]
919 ; SSE41-LABEL: combine_nested_undef_test17:
921 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
922 ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,0,1]
925 ; AVX-LABEL: combine_nested_undef_test17:
927 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
928 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,0,1]
930 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
931 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
935 define <4 x i32> @combine_nested_undef_test18(<4 x i32> %A, <4 x i32> %B) {
936 ; SSE-LABEL: combine_nested_undef_test18:
938 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
941 ; AVX-LABEL: combine_nested_undef_test18:
943 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
945 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
946 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 3>
950 define <4 x i32> @combine_nested_undef_test19(<4 x i32> %A, <4 x i32> %B) {
951 ; SSE2-LABEL: combine_nested_undef_test19:
953 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
954 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[0,0]
955 ; SSE2-NEXT: movaps %xmm1, %xmm0
958 ; SSSE3-LABEL: combine_nested_undef_test19:
960 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
961 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[0,0]
962 ; SSSE3-NEXT: movaps %xmm1, %xmm0
965 ; SSE41-LABEL: combine_nested_undef_test19:
967 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
968 ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0,0,0]
971 ; AVX-LABEL: combine_nested_undef_test19:
973 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
974 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,0,0,0]
976 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
977 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
981 define <4 x i32> @combine_nested_undef_test20(<4 x i32> %A, <4 x i32> %B) {
982 ; SSE2-LABEL: combine_nested_undef_test20:
984 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,3]
985 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
986 ; SSE2-NEXT: movaps %xmm1, %xmm0
989 ; SSSE3-LABEL: combine_nested_undef_test20:
991 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,3]
992 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
993 ; SSSE3-NEXT: movaps %xmm1, %xmm0
996 ; SSE41-LABEL: combine_nested_undef_test20:
998 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
999 ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,0]
1002 ; AVX-LABEL: combine_nested_undef_test20:
1004 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1005 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,3,0]
1007 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
1008 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
1012 define <4 x i32> @combine_nested_undef_test21(<4 x i32> %A, <4 x i32> %B) {
1013 ; SSE2-LABEL: combine_nested_undef_test21:
1015 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,1]
1016 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
1017 ; SSE2-NEXT: movaps %xmm1, %xmm0
1020 ; SSSE3-LABEL: combine_nested_undef_test21:
1022 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,1]
1023 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
1024 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1027 ; SSE41-LABEL: combine_nested_undef_test21:
1029 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1030 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
1033 ; AVX-LABEL: combine_nested_undef_test21:
1035 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1036 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
1038 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
1039 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1044 ; Test that we correctly combine shuffles according to rule
1045 ; shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
1047 define <4 x i32> @combine_nested_undef_test22(<4 x i32> %A, <4 x i32> %B) {
1048 ; SSE-LABEL: combine_nested_undef_test22:
1050 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1053 ; AVX-LABEL: combine_nested_undef_test22:
1055 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1057 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1058 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 3>
1062 define <4 x i32> @combine_nested_undef_test23(<4 x i32> %A, <4 x i32> %B) {
1063 ; SSE-LABEL: combine_nested_undef_test23:
1065 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1068 ; AVX-LABEL: combine_nested_undef_test23:
1070 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1072 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1073 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1077 define <4 x i32> @combine_nested_undef_test24(<4 x i32> %A, <4 x i32> %B) {
1078 ; SSE-LABEL: combine_nested_undef_test24:
1080 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1083 ; AVX-LABEL: combine_nested_undef_test24:
1085 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1087 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1088 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 4>
1092 define <4 x i32> @combine_nested_undef_test25(<4 x i32> %A, <4 x i32> %B) {
1093 ; SSE-LABEL: combine_nested_undef_test25:
1095 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1098 ; AVX1-LABEL: combine_nested_undef_test25:
1100 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1103 ; AVX2-LABEL: combine_nested_undef_test25:
1105 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1107 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 5, i32 2, i32 4>
1108 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 3, i32 1>
1112 define <4 x i32> @combine_nested_undef_test26(<4 x i32> %A, <4 x i32> %B) {
1113 ; SSE-LABEL: combine_nested_undef_test26:
1115 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1118 ; AVX-LABEL: combine_nested_undef_test26:
1120 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1122 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 6, i32 7>
1123 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
1127 define <4 x i32> @combine_nested_undef_test27(<4 x i32> %A, <4 x i32> %B) {
1128 ; SSE-LABEL: combine_nested_undef_test27:
1130 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1133 ; AVX1-LABEL: combine_nested_undef_test27:
1135 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1138 ; AVX2-LABEL: combine_nested_undef_test27:
1140 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1142 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 2, i32 1, i32 5, i32 4>
1143 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
1147 define <4 x i32> @combine_nested_undef_test28(<4 x i32> %A, <4 x i32> %B) {
1148 ; SSE-LABEL: combine_nested_undef_test28:
1150 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1153 ; AVX-LABEL: combine_nested_undef_test28:
1155 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1157 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
1158 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 3, i32 2>
1162 define <4 x float> @combine_test1(<4 x float> %a, <4 x float> %b) {
1163 ; SSE-LABEL: combine_test1:
1165 ; SSE-NEXT: movaps %xmm1, %xmm0
1168 ; AVX-LABEL: combine_test1:
1170 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1172 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1173 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1177 define <4 x float> @combine_test2(<4 x float> %a, <4 x float> %b) {
1178 ; SSE2-LABEL: combine_test2:
1180 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1181 ; SSE2-NEXT: movaps %xmm1, %xmm0
1184 ; SSSE3-LABEL: combine_test2:
1186 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1187 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1190 ; SSE41-LABEL: combine_test2:
1192 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1195 ; AVX-LABEL: combine_test2:
1197 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1199 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1200 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1204 define <4 x float> @combine_test3(<4 x float> %a, <4 x float> %b) {
1205 ; SSE-LABEL: combine_test3:
1207 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1210 ; AVX-LABEL: combine_test3:
1212 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1214 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1215 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1219 define <4 x float> @combine_test4(<4 x float> %a, <4 x float> %b) {
1220 ; SSE-LABEL: combine_test4:
1222 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1223 ; SSE-NEXT: movapd %xmm1, %xmm0
1226 ; AVX-LABEL: combine_test4:
1228 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1230 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1231 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1235 define <4 x float> @combine_test5(<4 x float> %a, <4 x float> %b) {
1236 ; SSE2-LABEL: combine_test5:
1238 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1239 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1242 ; SSSE3-LABEL: combine_test5:
1244 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1245 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1248 ; SSE41-LABEL: combine_test5:
1250 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1253 ; AVX-LABEL: combine_test5:
1255 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1257 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1258 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1262 define <4 x i32> @combine_test6(<4 x i32> %a, <4 x i32> %b) {
1263 ; SSE-LABEL: combine_test6:
1265 ; SSE-NEXT: movaps %xmm1, %xmm0
1268 ; AVX-LABEL: combine_test6:
1270 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1272 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1273 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1277 define <4 x i32> @combine_test7(<4 x i32> %a, <4 x i32> %b) {
1278 ; SSE2-LABEL: combine_test7:
1280 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1281 ; SSE2-NEXT: movaps %xmm1, %xmm0
1284 ; SSSE3-LABEL: combine_test7:
1286 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1287 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1290 ; SSE41-LABEL: combine_test7:
1292 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1295 ; AVX1-LABEL: combine_test7:
1297 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1300 ; AVX2-LABEL: combine_test7:
1302 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1304 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1305 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1309 define <4 x i32> @combine_test8(<4 x i32> %a, <4 x i32> %b) {
1310 ; SSE-LABEL: combine_test8:
1312 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1315 ; AVX-LABEL: combine_test8:
1317 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1319 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1320 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1324 define <4 x i32> @combine_test9(<4 x i32> %a, <4 x i32> %b) {
1325 ; SSE-LABEL: combine_test9:
1327 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1328 ; SSE-NEXT: movdqa %xmm1, %xmm0
1331 ; AVX-LABEL: combine_test9:
1333 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1335 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1336 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1340 define <4 x i32> @combine_test10(<4 x i32> %a, <4 x i32> %b) {
1341 ; SSE2-LABEL: combine_test10:
1343 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1344 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1347 ; SSSE3-LABEL: combine_test10:
1349 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1350 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1353 ; SSE41-LABEL: combine_test10:
1355 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1358 ; AVX1-LABEL: combine_test10:
1360 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1363 ; AVX2-LABEL: combine_test10:
1365 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1367 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1368 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1372 define <4 x float> @combine_test11(<4 x float> %a, <4 x float> %b) {
1373 ; ALL-LABEL: combine_test11:
1376 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1377 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1381 define <4 x float> @combine_test12(<4 x float> %a, <4 x float> %b) {
1382 ; SSE2-LABEL: combine_test12:
1384 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1385 ; SSE2-NEXT: movaps %xmm1, %xmm0
1388 ; SSSE3-LABEL: combine_test12:
1390 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1391 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1394 ; SSE41-LABEL: combine_test12:
1396 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1399 ; AVX-LABEL: combine_test12:
1401 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1403 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1404 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1408 define <4 x float> @combine_test13(<4 x float> %a, <4 x float> %b) {
1409 ; SSE-LABEL: combine_test13:
1411 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1414 ; AVX-LABEL: combine_test13:
1416 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1418 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1419 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1423 define <4 x float> @combine_test14(<4 x float> %a, <4 x float> %b) {
1424 ; SSE-LABEL: combine_test14:
1426 ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1429 ; AVX-LABEL: combine_test14:
1431 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1433 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1434 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1438 define <4 x float> @combine_test15(<4 x float> %a, <4 x float> %b) {
1439 ; SSE2-LABEL: combine_test15:
1441 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1442 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1445 ; SSSE3-LABEL: combine_test15:
1447 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1448 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1451 ; SSE41-LABEL: combine_test15:
1453 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1456 ; AVX-LABEL: combine_test15:
1458 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1460 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1461 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1465 define <4 x i32> @combine_test16(<4 x i32> %a, <4 x i32> %b) {
1466 ; ALL-LABEL: combine_test16:
1469 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1470 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1474 define <4 x i32> @combine_test17(<4 x i32> %a, <4 x i32> %b) {
1475 ; SSE2-LABEL: combine_test17:
1477 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1478 ; SSE2-NEXT: movaps %xmm1, %xmm0
1481 ; SSSE3-LABEL: combine_test17:
1483 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1484 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1487 ; SSE41-LABEL: combine_test17:
1489 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1492 ; AVX1-LABEL: combine_test17:
1494 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1497 ; AVX2-LABEL: combine_test17:
1499 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1501 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1502 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1506 define <4 x i32> @combine_test18(<4 x i32> %a, <4 x i32> %b) {
1507 ; SSE-LABEL: combine_test18:
1509 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1512 ; AVX-LABEL: combine_test18:
1514 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1516 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1517 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1521 define <4 x i32> @combine_test19(<4 x i32> %a, <4 x i32> %b) {
1522 ; SSE-LABEL: combine_test19:
1524 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1527 ; AVX-LABEL: combine_test19:
1529 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1531 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1532 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1536 define <4 x i32> @combine_test20(<4 x i32> %a, <4 x i32> %b) {
1537 ; SSE2-LABEL: combine_test20:
1539 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1540 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1543 ; SSSE3-LABEL: combine_test20:
1545 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1546 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1549 ; SSE41-LABEL: combine_test20:
1551 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1554 ; AVX1-LABEL: combine_test20:
1556 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1559 ; AVX2-LABEL: combine_test20:
1561 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1563 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1564 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1568 define <4 x i32> @combine_test21(<8 x i32> %a, <4 x i32>* %ptr) {
1569 ; SSE-LABEL: combine_test21:
1571 ; SSE-NEXT: movdqa %xmm0, %xmm2
1572 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
1573 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1574 ; SSE-NEXT: movdqa %xmm2, (%rdi)
1577 ; AVX1-LABEL: combine_test21:
1579 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
1580 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm0[0],xmm1[0]
1581 ; AVX1-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1582 ; AVX1-NEXT: vmovdqa %xmm2, (%rdi)
1583 ; AVX1-NEXT: vzeroupper
1586 ; AVX2-LABEL: combine_test21:
1588 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
1589 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm0[0],xmm1[0]
1590 ; AVX2-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1591 ; AVX2-NEXT: vmovdqa %xmm2, (%rdi)
1592 ; AVX2-NEXT: vzeroupper
1594 %1 = shufflevector <8 x i32> %a, <8 x i32> %a, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1595 %2 = shufflevector <8 x i32> %a, <8 x i32> %a, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
1596 store <4 x i32> %1, <4 x i32>* %ptr, align 16
1600 define <8 x float> @combine_test22(<2 x float>* %a, <2 x float>* %b) {
1601 ; SSE-LABEL: combine_test22:
1603 ; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
1604 ; SSE-NEXT: movhpd (%rsi), %xmm0
1607 ; AVX-LABEL: combine_test22:
1609 ; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
1610 ; AVX-NEXT: vmovhpd (%rsi), %xmm0, %xmm0
1612 ; Current AVX2 lowering of this is still awful, not adding a test case.
1613 %1 = load <2 x float>* %a, align 8
1614 %2 = load <2 x float>* %b, align 8
1615 %3 = shufflevector <2 x float> %1, <2 x float> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
1619 ; Check some negative cases.
1620 ; FIXME: Do any of these really make sense? Are they redundant with the above tests?
1622 define <4 x float> @combine_test1b(<4 x float> %a, <4 x float> %b) {
1623 ; SSE-LABEL: combine_test1b:
1625 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1,2,0]
1626 ; SSE-NEXT: movaps %xmm1, %xmm0
1629 ; AVX-LABEL: combine_test1b:
1631 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm1[0,1,2,0]
1633 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1634 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 0>
1638 define <4 x float> @combine_test2b(<4 x float> %a, <4 x float> %b) {
1639 ; SSE2-LABEL: combine_test2b:
1641 ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0,0]
1642 ; SSE2-NEXT: movaps %xmm1, %xmm0
1645 ; SSSE3-LABEL: combine_test2b:
1647 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
1650 ; SSE41-LABEL: combine_test2b:
1652 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
1655 ; AVX-LABEL: combine_test2b:
1657 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm1[0,0]
1659 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1660 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 0, i32 5>
1664 define <4 x float> @combine_test3b(<4 x float> %a, <4 x float> %b) {
1665 ; SSE2-LABEL: combine_test3b:
1667 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
1668 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
1671 ; SSSE3-LABEL: combine_test3b:
1673 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
1674 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
1677 ; SSE41-LABEL: combine_test3b:
1679 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
1680 ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3,2,3]
1683 ; AVX-LABEL: combine_test3b:
1685 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
1686 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,3,2,3]
1688 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 6, i32 3>
1689 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 7>
1693 define <4 x float> @combine_test4b(<4 x float> %a, <4 x float> %b) {
1694 ; SSE-LABEL: combine_test4b:
1696 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
1697 ; SSE-NEXT: movaps %xmm1, %xmm0
1700 ; AVX-LABEL: combine_test4b:
1702 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm1[1,1,2,3]
1704 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1705 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 5, i32 5, i32 2, i32 7>
1710 ; Verify that we correctly fold shuffles even when we use illegal vector types.
1712 define <4 x i8> @combine_test1c(<4 x i8>* %a, <4 x i8>* %b) {
1713 ; SSE2-LABEL: combine_test1c:
1715 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1716 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1717 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1718 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1719 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1720 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1721 ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
1724 ; SSSE3-LABEL: combine_test1c:
1726 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1727 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1728 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1729 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1730 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1731 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1732 ; SSSE3-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
1735 ; SSE41-LABEL: combine_test1c:
1737 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1738 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1739 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
1742 ; AVX1-LABEL: combine_test1c:
1744 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1745 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1746 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1749 ; AVX2-LABEL: combine_test1c:
1751 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1752 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1753 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1755 %A = load <4 x i8>* %a
1756 %B = load <4 x i8>* %b
1757 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1758 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1762 define <4 x i8> @combine_test2c(<4 x i8>* %a, <4 x i8>* %b) {
1763 ; SSE2-LABEL: combine_test2c:
1765 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1766 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1767 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1768 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1769 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1770 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1771 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1774 ; SSSE3-LABEL: combine_test2c:
1776 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1777 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1778 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1779 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1780 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1781 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1782 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1785 ; SSE41-LABEL: combine_test2c:
1787 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1788 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1789 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1792 ; AVX-LABEL: combine_test2c:
1794 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1795 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1796 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1798 %A = load <4 x i8>* %a
1799 %B = load <4 x i8>* %b
1800 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 1, i32 5>
1801 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1805 define <4 x i8> @combine_test3c(<4 x i8>* %a, <4 x i8>* %b) {
1806 ; SSE2-LABEL: combine_test3c:
1808 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1809 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1810 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1811 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1812 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1813 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1814 ; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1817 ; SSSE3-LABEL: combine_test3c:
1819 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1820 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1821 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1822 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1823 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1824 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1825 ; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1828 ; SSE41-LABEL: combine_test3c:
1830 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1831 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1832 ; SSE41-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1835 ; AVX-LABEL: combine_test3c:
1837 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1838 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1839 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1841 %A = load <4 x i8>* %a
1842 %B = load <4 x i8>* %b
1843 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1844 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1848 define <4 x i8> @combine_test4c(<4 x i8>* %a, <4 x i8>* %b) {
1849 ; SSE2-LABEL: combine_test4c:
1851 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1852 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1853 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1854 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1855 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1856 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1857 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1858 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1861 ; SSSE3-LABEL: combine_test4c:
1863 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1864 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1865 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1866 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1867 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1868 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1869 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1870 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1873 ; SSE41-LABEL: combine_test4c:
1875 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1876 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1877 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1880 ; AVX1-LABEL: combine_test4c:
1882 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1883 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1884 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1887 ; AVX2-LABEL: combine_test4c:
1889 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1890 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1891 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1893 %A = load <4 x i8>* %a
1894 %B = load <4 x i8>* %b
1895 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1896 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1901 ; The following test cases are generated from this C++ code
1903 ;__m128 blend_01(__m128 a, __m128 b)
1906 ; s = _mm_blend_ps( s, b, 1<<0 );
1907 ; s = _mm_blend_ps( s, b, 1<<1 );
1911 ;__m128 blend_02(__m128 a, __m128 b)
1914 ; s = _mm_blend_ps( s, b, 1<<0 );
1915 ; s = _mm_blend_ps( s, b, 1<<2 );
1919 ;__m128 blend_123(__m128 a, __m128 b)
1922 ; s = _mm_blend_ps( s, b, 1<<1 );
1923 ; s = _mm_blend_ps( s, b, 1<<2 );
1924 ; s = _mm_blend_ps( s, b, 1<<3 );
1928 ; Ideally, we should collapse the following shuffles into a single one.
1930 define <4 x float> @combine_blend_01(<4 x float> %a, <4 x float> %b) {
1931 ; SSE2-LABEL: combine_blend_01:
1933 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1936 ; SSSE3-LABEL: combine_blend_01:
1938 ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1941 ; SSE41-LABEL: combine_blend_01:
1943 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1946 ; AVX-LABEL: combine_blend_01:
1948 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1950 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 undef, i32 2, i32 3>
1951 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1952 ret <4 x float> %shuffle6
1955 define <4 x float> @combine_blend_02(<4 x float> %a, <4 x float> %b) {
1956 ; SSE2-LABEL: combine_blend_02:
1958 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
1959 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
1960 ; SSE2-NEXT: movaps %xmm1, %xmm0
1963 ; SSSE3-LABEL: combine_blend_02:
1965 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
1966 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
1967 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1970 ; SSE41-LABEL: combine_blend_02:
1972 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1975 ; AVX-LABEL: combine_blend_02:
1977 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1979 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 undef, i32 3>
1980 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1981 ret <4 x float> %shuffle6
1984 define <4 x float> @combine_blend_123(<4 x float> %a, <4 x float> %b) {
1985 ; SSE2-LABEL: combine_blend_123:
1987 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1988 ; SSE2-NEXT: movaps %xmm1, %xmm0
1991 ; SSSE3-LABEL: combine_blend_123:
1993 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1994 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1997 ; SSE41-LABEL: combine_blend_123:
1999 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
2002 ; AVX-LABEL: combine_blend_123:
2004 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
2006 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
2007 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
2008 %shuffle12 = shufflevector <4 x float> %shuffle6, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
2009 ret <4 x float> %shuffle12
2012 define <4 x i32> @combine_test_movhl_1(<4 x i32> %a, <4 x i32> %b) {
2013 ; SSE-LABEL: combine_test_movhl_1:
2015 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2016 ; SSE-NEXT: movdqa %xmm1, %xmm0
2019 ; AVX-LABEL: combine_test_movhl_1:
2021 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2023 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 7, i32 5, i32 3>
2024 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 0, i32 3>
2028 define <4 x i32> @combine_test_movhl_2(<4 x i32> %a, <4 x i32> %b) {
2029 ; SSE-LABEL: combine_test_movhl_2:
2031 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2032 ; SSE-NEXT: movdqa %xmm1, %xmm0
2035 ; AVX-LABEL: combine_test_movhl_2:
2037 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2039 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 0, i32 3, i32 6>
2040 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 3, i32 7, i32 0, i32 2>
2044 define <4 x i32> @combine_test_movhl_3(<4 x i32> %a, <4 x i32> %b) {
2045 ; SSE-LABEL: combine_test_movhl_3:
2047 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2048 ; SSE-NEXT: movdqa %xmm1, %xmm0
2051 ; AVX-LABEL: combine_test_movhl_3:
2053 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2055 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 6, i32 3, i32 2>
2056 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 0, i32 3, i32 2>
2061 ; Verify that we fold shuffles according to rule:
2062 ; (shuffle(shuffle A, Undef, M0), B, M1) -> (shuffle A, B, M2)
2064 define <4 x float> @combine_undef_input_test1(<4 x float> %a, <4 x float> %b) {
2065 ; SSE2-LABEL: combine_undef_input_test1:
2067 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2070 ; SSSE3-LABEL: combine_undef_input_test1:
2072 ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2075 ; SSE41-LABEL: combine_undef_input_test1:
2077 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2080 ; AVX-LABEL: combine_undef_input_test1:
2082 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2084 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2085 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2089 define <4 x float> @combine_undef_input_test2(<4 x float> %a, <4 x float> %b) {
2090 ; SSE-LABEL: combine_undef_input_test2:
2092 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2095 ; AVX-LABEL: combine_undef_input_test2:
2097 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2099 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2100 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2104 define <4 x float> @combine_undef_input_test3(<4 x float> %a, <4 x float> %b) {
2105 ; SSE-LABEL: combine_undef_input_test3:
2107 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2110 ; AVX-LABEL: combine_undef_input_test3:
2112 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2114 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2115 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2119 define <4 x float> @combine_undef_input_test4(<4 x float> %a, <4 x float> %b) {
2120 ; SSE-LABEL: combine_undef_input_test4:
2122 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2123 ; SSE-NEXT: movapd %xmm1, %xmm0
2126 ; AVX-LABEL: combine_undef_input_test4:
2128 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2130 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2131 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2135 define <4 x float> @combine_undef_input_test5(<4 x float> %a, <4 x float> %b) {
2136 ; SSE2-LABEL: combine_undef_input_test5:
2138 ; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2139 ; SSE2-NEXT: movapd %xmm1, %xmm0
2142 ; SSSE3-LABEL: combine_undef_input_test5:
2144 ; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2145 ; SSSE3-NEXT: movapd %xmm1, %xmm0
2148 ; SSE41-LABEL: combine_undef_input_test5:
2150 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2153 ; AVX-LABEL: combine_undef_input_test5:
2155 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2157 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2158 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2163 ; Verify that we fold shuffles according to rule:
2164 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2166 define <4 x float> @combine_undef_input_test6(<4 x float> %a) {
2167 ; ALL-LABEL: combine_undef_input_test6:
2170 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2171 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2175 define <4 x float> @combine_undef_input_test7(<4 x float> %a) {
2176 ; SSE2-LABEL: combine_undef_input_test7:
2178 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2181 ; SSSE3-LABEL: combine_undef_input_test7:
2183 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2186 ; SSE41-LABEL: combine_undef_input_test7:
2188 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2191 ; AVX-LABEL: combine_undef_input_test7:
2193 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2195 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2196 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2200 define <4 x float> @combine_undef_input_test8(<4 x float> %a) {
2201 ; SSE2-LABEL: combine_undef_input_test8:
2203 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2206 ; SSSE3-LABEL: combine_undef_input_test8:
2208 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2211 ; SSE41-LABEL: combine_undef_input_test8:
2213 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2216 ; AVX-LABEL: combine_undef_input_test8:
2218 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2220 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2221 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2225 define <4 x float> @combine_undef_input_test9(<4 x float> %a) {
2226 ; SSE-LABEL: combine_undef_input_test9:
2228 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2231 ; AVX-LABEL: combine_undef_input_test9:
2233 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2235 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2236 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2240 define <4 x float> @combine_undef_input_test10(<4 x float> %a) {
2241 ; ALL-LABEL: combine_undef_input_test10:
2244 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2245 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2249 define <4 x float> @combine_undef_input_test11(<4 x float> %a, <4 x float> %b) {
2250 ; SSE2-LABEL: combine_undef_input_test11:
2252 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2255 ; SSSE3-LABEL: combine_undef_input_test11:
2257 ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2260 ; SSE41-LABEL: combine_undef_input_test11:
2262 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2265 ; AVX-LABEL: combine_undef_input_test11:
2267 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2269 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2270 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 6>
2274 define <4 x float> @combine_undef_input_test12(<4 x float> %a, <4 x float> %b) {
2275 ; SSE-LABEL: combine_undef_input_test12:
2277 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2280 ; AVX-LABEL: combine_undef_input_test12:
2282 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2284 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2285 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2289 define <4 x float> @combine_undef_input_test13(<4 x float> %a, <4 x float> %b) {
2290 ; SSE-LABEL: combine_undef_input_test13:
2292 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2295 ; AVX-LABEL: combine_undef_input_test13:
2297 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2299 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2300 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 5, i32 0, i32 5>
2304 define <4 x float> @combine_undef_input_test14(<4 x float> %a, <4 x float> %b) {
2305 ; SSE-LABEL: combine_undef_input_test14:
2307 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2308 ; SSE-NEXT: movapd %xmm1, %xmm0
2311 ; AVX-LABEL: combine_undef_input_test14:
2313 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2315 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2316 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2320 define <4 x float> @combine_undef_input_test15(<4 x float> %a, <4 x float> %b) {
2321 ; SSE2-LABEL: combine_undef_input_test15:
2323 ; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2324 ; SSE2-NEXT: movapd %xmm1, %xmm0
2327 ; SSSE3-LABEL: combine_undef_input_test15:
2329 ; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2330 ; SSSE3-NEXT: movapd %xmm1, %xmm0
2333 ; SSE41-LABEL: combine_undef_input_test15:
2335 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2338 ; AVX-LABEL: combine_undef_input_test15:
2340 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2342 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2343 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2348 ; Verify that shuffles are canonicalized according to rules:
2349 ; shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
2351 ; This allows to trigger the following combine rule:
2352 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2354 ; As a result, all the shuffle pairs in each function below should be
2355 ; combined into a single legal shuffle operation.
2357 define <4 x float> @combine_undef_input_test16(<4 x float> %a) {
2358 ; ALL-LABEL: combine_undef_input_test16:
2361 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2362 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
2366 define <4 x float> @combine_undef_input_test17(<4 x float> %a) {
2367 ; SSE2-LABEL: combine_undef_input_test17:
2369 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2372 ; SSSE3-LABEL: combine_undef_input_test17:
2374 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2377 ; SSE41-LABEL: combine_undef_input_test17:
2379 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2382 ; AVX-LABEL: combine_undef_input_test17:
2384 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2386 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2387 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2391 define <4 x float> @combine_undef_input_test18(<4 x float> %a) {
2392 ; SSE2-LABEL: combine_undef_input_test18:
2394 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2397 ; SSSE3-LABEL: combine_undef_input_test18:
2399 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2402 ; SSE41-LABEL: combine_undef_input_test18:
2404 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2407 ; AVX-LABEL: combine_undef_input_test18:
2409 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2411 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2412 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 0, i32 5>
2416 define <4 x float> @combine_undef_input_test19(<4 x float> %a) {
2417 ; SSE-LABEL: combine_undef_input_test19:
2419 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2422 ; AVX-LABEL: combine_undef_input_test19:
2424 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2426 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2427 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2431 define <4 x float> @combine_undef_input_test20(<4 x float> %a) {
2432 ; ALL-LABEL: combine_undef_input_test20:
2435 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2436 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2440 ; These tests are designed to test the ability to combine away unnecessary
2441 ; operations feeding into a shuffle. The AVX cases are the important ones as
2442 ; they leverage operations which cannot be done naturally on the entire vector
2443 ; and thus are decomposed into multiple smaller operations.
2445 define <8 x i32> @combine_unneeded_subvector1(<8 x i32> %a) {
2446 ; SSE-LABEL: combine_unneeded_subvector1:
2448 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2449 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,2,1,0]
2450 ; SSE-NEXT: movdqa %xmm0, %xmm1
2453 ; AVX1-LABEL: combine_unneeded_subvector1:
2455 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2456 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2457 ; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
2458 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2461 ; AVX2-LABEL: combine_unneeded_subvector1:
2463 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2464 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [7,6,5,4,7,6,5,4]
2465 ; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
2467 %b = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2468 %c = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 7, i32 6, i32 5, i32 4>
2472 define <8 x i32> @combine_unneeded_subvector2(<8 x i32> %a, <8 x i32> %b) {
2473 ; SSE-LABEL: combine_unneeded_subvector2:
2475 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2476 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[3,2,1,0]
2477 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
2480 ; AVX1-LABEL: combine_unneeded_subvector2:
2482 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2483 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2484 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2485 ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
2486 ; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2489 ; AVX2-LABEL: combine_unneeded_subvector2:
2491 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2492 ; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
2493 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2495 %c = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2496 %d = shufflevector <8 x i32> %b, <8 x i32> %c, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 15, i32 14, i32 13, i32 12>
2500 define <4 x float> @combine_insertps1(<4 x float> %a, <4 x float> %b) {
2501 ; SSE2-LABEL: combine_insertps1:
2503 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,0]
2504 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[2,3]
2505 ; SSE2-NEXT: movaps %xmm1, %xmm0
2508 ; SSSE3-LABEL: combine_insertps1:
2510 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,0]
2511 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[2,3]
2512 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2515 ; SSE41-LABEL: combine_insertps1:
2517 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
2520 ; AVX-LABEL: combine_insertps1:
2522 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
2525 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 6, i32 2, i32 4>
2526 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32> <i32 5, i32 1, i32 6, i32 3>
2530 define <4 x float> @combine_insertps2(<4 x float> %a, <4 x float> %b) {
2531 ; SSE2-LABEL: combine_insertps2:
2533 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,0]
2534 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
2535 ; SSE2-NEXT: movaps %xmm1, %xmm0
2538 ; SSSE3-LABEL: combine_insertps2:
2540 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,0]
2541 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
2542 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2545 ; SSE41-LABEL: combine_insertps2:
2547 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
2550 ; AVX-LABEL: combine_insertps2:
2552 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
2555 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 1, i32 6, i32 7>
2556 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2560 define <4 x float> @combine_insertps3(<4 x float> %a, <4 x float> %b) {
2561 ; SSE2-LABEL: combine_insertps3:
2563 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
2564 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2567 ; SSSE3-LABEL: combine_insertps3:
2569 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
2570 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2573 ; SSE41-LABEL: combine_insertps3:
2575 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
2578 ; AVX-LABEL: combine_insertps3:
2580 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
2583 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
2584 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 5, i32 3>
2588 define <4 x float> @combine_insertps4(<4 x float> %a, <4 x float> %b) {
2589 ; SSE2-LABEL: combine_insertps4:
2591 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
2592 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
2595 ; SSSE3-LABEL: combine_insertps4:
2597 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
2598 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
2601 ; SSE41-LABEL: combine_insertps4:
2603 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
2606 ; AVX-LABEL: combine_insertps4:
2608 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
2611 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
2612 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 6, i32 5>
2616 define <4 x float> @PR22377(<4 x float> %a, <4 x float> %b) {
2617 ; SSE-LABEL: PR22377:
2618 ; SSE: # BB#0: # %entry
2619 ; SSE-NEXT: movaps %xmm0, %xmm1
2620 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3,1,3]
2621 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,0,2]
2622 ; SSE-NEXT: addps %xmm0, %xmm1
2623 ; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
2626 ; AVX-LABEL: PR22377:
2627 ; AVX: # BB#0: # %entry
2628 ; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[1,3,1,3]
2629 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,0,2]
2630 ; AVX-NEXT: vaddps %xmm0, %xmm1, %xmm1
2631 ; AVX-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
2634 %s1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 1, i32 3>
2635 %s2 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
2636 %r2 = fadd <4 x float> %s1, %s2
2637 %s3 = shufflevector <4 x float> %s2, <4 x float> %r2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
2641 define <4 x float> @PR22390(<4 x float> %a, <4 x float> %b) {
2642 ; SSE2-LABEL: PR22390:
2643 ; SSE2: # BB#0: # %entry
2644 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0,1,2]
2645 ; SSE2-NEXT: movaps %xmm0, %xmm2
2646 ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
2647 ; SSE2-NEXT: addps %xmm0, %xmm2
2648 ; SSE2-NEXT: movaps %xmm2, %xmm0
2651 ; SSSE3-LABEL: PR22390:
2652 ; SSSE3: # BB#0: # %entry
2653 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0,1,2]
2654 ; SSSE3-NEXT: movaps %xmm0, %xmm2
2655 ; SSSE3-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
2656 ; SSSE3-NEXT: addps %xmm0, %xmm2
2657 ; SSSE3-NEXT: movaps %xmm2, %xmm0
2660 ; SSE41-LABEL: PR22390:
2661 ; SSE41: # BB#0: # %entry
2662 ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0,1,2]
2663 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm0[1,2,3]
2664 ; SSE41-NEXT: addps %xmm1, %xmm0
2667 ; AVX-LABEL: PR22390:
2668 ; AVX: # BB#0: # %entry
2669 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,0,1,2]
2670 ; AVX-NEXT: vblendps {{.*#+}} xmm1 = xmm1[0],xmm0[1,2,3]
2671 ; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
2674 %s1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
2675 %s2 = shufflevector <4 x float> %s1, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
2676 %r2 = fadd <4 x float> %s1, %s2
2680 define <8 x float> @PR22412(<8 x float> %a, <8 x float> %b) {
2681 ; SSE2-LABEL: PR22412:
2682 ; SSE2: # BB#0: # %entry
2683 ; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
2684 ; SSE2-NEXT: movapd %xmm2, %xmm0
2685 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm3[3,2]
2686 ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,0],xmm2[3,2]
2687 ; SSE2-NEXT: movaps %xmm3, %xmm1
2690 ; SSSE3-LABEL: PR22412:
2691 ; SSSE3: # BB#0: # %entry
2692 ; SSSE3-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
2693 ; SSSE3-NEXT: movapd %xmm2, %xmm0
2694 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm3[3,2]
2695 ; SSSE3-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,0],xmm2[3,2]
2696 ; SSSE3-NEXT: movaps %xmm3, %xmm1
2699 ; SSE41-LABEL: PR22412:
2700 ; SSE41: # BB#0: # %entry
2701 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm2[1]
2702 ; SSE41-NEXT: movapd %xmm0, %xmm1
2703 ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm3[3,2]
2704 ; SSE41-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,0],xmm0[3,2]
2705 ; SSE41-NEXT: movaps %xmm1, %xmm0
2706 ; SSE41-NEXT: movaps %xmm3, %xmm1
2709 ; AVX1-LABEL: PR22412:
2710 ; AVX1: # BB#0: # %entry
2711 ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
2712 ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
2713 ; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,0],ymm1[3,2],ymm0[5,4],ymm1[7,6]
2716 ; AVX2-LABEL: PR22412:
2717 ; AVX2: # BB#0: # %entry
2718 ; AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
2719 ; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [1,0,7,6,5,4,3,2]
2720 ; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
2723 %s1 = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 1, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
2724 %s2 = shufflevector <8 x float> %s1, <8 x float> undef, <8 x i32> <i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2>