1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
3 ; RUN: llc < %s -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
4 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
5 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
6 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
8 ; Verify that the DAG combiner correctly folds bitwise operations across
9 ; shuffles, nested shuffles with undef, pairs of nested shuffles, and other
10 ; basic and always-safe patterns. Also test that the DAG combiner will combine
11 ; target-specific shuffle instructions where reasonable.
13 target triple = "x86_64-unknown-unknown"
15 declare <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32>, i8)
16 declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8)
17 declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8)
19 define <4 x i32> @combine_pshufd1(<4 x i32> %a) {
20 ; ALL-LABEL: combine_pshufd1:
21 ; ALL: # BB#0: # %entry
24 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
25 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 27)
29 define <4 x i32> @combine_pshufd2(<4 x i32> %a) {
30 ; ALL-LABEL: combine_pshufd2:
31 ; ALL: # BB#0: # %entry
34 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
35 %b.cast = bitcast <4 x i32> %b to <8 x i16>
36 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 -28)
37 %c.cast = bitcast <8 x i16> %c to <4 x i32>
38 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
42 define <4 x i32> @combine_pshufd3(<4 x i32> %a) {
43 ; ALL-LABEL: combine_pshufd3:
44 ; ALL: # BB#0: # %entry
47 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
48 %b.cast = bitcast <4 x i32> %b to <8 x i16>
49 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 -28)
50 %c.cast = bitcast <8 x i16> %c to <4 x i32>
51 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
55 define <4 x i32> @combine_pshufd4(<4 x i32> %a) {
56 ; SSE-LABEL: combine_pshufd4:
57 ; SSE: # BB#0: # %entry
58 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
61 ; AVX-LABEL: combine_pshufd4:
62 ; AVX: # BB#0: # %entry
63 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
66 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -31)
67 %b.cast = bitcast <4 x i32> %b to <8 x i16>
68 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 27)
69 %c.cast = bitcast <8 x i16> %c to <4 x i32>
70 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -31)
74 define <4 x i32> @combine_pshufd5(<4 x i32> %a) {
75 ; SSE-LABEL: combine_pshufd5:
76 ; SSE: # BB#0: # %entry
77 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
80 ; AVX-LABEL: combine_pshufd5:
81 ; AVX: # BB#0: # %entry
82 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
85 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -76)
86 %b.cast = bitcast <4 x i32> %b to <8 x i16>
87 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 27)
88 %c.cast = bitcast <8 x i16> %c to <4 x i32>
89 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -76)
93 define <4 x i32> @combine_pshufd6(<4 x i32> %a) {
94 ; SSE-LABEL: combine_pshufd6:
95 ; SSE: # BB#0: # %entry
96 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
99 ; AVX-LABEL: combine_pshufd6:
100 ; AVX: # BB#0: # %entry
101 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
104 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 0)
105 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 8)
109 define <8 x i16> @combine_pshuflw1(<8 x i16> %a) {
110 ; ALL-LABEL: combine_pshuflw1:
111 ; ALL: # BB#0: # %entry
114 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
115 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
119 define <8 x i16> @combine_pshuflw2(<8 x i16> %a) {
120 ; ALL-LABEL: combine_pshuflw2:
121 ; ALL: # BB#0: # %entry
124 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
125 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 -28)
126 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
130 define <8 x i16> @combine_pshuflw3(<8 x i16> %a) {
131 ; SSE-LABEL: combine_pshuflw3:
132 ; SSE: # BB#0: # %entry
133 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
136 ; AVX-LABEL: combine_pshuflw3:
137 ; AVX: # BB#0: # %entry
138 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
141 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
142 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 27)
143 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
147 define <8 x i16> @combine_pshufhw1(<8 x i16> %a) {
148 ; SSE-LABEL: combine_pshufhw1:
149 ; SSE: # BB#0: # %entry
150 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
153 ; AVX-LABEL: combine_pshufhw1:
154 ; AVX: # BB#0: # %entry
155 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
158 %b = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27)
159 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
160 %d = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %c, i8 27)
164 define <4 x i32> @combine_bitwise_ops_test1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
165 ; SSE-LABEL: combine_bitwise_ops_test1:
167 ; SSE-NEXT: pand %xmm1, %xmm0
168 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
171 ; AVX-LABEL: combine_bitwise_ops_test1:
173 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
174 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
176 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
177 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
178 %and = and <4 x i32> %shuf1, %shuf2
182 define <4 x i32> @combine_bitwise_ops_test2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
183 ; SSE-LABEL: combine_bitwise_ops_test2:
185 ; SSE-NEXT: por %xmm1, %xmm0
186 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
189 ; AVX-LABEL: combine_bitwise_ops_test2:
191 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
192 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
194 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
195 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
196 %or = or <4 x i32> %shuf1, %shuf2
200 define <4 x i32> @combine_bitwise_ops_test3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
201 ; SSE-LABEL: combine_bitwise_ops_test3:
203 ; SSE-NEXT: pxor %xmm1, %xmm0
204 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
207 ; AVX-LABEL: combine_bitwise_ops_test3:
209 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
210 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
212 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
213 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
214 %xor = xor <4 x i32> %shuf1, %shuf2
218 define <4 x i32> @combine_bitwise_ops_test4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
219 ; SSE-LABEL: combine_bitwise_ops_test4:
221 ; SSE-NEXT: pand %xmm1, %xmm0
222 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
225 ; AVX-LABEL: combine_bitwise_ops_test4:
227 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
228 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
230 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
231 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
232 %and = and <4 x i32> %shuf1, %shuf2
236 define <4 x i32> @combine_bitwise_ops_test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
237 ; SSE-LABEL: combine_bitwise_ops_test5:
239 ; SSE-NEXT: por %xmm1, %xmm0
240 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
243 ; AVX-LABEL: combine_bitwise_ops_test5:
245 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
246 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
248 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
249 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
250 %or = or <4 x i32> %shuf1, %shuf2
254 define <4 x i32> @combine_bitwise_ops_test6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
255 ; SSE-LABEL: combine_bitwise_ops_test6:
257 ; SSE-NEXT: pxor %xmm1, %xmm0
258 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
261 ; AVX-LABEL: combine_bitwise_ops_test6:
263 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
264 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
266 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
267 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
268 %xor = xor <4 x i32> %shuf1, %shuf2
273 ; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles
274 ; are not performing a swizzle operations.
276 define <4 x i32> @combine_bitwise_ops_test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
277 ; SSE2-LABEL: combine_bitwise_ops_test1b:
279 ; SSE2-NEXT: pand %xmm1, %xmm0
280 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
281 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
282 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
285 ; SSSE3-LABEL: combine_bitwise_ops_test1b:
287 ; SSSE3-NEXT: pand %xmm1, %xmm0
288 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
289 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
290 ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
293 ; SSE41-LABEL: combine_bitwise_ops_test1b:
295 ; SSE41-NEXT: pand %xmm1, %xmm0
296 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
299 ; AVX1-LABEL: combine_bitwise_ops_test1b:
301 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
302 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
305 ; AVX2-LABEL: combine_bitwise_ops_test1b:
307 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
308 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
310 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
311 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
312 %and = and <4 x i32> %shuf1, %shuf2
316 define <4 x i32> @combine_bitwise_ops_test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
317 ; SSE2-LABEL: combine_bitwise_ops_test2b:
319 ; SSE2-NEXT: por %xmm1, %xmm0
320 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
321 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
322 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
325 ; SSSE3-LABEL: combine_bitwise_ops_test2b:
327 ; SSSE3-NEXT: por %xmm1, %xmm0
328 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
329 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
330 ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
333 ; SSE41-LABEL: combine_bitwise_ops_test2b:
335 ; SSE41-NEXT: por %xmm1, %xmm0
336 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
339 ; AVX1-LABEL: combine_bitwise_ops_test2b:
341 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
342 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
345 ; AVX2-LABEL: combine_bitwise_ops_test2b:
347 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
348 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
350 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
351 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
352 %or = or <4 x i32> %shuf1, %shuf2
356 define <4 x i32> @combine_bitwise_ops_test3b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
357 ; SSE2-LABEL: combine_bitwise_ops_test3b:
359 ; SSE2-NEXT: xorps %xmm1, %xmm0
360 ; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
363 ; SSSE3-LABEL: combine_bitwise_ops_test3b:
365 ; SSSE3-NEXT: xorps %xmm1, %xmm0
366 ; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
369 ; SSE41-LABEL: combine_bitwise_ops_test3b:
371 ; SSE41-NEXT: pxor %xmm1, %xmm0
372 ; SSE41-NEXT: pxor %xmm1, %xmm1
373 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
376 ; AVX1-LABEL: combine_bitwise_ops_test3b:
378 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
379 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
380 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
383 ; AVX2-LABEL: combine_bitwise_ops_test3b:
385 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
386 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
387 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
389 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
390 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
391 %xor = xor <4 x i32> %shuf1, %shuf2
395 define <4 x i32> @combine_bitwise_ops_test4b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
396 ; SSE2-LABEL: combine_bitwise_ops_test4b:
398 ; SSE2-NEXT: pand %xmm1, %xmm0
399 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
400 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
401 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
404 ; SSSE3-LABEL: combine_bitwise_ops_test4b:
406 ; SSSE3-NEXT: pand %xmm1, %xmm0
407 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
408 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
409 ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
412 ; SSE41-LABEL: combine_bitwise_ops_test4b:
414 ; SSE41-NEXT: pand %xmm1, %xmm0
415 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
418 ; AVX1-LABEL: combine_bitwise_ops_test4b:
420 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
421 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
424 ; AVX2-LABEL: combine_bitwise_ops_test4b:
426 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
427 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
429 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
430 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
431 %and = and <4 x i32> %shuf1, %shuf2
435 define <4 x i32> @combine_bitwise_ops_test5b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
436 ; SSE2-LABEL: combine_bitwise_ops_test5b:
438 ; SSE2-NEXT: por %xmm1, %xmm0
439 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
440 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
441 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
444 ; SSSE3-LABEL: combine_bitwise_ops_test5b:
446 ; SSSE3-NEXT: por %xmm1, %xmm0
447 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
448 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
449 ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
452 ; SSE41-LABEL: combine_bitwise_ops_test5b:
454 ; SSE41-NEXT: por %xmm1, %xmm0
455 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
458 ; AVX1-LABEL: combine_bitwise_ops_test5b:
460 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
461 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
464 ; AVX2-LABEL: combine_bitwise_ops_test5b:
466 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
467 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
469 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
470 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
471 %or = or <4 x i32> %shuf1, %shuf2
475 define <4 x i32> @combine_bitwise_ops_test6b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
476 ; SSE2-LABEL: combine_bitwise_ops_test6b:
478 ; SSE2-NEXT: xorps %xmm1, %xmm0
479 ; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
482 ; SSSE3-LABEL: combine_bitwise_ops_test6b:
484 ; SSSE3-NEXT: xorps %xmm1, %xmm0
485 ; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
488 ; SSE41-LABEL: combine_bitwise_ops_test6b:
490 ; SSE41-NEXT: pxor %xmm1, %xmm0
491 ; SSE41-NEXT: pxor %xmm1, %xmm1
492 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
495 ; AVX1-LABEL: combine_bitwise_ops_test6b:
497 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
498 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
499 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
502 ; AVX2-LABEL: combine_bitwise_ops_test6b:
504 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
505 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
506 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
508 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
509 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
510 %xor = xor <4 x i32> %shuf1, %shuf2
514 define <4 x i32> @combine_bitwise_ops_test1c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
515 ; SSE2-LABEL: combine_bitwise_ops_test1c:
517 ; SSE2-NEXT: pand %xmm1, %xmm0
518 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
519 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
520 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
523 ; SSSE3-LABEL: combine_bitwise_ops_test1c:
525 ; SSSE3-NEXT: pand %xmm1, %xmm0
526 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
527 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
528 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
531 ; SSE41-LABEL: combine_bitwise_ops_test1c:
533 ; SSE41-NEXT: pand %xmm1, %xmm0
534 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
535 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
538 ; AVX1-LABEL: combine_bitwise_ops_test1c:
540 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
541 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
542 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
545 ; AVX2-LABEL: combine_bitwise_ops_test1c:
547 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
548 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
549 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
551 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
552 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
553 %and = and <4 x i32> %shuf1, %shuf2
557 define <4 x i32> @combine_bitwise_ops_test2c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
558 ; SSE2-LABEL: combine_bitwise_ops_test2c:
560 ; SSE2-NEXT: por %xmm1, %xmm0
561 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
562 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
563 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
566 ; SSSE3-LABEL: combine_bitwise_ops_test2c:
568 ; SSSE3-NEXT: por %xmm1, %xmm0
569 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
570 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
571 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
574 ; SSE41-LABEL: combine_bitwise_ops_test2c:
576 ; SSE41-NEXT: por %xmm1, %xmm0
577 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
578 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
581 ; AVX1-LABEL: combine_bitwise_ops_test2c:
583 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
584 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
585 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
588 ; AVX2-LABEL: combine_bitwise_ops_test2c:
590 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
591 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
592 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
594 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
595 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
596 %or = or <4 x i32> %shuf1, %shuf2
600 define <4 x i32> @combine_bitwise_ops_test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
601 ; SSE2-LABEL: combine_bitwise_ops_test3c:
603 ; SSE2-NEXT: pxor %xmm1, %xmm0
604 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,2]
605 ; SSE2-NEXT: pxor %xmm1, %xmm1
606 ; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
609 ; SSSE3-LABEL: combine_bitwise_ops_test3c:
611 ; SSSE3-NEXT: pxor %xmm1, %xmm0
612 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,2]
613 ; SSSE3-NEXT: pxor %xmm1, %xmm1
614 ; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
617 ; SSE41-LABEL: combine_bitwise_ops_test3c:
619 ; SSE41-NEXT: pxor %xmm1, %xmm0
620 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
621 ; SSE41-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
624 ; AVX-LABEL: combine_bitwise_ops_test3c:
626 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
627 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
628 ; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
630 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
631 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
632 %xor = xor <4 x i32> %shuf1, %shuf2
636 define <4 x i32> @combine_bitwise_ops_test4c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
637 ; SSE2-LABEL: combine_bitwise_ops_test4c:
639 ; SSE2-NEXT: pand %xmm1, %xmm0
640 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
641 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
642 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
645 ; SSSE3-LABEL: combine_bitwise_ops_test4c:
647 ; SSSE3-NEXT: pand %xmm1, %xmm0
648 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
649 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
650 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
653 ; SSE41-LABEL: combine_bitwise_ops_test4c:
655 ; SSE41-NEXT: pand %xmm1, %xmm0
656 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
657 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
660 ; AVX1-LABEL: combine_bitwise_ops_test4c:
662 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
663 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
664 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
667 ; AVX2-LABEL: combine_bitwise_ops_test4c:
669 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
670 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
671 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
673 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
674 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
675 %and = and <4 x i32> %shuf1, %shuf2
679 define <4 x i32> @combine_bitwise_ops_test5c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
680 ; SSE2-LABEL: combine_bitwise_ops_test5c:
682 ; SSE2-NEXT: por %xmm1, %xmm0
683 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
684 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
685 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
688 ; SSSE3-LABEL: combine_bitwise_ops_test5c:
690 ; SSSE3-NEXT: por %xmm1, %xmm0
691 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
692 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
693 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
696 ; SSE41-LABEL: combine_bitwise_ops_test5c:
698 ; SSE41-NEXT: por %xmm1, %xmm0
699 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
700 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
703 ; AVX1-LABEL: combine_bitwise_ops_test5c:
705 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
706 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
707 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
710 ; AVX2-LABEL: combine_bitwise_ops_test5c:
712 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
713 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
714 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
716 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
717 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
718 %or = or <4 x i32> %shuf1, %shuf2
722 define <4 x i32> @combine_bitwise_ops_test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
723 ; SSE2-LABEL: combine_bitwise_ops_test6c:
725 ; SSE2-NEXT: pxor %xmm1, %xmm0
726 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
727 ; SSE2-NEXT: pxor %xmm0, %xmm0
728 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
731 ; SSSE3-LABEL: combine_bitwise_ops_test6c:
733 ; SSSE3-NEXT: pxor %xmm1, %xmm0
734 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
735 ; SSSE3-NEXT: pxor %xmm0, %xmm0
736 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
739 ; SSE41-LABEL: combine_bitwise_ops_test6c:
741 ; SSE41-NEXT: pxor %xmm1, %xmm0
742 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
743 ; SSE41-NEXT: pxor %xmm0, %xmm0
744 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
747 ; AVX1-LABEL: combine_bitwise_ops_test6c:
749 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
750 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
751 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
752 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
755 ; AVX2-LABEL: combine_bitwise_ops_test6c:
757 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
758 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
759 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
760 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
762 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
763 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
764 %xor = xor <4 x i32> %shuf1, %shuf2
768 define <4 x i32> @combine_nested_undef_test1(<4 x i32> %A, <4 x i32> %B) {
769 ; SSE-LABEL: combine_nested_undef_test1:
771 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
774 ; AVX-LABEL: combine_nested_undef_test1:
776 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
778 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
779 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
783 define <4 x i32> @combine_nested_undef_test2(<4 x i32> %A, <4 x i32> %B) {
784 ; SSE-LABEL: combine_nested_undef_test2:
786 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
789 ; AVX-LABEL: combine_nested_undef_test2:
791 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
793 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
794 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
798 define <4 x i32> @combine_nested_undef_test3(<4 x i32> %A, <4 x i32> %B) {
799 ; SSE-LABEL: combine_nested_undef_test3:
801 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
804 ; AVX-LABEL: combine_nested_undef_test3:
806 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
808 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
809 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
813 define <4 x i32> @combine_nested_undef_test4(<4 x i32> %A, <4 x i32> %B) {
814 ; SSE-LABEL: combine_nested_undef_test4:
816 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
819 ; AVX1-LABEL: combine_nested_undef_test4:
821 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
824 ; AVX2-LABEL: combine_nested_undef_test4:
826 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
828 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 7, i32 1>
829 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 3>
833 define <4 x i32> @combine_nested_undef_test5(<4 x i32> %A, <4 x i32> %B) {
834 ; SSE-LABEL: combine_nested_undef_test5:
836 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
839 ; AVX-LABEL: combine_nested_undef_test5:
841 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
843 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 5, i32 5, i32 2, i32 3>
844 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 4, i32 3>
848 define <4 x i32> @combine_nested_undef_test6(<4 x i32> %A, <4 x i32> %B) {
849 ; SSE-LABEL: combine_nested_undef_test6:
851 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
854 ; AVX-LABEL: combine_nested_undef_test6:
856 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
858 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
859 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 4>
863 define <4 x i32> @combine_nested_undef_test7(<4 x i32> %A, <4 x i32> %B) {
864 ; SSE-LABEL: combine_nested_undef_test7:
866 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
869 ; AVX-LABEL: combine_nested_undef_test7:
871 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
873 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
874 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
878 define <4 x i32> @combine_nested_undef_test8(<4 x i32> %A, <4 x i32> %B) {
879 ; SSE-LABEL: combine_nested_undef_test8:
881 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
884 ; AVX-LABEL: combine_nested_undef_test8:
886 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
888 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
889 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
893 define <4 x i32> @combine_nested_undef_test9(<4 x i32> %A, <4 x i32> %B) {
894 ; SSE-LABEL: combine_nested_undef_test9:
896 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
899 ; AVX-LABEL: combine_nested_undef_test9:
901 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
903 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 2, i32 5>
904 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
908 define <4 x i32> @combine_nested_undef_test10(<4 x i32> %A, <4 x i32> %B) {
909 ; SSE-LABEL: combine_nested_undef_test10:
911 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
914 ; AVX-LABEL: combine_nested_undef_test10:
916 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
918 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 5>
919 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 4>
923 define <4 x i32> @combine_nested_undef_test11(<4 x i32> %A, <4 x i32> %B) {
924 ; SSE-LABEL: combine_nested_undef_test11:
926 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
929 ; AVX-LABEL: combine_nested_undef_test11:
931 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
933 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 2, i32 5, i32 4>
934 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 0>
938 define <4 x i32> @combine_nested_undef_test12(<4 x i32> %A, <4 x i32> %B) {
939 ; SSE-LABEL: combine_nested_undef_test12:
941 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
944 ; AVX1-LABEL: combine_nested_undef_test12:
946 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
949 ; AVX2-LABEL: combine_nested_undef_test12:
951 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
953 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 0, i32 2, i32 4>
954 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 0, i32 4>
958 ; The following pair of shuffles is folded into vector %A.
959 define <4 x i32> @combine_nested_undef_test13(<4 x i32> %A, <4 x i32> %B) {
960 ; ALL-LABEL: combine_nested_undef_test13:
963 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 4, i32 2, i32 6>
964 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 0, i32 2, i32 4>
968 ; The following pair of shuffles is folded into vector %B.
969 define <4 x i32> @combine_nested_undef_test14(<4 x i32> %A, <4 x i32> %B) {
970 ; SSE-LABEL: combine_nested_undef_test14:
972 ; SSE-NEXT: movaps %xmm1, %xmm0
975 ; AVX-LABEL: combine_nested_undef_test14:
977 ; AVX-NEXT: vmovaps %xmm1, %xmm0
979 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
980 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 4, i32 1, i32 4>
985 ; Verify that we don't optimize the following cases. We expect more than one shuffle.
987 ; FIXME: Many of these already don't make sense, and the rest should stop
988 ; making sense with th enew vector shuffle lowering. Revisit at least testing for
991 define <4 x i32> @combine_nested_undef_test15(<4 x i32> %A, <4 x i32> %B) {
992 ; SSE2-LABEL: combine_nested_undef_test15:
994 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
995 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,1]
996 ; SSE2-NEXT: movaps %xmm1, %xmm0
999 ; SSSE3-LABEL: combine_nested_undef_test15:
1001 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
1002 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,1]
1003 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1006 ; SSE41-LABEL: combine_nested_undef_test15:
1008 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
1009 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
1010 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1013 ; AVX1-LABEL: combine_nested_undef_test15:
1015 ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
1016 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
1017 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1020 ; AVX2-LABEL: combine_nested_undef_test15:
1022 ; AVX2-NEXT: vpbroadcastd %xmm1, %xmm1
1023 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
1024 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
1026 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
1027 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
1031 define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
1032 ; SSE2-LABEL: combine_nested_undef_test16:
1034 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
1035 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,2,3]
1036 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1039 ; SSSE3-LABEL: combine_nested_undef_test16:
1041 ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
1042 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,2,3]
1043 ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1046 ; SSE41-LABEL: combine_nested_undef_test16:
1048 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
1049 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
1052 ; AVX1-LABEL: combine_nested_undef_test16:
1054 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
1055 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
1058 ; AVX2-LABEL: combine_nested_undef_test16:
1060 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
1061 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
1063 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1064 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
1068 define <4 x i32> @combine_nested_undef_test17(<4 x i32> %A, <4 x i32> %B) {
1069 ; SSE2-LABEL: combine_nested_undef_test17:
1071 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
1072 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1],xmm1[0,2]
1075 ; SSSE3-LABEL: combine_nested_undef_test17:
1077 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
1078 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1],xmm1[0,2]
1081 ; SSE41-LABEL: combine_nested_undef_test17:
1083 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
1084 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
1087 ; AVX1-LABEL: combine_nested_undef_test17:
1089 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
1090 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
1093 ; AVX2-LABEL: combine_nested_undef_test17:
1095 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
1096 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
1098 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
1099 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
1103 define <4 x i32> @combine_nested_undef_test18(<4 x i32> %A, <4 x i32> %B) {
1104 ; SSE-LABEL: combine_nested_undef_test18:
1106 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
1109 ; AVX-LABEL: combine_nested_undef_test18:
1111 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
1113 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1114 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 3>
1118 define <4 x i32> @combine_nested_undef_test19(<4 x i32> %A, <4 x i32> %B) {
1119 ; SSE2-LABEL: combine_nested_undef_test19:
1121 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1122 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,0,0,0]
1125 ; SSSE3-LABEL: combine_nested_undef_test19:
1127 ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1128 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,0,0,0]
1131 ; SSE41-LABEL: combine_nested_undef_test19:
1133 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1134 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,0,0]
1137 ; AVX1-LABEL: combine_nested_undef_test19:
1139 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1140 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,0,0]
1143 ; AVX2-LABEL: combine_nested_undef_test19:
1145 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
1146 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,0,0]
1148 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
1149 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
1153 define <4 x i32> @combine_nested_undef_test20(<4 x i32> %A, <4 x i32> %B) {
1154 ; SSE2-LABEL: combine_nested_undef_test20:
1156 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,3]
1157 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
1158 ; SSE2-NEXT: movaps %xmm1, %xmm0
1161 ; SSSE3-LABEL: combine_nested_undef_test20:
1163 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,3]
1164 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
1165 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1168 ; SSE41-LABEL: combine_nested_undef_test20:
1170 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
1171 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,3,0]
1174 ; AVX1-LABEL: combine_nested_undef_test20:
1176 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
1177 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,3,0]
1180 ; AVX2-LABEL: combine_nested_undef_test20:
1182 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
1183 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,3,0]
1185 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
1186 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
1190 define <4 x i32> @combine_nested_undef_test21(<4 x i32> %A, <4 x i32> %B) {
1191 ; SSE2-LABEL: combine_nested_undef_test21:
1193 ; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
1194 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,0,3]
1197 ; SSSE3-LABEL: combine_nested_undef_test21:
1199 ; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
1200 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,0,3]
1203 ; SSE41-LABEL: combine_nested_undef_test21:
1205 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1206 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1209 ; AVX1-LABEL: combine_nested_undef_test21:
1211 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1212 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1215 ; AVX2-LABEL: combine_nested_undef_test21:
1217 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1218 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1220 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
1221 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1226 ; Test that we correctly combine shuffles according to rule
1227 ; shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
1229 define <4 x i32> @combine_nested_undef_test22(<4 x i32> %A, <4 x i32> %B) {
1230 ; SSE-LABEL: combine_nested_undef_test22:
1232 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1235 ; AVX-LABEL: combine_nested_undef_test22:
1237 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1239 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1240 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 3>
1244 define <4 x i32> @combine_nested_undef_test23(<4 x i32> %A, <4 x i32> %B) {
1245 ; SSE-LABEL: combine_nested_undef_test23:
1247 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1250 ; AVX-LABEL: combine_nested_undef_test23:
1252 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1254 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1255 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1259 define <4 x i32> @combine_nested_undef_test24(<4 x i32> %A, <4 x i32> %B) {
1260 ; SSE-LABEL: combine_nested_undef_test24:
1262 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1265 ; AVX-LABEL: combine_nested_undef_test24:
1267 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1269 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1270 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 4>
1274 define <4 x i32> @combine_nested_undef_test25(<4 x i32> %A, <4 x i32> %B) {
1275 ; SSE-LABEL: combine_nested_undef_test25:
1277 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1280 ; AVX1-LABEL: combine_nested_undef_test25:
1282 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1285 ; AVX2-LABEL: combine_nested_undef_test25:
1287 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1289 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 5, i32 2, i32 4>
1290 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 3, i32 1>
1294 define <4 x i32> @combine_nested_undef_test26(<4 x i32> %A, <4 x i32> %B) {
1295 ; SSE-LABEL: combine_nested_undef_test26:
1297 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1300 ; AVX-LABEL: combine_nested_undef_test26:
1302 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1304 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 6, i32 7>
1305 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
1309 define <4 x i32> @combine_nested_undef_test27(<4 x i32> %A, <4 x i32> %B) {
1310 ; SSE-LABEL: combine_nested_undef_test27:
1312 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1315 ; AVX1-LABEL: combine_nested_undef_test27:
1317 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1320 ; AVX2-LABEL: combine_nested_undef_test27:
1322 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1324 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 2, i32 1, i32 5, i32 4>
1325 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
1329 define <4 x i32> @combine_nested_undef_test28(<4 x i32> %A, <4 x i32> %B) {
1330 ; SSE-LABEL: combine_nested_undef_test28:
1332 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1335 ; AVX-LABEL: combine_nested_undef_test28:
1337 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1339 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
1340 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 3, i32 2>
1344 define <4 x float> @combine_test1(<4 x float> %a, <4 x float> %b) {
1345 ; SSE-LABEL: combine_test1:
1347 ; SSE-NEXT: movaps %xmm1, %xmm0
1350 ; AVX-LABEL: combine_test1:
1352 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1354 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1355 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1359 define <4 x float> @combine_test2(<4 x float> %a, <4 x float> %b) {
1360 ; SSE2-LABEL: combine_test2:
1362 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1363 ; SSE2-NEXT: movaps %xmm1, %xmm0
1366 ; SSSE3-LABEL: combine_test2:
1368 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1369 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1372 ; SSE41-LABEL: combine_test2:
1374 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1377 ; AVX-LABEL: combine_test2:
1379 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1381 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1382 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1386 define <4 x float> @combine_test3(<4 x float> %a, <4 x float> %b) {
1387 ; SSE-LABEL: combine_test3:
1389 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1392 ; AVX-LABEL: combine_test3:
1394 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1396 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1397 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1401 define <4 x float> @combine_test4(<4 x float> %a, <4 x float> %b) {
1402 ; SSE-LABEL: combine_test4:
1404 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1405 ; SSE-NEXT: movapd %xmm1, %xmm0
1408 ; AVX-LABEL: combine_test4:
1410 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1412 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1413 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1417 define <4 x float> @combine_test5(<4 x float> %a, <4 x float> %b) {
1418 ; SSE2-LABEL: combine_test5:
1420 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1421 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1424 ; SSSE3-LABEL: combine_test5:
1426 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1427 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1430 ; SSE41-LABEL: combine_test5:
1432 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1435 ; AVX-LABEL: combine_test5:
1437 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1439 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1440 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1444 define <4 x i32> @combine_test6(<4 x i32> %a, <4 x i32> %b) {
1445 ; SSE-LABEL: combine_test6:
1447 ; SSE-NEXT: movaps %xmm1, %xmm0
1450 ; AVX-LABEL: combine_test6:
1452 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1454 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1455 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1459 define <4 x i32> @combine_test7(<4 x i32> %a, <4 x i32> %b) {
1460 ; SSE2-LABEL: combine_test7:
1462 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1463 ; SSE2-NEXT: movaps %xmm1, %xmm0
1466 ; SSSE3-LABEL: combine_test7:
1468 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1469 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1472 ; SSE41-LABEL: combine_test7:
1474 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1477 ; AVX1-LABEL: combine_test7:
1479 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1482 ; AVX2-LABEL: combine_test7:
1484 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1486 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1487 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1491 define <4 x i32> @combine_test8(<4 x i32> %a, <4 x i32> %b) {
1492 ; SSE-LABEL: combine_test8:
1494 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1497 ; AVX-LABEL: combine_test8:
1499 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1501 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1502 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1506 define <4 x i32> @combine_test9(<4 x i32> %a, <4 x i32> %b) {
1507 ; SSE-LABEL: combine_test9:
1509 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1510 ; SSE-NEXT: movdqa %xmm1, %xmm0
1513 ; AVX-LABEL: combine_test9:
1515 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1517 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1518 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1522 define <4 x i32> @combine_test10(<4 x i32> %a, <4 x i32> %b) {
1523 ; SSE2-LABEL: combine_test10:
1525 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1526 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1529 ; SSSE3-LABEL: combine_test10:
1531 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1532 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1535 ; SSE41-LABEL: combine_test10:
1537 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1540 ; AVX1-LABEL: combine_test10:
1542 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1545 ; AVX2-LABEL: combine_test10:
1547 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1549 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1550 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1554 define <4 x float> @combine_test11(<4 x float> %a, <4 x float> %b) {
1555 ; ALL-LABEL: combine_test11:
1558 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1559 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1563 define <4 x float> @combine_test12(<4 x float> %a, <4 x float> %b) {
1564 ; SSE2-LABEL: combine_test12:
1566 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1567 ; SSE2-NEXT: movaps %xmm1, %xmm0
1570 ; SSSE3-LABEL: combine_test12:
1572 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1573 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1576 ; SSE41-LABEL: combine_test12:
1578 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1581 ; AVX-LABEL: combine_test12:
1583 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1585 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1586 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1590 define <4 x float> @combine_test13(<4 x float> %a, <4 x float> %b) {
1591 ; SSE-LABEL: combine_test13:
1593 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1596 ; AVX-LABEL: combine_test13:
1598 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1600 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1601 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1605 define <4 x float> @combine_test14(<4 x float> %a, <4 x float> %b) {
1606 ; SSE-LABEL: combine_test14:
1608 ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1611 ; AVX-LABEL: combine_test14:
1613 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1615 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1616 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1620 define <4 x float> @combine_test15(<4 x float> %a, <4 x float> %b) {
1621 ; SSE2-LABEL: combine_test15:
1623 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1624 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1627 ; SSSE3-LABEL: combine_test15:
1629 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1630 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1633 ; SSE41-LABEL: combine_test15:
1635 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1638 ; AVX-LABEL: combine_test15:
1640 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1642 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1643 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1647 define <4 x i32> @combine_test16(<4 x i32> %a, <4 x i32> %b) {
1648 ; ALL-LABEL: combine_test16:
1651 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1652 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1656 define <4 x i32> @combine_test17(<4 x i32> %a, <4 x i32> %b) {
1657 ; SSE2-LABEL: combine_test17:
1659 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1660 ; SSE2-NEXT: movaps %xmm1, %xmm0
1663 ; SSSE3-LABEL: combine_test17:
1665 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1666 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1669 ; SSE41-LABEL: combine_test17:
1671 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1674 ; AVX1-LABEL: combine_test17:
1676 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1679 ; AVX2-LABEL: combine_test17:
1681 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1683 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1684 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1688 define <4 x i32> @combine_test18(<4 x i32> %a, <4 x i32> %b) {
1689 ; SSE-LABEL: combine_test18:
1691 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1694 ; AVX-LABEL: combine_test18:
1696 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1698 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1699 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1703 define <4 x i32> @combine_test19(<4 x i32> %a, <4 x i32> %b) {
1704 ; SSE-LABEL: combine_test19:
1706 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1709 ; AVX-LABEL: combine_test19:
1711 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1713 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1714 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1718 define <4 x i32> @combine_test20(<4 x i32> %a, <4 x i32> %b) {
1719 ; SSE2-LABEL: combine_test20:
1721 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1722 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1725 ; SSSE3-LABEL: combine_test20:
1727 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1728 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1731 ; SSE41-LABEL: combine_test20:
1733 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1736 ; AVX1-LABEL: combine_test20:
1738 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1741 ; AVX2-LABEL: combine_test20:
1743 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1745 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1746 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1750 define <4 x i32> @combine_test21(<8 x i32> %a, <4 x i32>* %ptr) {
1751 ; SSE-LABEL: combine_test21:
1753 ; SSE-NEXT: movdqa %xmm0, %xmm2
1754 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
1755 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1756 ; SSE-NEXT: movdqa %xmm2, (%rdi)
1759 ; AVX1-LABEL: combine_test21:
1761 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
1762 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm0[0],xmm1[0]
1763 ; AVX1-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1764 ; AVX1-NEXT: vmovdqa %xmm2, (%rdi)
1765 ; AVX1-NEXT: vzeroupper
1768 ; AVX2-LABEL: combine_test21:
1770 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
1771 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm0[0],xmm1[0]
1772 ; AVX2-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1773 ; AVX2-NEXT: vmovdqa %xmm2, (%rdi)
1774 ; AVX2-NEXT: vzeroupper
1776 %1 = shufflevector <8 x i32> %a, <8 x i32> %a, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1777 %2 = shufflevector <8 x i32> %a, <8 x i32> %a, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
1778 store <4 x i32> %1, <4 x i32>* %ptr, align 16
1782 define <8 x float> @combine_test22(<2 x float>* %a, <2 x float>* %b) {
1783 ; SSE-LABEL: combine_test22:
1785 ; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
1786 ; SSE-NEXT: movhpd (%rsi), %xmm0
1789 ; AVX-LABEL: combine_test22:
1791 ; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
1792 ; AVX-NEXT: vmovhpd (%rsi), %xmm0, %xmm0
1794 ; Current AVX2 lowering of this is still awful, not adding a test case.
1795 %1 = load <2 x float>, <2 x float>* %a, align 8
1796 %2 = load <2 x float>, <2 x float>* %b, align 8
1797 %3 = shufflevector <2 x float> %1, <2 x float> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
1801 ; Check some negative cases.
1802 ; FIXME: Do any of these really make sense? Are they redundant with the above tests?
1804 define <4 x float> @combine_test1b(<4 x float> %a, <4 x float> %b) {
1805 ; SSE-LABEL: combine_test1b:
1807 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1,2,0]
1808 ; SSE-NEXT: movaps %xmm1, %xmm0
1811 ; AVX-LABEL: combine_test1b:
1813 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm1[0,1,2,0]
1815 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1816 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 0>
1820 define <4 x float> @combine_test2b(<4 x float> %a, <4 x float> %b) {
1821 ; SSE2-LABEL: combine_test2b:
1823 ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0,0]
1824 ; SSE2-NEXT: movaps %xmm1, %xmm0
1827 ; SSSE3-LABEL: combine_test2b:
1829 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
1832 ; SSE41-LABEL: combine_test2b:
1834 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
1837 ; AVX-LABEL: combine_test2b:
1839 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm1[0,0]
1841 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1842 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 0, i32 5>
1846 define <4 x float> @combine_test3b(<4 x float> %a, <4 x float> %b) {
1847 ; SSE2-LABEL: combine_test3b:
1849 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
1850 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
1853 ; SSSE3-LABEL: combine_test3b:
1855 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
1856 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
1859 ; SSE41-LABEL: combine_test3b:
1861 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
1862 ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3,2,3]
1865 ; AVX-LABEL: combine_test3b:
1867 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
1868 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,3,2,3]
1870 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 6, i32 3>
1871 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 7>
1875 define <4 x float> @combine_test4b(<4 x float> %a, <4 x float> %b) {
1876 ; SSE-LABEL: combine_test4b:
1878 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
1879 ; SSE-NEXT: movaps %xmm1, %xmm0
1882 ; AVX-LABEL: combine_test4b:
1884 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm1[1,1,2,3]
1886 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1887 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 5, i32 5, i32 2, i32 7>
1892 ; Verify that we correctly fold shuffles even when we use illegal vector types.
1894 define <4 x i8> @combine_test1c(<4 x i8>* %a, <4 x i8>* %b) {
1895 ; SSE2-LABEL: combine_test1c:
1897 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1898 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1899 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1900 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1901 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1902 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1903 ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
1906 ; SSSE3-LABEL: combine_test1c:
1908 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1909 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1910 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1911 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1912 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1913 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1914 ; SSSE3-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
1917 ; SSE41-LABEL: combine_test1c:
1919 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1920 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1921 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
1924 ; AVX1-LABEL: combine_test1c:
1926 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1927 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1928 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1931 ; AVX2-LABEL: combine_test1c:
1933 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1934 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1935 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1937 %A = load <4 x i8>, <4 x i8>* %a
1938 %B = load <4 x i8>, <4 x i8>* %b
1939 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1940 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1944 define <4 x i8> @combine_test2c(<4 x i8>* %a, <4 x i8>* %b) {
1945 ; SSE2-LABEL: combine_test2c:
1947 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1948 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1949 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1950 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1951 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1952 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1953 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1956 ; SSSE3-LABEL: combine_test2c:
1958 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1959 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1960 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1961 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1962 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1963 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1964 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1967 ; SSE41-LABEL: combine_test2c:
1969 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1970 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1971 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1974 ; AVX-LABEL: combine_test2c:
1976 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1977 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1978 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1980 %A = load <4 x i8>, <4 x i8>* %a
1981 %B = load <4 x i8>, <4 x i8>* %b
1982 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 1, i32 5>
1983 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1987 define <4 x i8> @combine_test3c(<4 x i8>* %a, <4 x i8>* %b) {
1988 ; SSE2-LABEL: combine_test3c:
1990 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1991 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1992 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1993 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1994 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1995 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1996 ; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1999 ; SSSE3-LABEL: combine_test3c:
2001 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
2002 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
2003 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
2004 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
2005 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
2006 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
2007 ; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
2010 ; SSE41-LABEL: combine_test3c:
2012 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2013 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2014 ; SSE41-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
2017 ; AVX-LABEL: combine_test3c:
2019 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2020 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2021 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2023 %A = load <4 x i8>, <4 x i8>* %a
2024 %B = load <4 x i8>, <4 x i8>* %b
2025 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2026 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2030 define <4 x i8> @combine_test4c(<4 x i8>* %a, <4 x i8>* %b) {
2031 ; SSE2-LABEL: combine_test4c:
2033 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
2034 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
2035 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
2036 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
2037 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
2038 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
2039 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
2040 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
2043 ; SSSE3-LABEL: combine_test4c:
2045 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
2046 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
2047 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
2048 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
2049 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
2050 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
2051 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
2052 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
2055 ; SSE41-LABEL: combine_test4c:
2057 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2058 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2059 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
2062 ; AVX1-LABEL: combine_test4c:
2064 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2065 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2066 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
2069 ; AVX2-LABEL: combine_test4c:
2071 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2072 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2073 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
2075 %A = load <4 x i8>, <4 x i8>* %a
2076 %B = load <4 x i8>, <4 x i8>* %b
2077 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
2078 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
2083 ; The following test cases are generated from this C++ code
2085 ;__m128 blend_01(__m128 a, __m128 b)
2088 ; s = _mm_blend_ps( s, b, 1<<0 );
2089 ; s = _mm_blend_ps( s, b, 1<<1 );
2093 ;__m128 blend_02(__m128 a, __m128 b)
2096 ; s = _mm_blend_ps( s, b, 1<<0 );
2097 ; s = _mm_blend_ps( s, b, 1<<2 );
2101 ;__m128 blend_123(__m128 a, __m128 b)
2104 ; s = _mm_blend_ps( s, b, 1<<1 );
2105 ; s = _mm_blend_ps( s, b, 1<<2 );
2106 ; s = _mm_blend_ps( s, b, 1<<3 );
2110 ; Ideally, we should collapse the following shuffles into a single one.
2112 define <4 x float> @combine_blend_01(<4 x float> %a, <4 x float> %b) {
2113 ; SSE2-LABEL: combine_blend_01:
2115 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2118 ; SSSE3-LABEL: combine_blend_01:
2120 ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2123 ; SSE41-LABEL: combine_blend_01:
2125 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2128 ; AVX-LABEL: combine_blend_01:
2130 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2132 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 undef, i32 2, i32 3>
2133 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
2134 ret <4 x float> %shuffle6
2137 define <4 x float> @combine_blend_02(<4 x float> %a, <4 x float> %b) {
2138 ; SSE2-LABEL: combine_blend_02:
2140 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
2141 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
2142 ; SSE2-NEXT: movaps %xmm1, %xmm0
2145 ; SSSE3-LABEL: combine_blend_02:
2147 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
2148 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
2149 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2152 ; SSE41-LABEL: combine_blend_02:
2154 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
2157 ; AVX-LABEL: combine_blend_02:
2159 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
2161 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 undef, i32 3>
2162 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
2163 ret <4 x float> %shuffle6
2166 define <4 x float> @combine_blend_123(<4 x float> %a, <4 x float> %b) {
2167 ; SSE2-LABEL: combine_blend_123:
2169 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
2170 ; SSE2-NEXT: movaps %xmm1, %xmm0
2173 ; SSSE3-LABEL: combine_blend_123:
2175 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
2176 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2179 ; SSE41-LABEL: combine_blend_123:
2181 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
2184 ; AVX-LABEL: combine_blend_123:
2186 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
2188 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
2189 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
2190 %shuffle12 = shufflevector <4 x float> %shuffle6, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
2191 ret <4 x float> %shuffle12
2194 define <4 x i32> @combine_test_movhl_1(<4 x i32> %a, <4 x i32> %b) {
2195 ; SSE-LABEL: combine_test_movhl_1:
2197 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2198 ; SSE-NEXT: movdqa %xmm1, %xmm0
2201 ; AVX-LABEL: combine_test_movhl_1:
2203 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2205 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 7, i32 5, i32 3>
2206 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 0, i32 3>
2210 define <4 x i32> @combine_test_movhl_2(<4 x i32> %a, <4 x i32> %b) {
2211 ; SSE-LABEL: combine_test_movhl_2:
2213 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2214 ; SSE-NEXT: movdqa %xmm1, %xmm0
2217 ; AVX-LABEL: combine_test_movhl_2:
2219 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2221 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 0, i32 3, i32 6>
2222 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 3, i32 7, i32 0, i32 2>
2226 define <4 x i32> @combine_test_movhl_3(<4 x i32> %a, <4 x i32> %b) {
2227 ; SSE-LABEL: combine_test_movhl_3:
2229 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2230 ; SSE-NEXT: movdqa %xmm1, %xmm0
2233 ; AVX-LABEL: combine_test_movhl_3:
2235 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2237 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 6, i32 3, i32 2>
2238 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 0, i32 3, i32 2>
2243 ; Verify that we fold shuffles according to rule:
2244 ; (shuffle(shuffle A, Undef, M0), B, M1) -> (shuffle A, B, M2)
2246 define <4 x float> @combine_undef_input_test1(<4 x float> %a, <4 x float> %b) {
2247 ; SSE2-LABEL: combine_undef_input_test1:
2249 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2252 ; SSSE3-LABEL: combine_undef_input_test1:
2254 ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2257 ; SSE41-LABEL: combine_undef_input_test1:
2259 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2262 ; AVX-LABEL: combine_undef_input_test1:
2264 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2266 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2267 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2271 define <4 x float> @combine_undef_input_test2(<4 x float> %a, <4 x float> %b) {
2272 ; SSE-LABEL: combine_undef_input_test2:
2274 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2277 ; AVX-LABEL: combine_undef_input_test2:
2279 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2281 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2282 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2286 define <4 x float> @combine_undef_input_test3(<4 x float> %a, <4 x float> %b) {
2287 ; SSE-LABEL: combine_undef_input_test3:
2289 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2292 ; AVX-LABEL: combine_undef_input_test3:
2294 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2296 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2297 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2301 define <4 x float> @combine_undef_input_test4(<4 x float> %a, <4 x float> %b) {
2302 ; SSE-LABEL: combine_undef_input_test4:
2304 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2305 ; SSE-NEXT: movapd %xmm1, %xmm0
2308 ; AVX-LABEL: combine_undef_input_test4:
2310 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2312 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2313 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2317 define <4 x float> @combine_undef_input_test5(<4 x float> %a, <4 x float> %b) {
2318 ; SSE2-LABEL: combine_undef_input_test5:
2320 ; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2321 ; SSE2-NEXT: movapd %xmm1, %xmm0
2324 ; SSSE3-LABEL: combine_undef_input_test5:
2326 ; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2327 ; SSSE3-NEXT: movapd %xmm1, %xmm0
2330 ; SSE41-LABEL: combine_undef_input_test5:
2332 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2335 ; AVX-LABEL: combine_undef_input_test5:
2337 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2339 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2340 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2345 ; Verify that we fold shuffles according to rule:
2346 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2348 define <4 x float> @combine_undef_input_test6(<4 x float> %a) {
2349 ; ALL-LABEL: combine_undef_input_test6:
2352 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2353 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2357 define <4 x float> @combine_undef_input_test7(<4 x float> %a) {
2358 ; SSE2-LABEL: combine_undef_input_test7:
2360 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2363 ; SSSE3-LABEL: combine_undef_input_test7:
2365 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2368 ; SSE41-LABEL: combine_undef_input_test7:
2370 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2373 ; AVX-LABEL: combine_undef_input_test7:
2375 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2377 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2378 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2382 define <4 x float> @combine_undef_input_test8(<4 x float> %a) {
2383 ; SSE2-LABEL: combine_undef_input_test8:
2385 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2388 ; SSSE3-LABEL: combine_undef_input_test8:
2390 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2393 ; SSE41-LABEL: combine_undef_input_test8:
2395 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2398 ; AVX-LABEL: combine_undef_input_test8:
2400 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2402 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2403 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2407 define <4 x float> @combine_undef_input_test9(<4 x float> %a) {
2408 ; SSE-LABEL: combine_undef_input_test9:
2410 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2413 ; AVX-LABEL: combine_undef_input_test9:
2415 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2417 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2418 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2422 define <4 x float> @combine_undef_input_test10(<4 x float> %a) {
2423 ; ALL-LABEL: combine_undef_input_test10:
2426 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2427 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2431 define <4 x float> @combine_undef_input_test11(<4 x float> %a, <4 x float> %b) {
2432 ; SSE2-LABEL: combine_undef_input_test11:
2434 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2437 ; SSSE3-LABEL: combine_undef_input_test11:
2439 ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2442 ; SSE41-LABEL: combine_undef_input_test11:
2444 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2447 ; AVX-LABEL: combine_undef_input_test11:
2449 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2451 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2452 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 6>
2456 define <4 x float> @combine_undef_input_test12(<4 x float> %a, <4 x float> %b) {
2457 ; SSE-LABEL: combine_undef_input_test12:
2459 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2462 ; AVX-LABEL: combine_undef_input_test12:
2464 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2466 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2467 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2471 define <4 x float> @combine_undef_input_test13(<4 x float> %a, <4 x float> %b) {
2472 ; SSE-LABEL: combine_undef_input_test13:
2474 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2477 ; AVX-LABEL: combine_undef_input_test13:
2479 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2481 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2482 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 5, i32 0, i32 5>
2486 define <4 x float> @combine_undef_input_test14(<4 x float> %a, <4 x float> %b) {
2487 ; SSE-LABEL: combine_undef_input_test14:
2489 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2490 ; SSE-NEXT: movapd %xmm1, %xmm0
2493 ; AVX-LABEL: combine_undef_input_test14:
2495 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2497 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2498 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2502 define <4 x float> @combine_undef_input_test15(<4 x float> %a, <4 x float> %b) {
2503 ; SSE2-LABEL: combine_undef_input_test15:
2505 ; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2506 ; SSE2-NEXT: movapd %xmm1, %xmm0
2509 ; SSSE3-LABEL: combine_undef_input_test15:
2511 ; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2512 ; SSSE3-NEXT: movapd %xmm1, %xmm0
2515 ; SSE41-LABEL: combine_undef_input_test15:
2517 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2520 ; AVX-LABEL: combine_undef_input_test15:
2522 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2524 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2525 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2530 ; Verify that shuffles are canonicalized according to rules:
2531 ; shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
2533 ; This allows to trigger the following combine rule:
2534 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2536 ; As a result, all the shuffle pairs in each function below should be
2537 ; combined into a single legal shuffle operation.
2539 define <4 x float> @combine_undef_input_test16(<4 x float> %a) {
2540 ; ALL-LABEL: combine_undef_input_test16:
2543 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2544 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
2548 define <4 x float> @combine_undef_input_test17(<4 x float> %a) {
2549 ; SSE2-LABEL: combine_undef_input_test17:
2551 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2554 ; SSSE3-LABEL: combine_undef_input_test17:
2556 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2559 ; SSE41-LABEL: combine_undef_input_test17:
2561 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2564 ; AVX-LABEL: combine_undef_input_test17:
2566 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2568 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2569 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2573 define <4 x float> @combine_undef_input_test18(<4 x float> %a) {
2574 ; SSE2-LABEL: combine_undef_input_test18:
2576 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2579 ; SSSE3-LABEL: combine_undef_input_test18:
2581 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2584 ; SSE41-LABEL: combine_undef_input_test18:
2586 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2589 ; AVX-LABEL: combine_undef_input_test18:
2591 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2593 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2594 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 0, i32 5>
2598 define <4 x float> @combine_undef_input_test19(<4 x float> %a) {
2599 ; SSE-LABEL: combine_undef_input_test19:
2601 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2604 ; AVX-LABEL: combine_undef_input_test19:
2606 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2608 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2609 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2613 define <4 x float> @combine_undef_input_test20(<4 x float> %a) {
2614 ; ALL-LABEL: combine_undef_input_test20:
2617 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2618 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2622 ; These tests are designed to test the ability to combine away unnecessary
2623 ; operations feeding into a shuffle. The AVX cases are the important ones as
2624 ; they leverage operations which cannot be done naturally on the entire vector
2625 ; and thus are decomposed into multiple smaller operations.
2627 define <8 x i32> @combine_unneeded_subvector1(<8 x i32> %a) {
2628 ; SSE-LABEL: combine_unneeded_subvector1:
2630 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2631 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,2,1,0]
2632 ; SSE-NEXT: movdqa %xmm0, %xmm1
2635 ; AVX1-LABEL: combine_unneeded_subvector1:
2637 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2638 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2639 ; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
2640 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2643 ; AVX2-LABEL: combine_unneeded_subvector1:
2645 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2646 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [7,6,5,4,7,6,5,4]
2647 ; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
2649 %b = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2650 %c = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 7, i32 6, i32 5, i32 4>
2654 define <8 x i32> @combine_unneeded_subvector2(<8 x i32> %a, <8 x i32> %b) {
2655 ; SSE-LABEL: combine_unneeded_subvector2:
2657 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2658 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[3,2,1,0]
2659 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
2662 ; AVX1-LABEL: combine_unneeded_subvector2:
2664 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2665 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2666 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2667 ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
2668 ; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2671 ; AVX2-LABEL: combine_unneeded_subvector2:
2673 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2674 ; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
2675 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2677 %c = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2678 %d = shufflevector <8 x i32> %b, <8 x i32> %c, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 15, i32 14, i32 13, i32 12>
2682 define <4 x float> @combine_insertps1(<4 x float> %a, <4 x float> %b) {
2683 ; SSE2-LABEL: combine_insertps1:
2685 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,0]
2686 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[2,3]
2687 ; SSE2-NEXT: movaps %xmm1, %xmm0
2690 ; SSSE3-LABEL: combine_insertps1:
2692 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,0]
2693 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[2,3]
2694 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2697 ; SSE41-LABEL: combine_insertps1:
2699 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
2702 ; AVX-LABEL: combine_insertps1:
2704 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
2707 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 6, i32 2, i32 4>
2708 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32> <i32 5, i32 1, i32 6, i32 3>
2712 define <4 x float> @combine_insertps2(<4 x float> %a, <4 x float> %b) {
2713 ; SSE2-LABEL: combine_insertps2:
2715 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,0]
2716 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
2717 ; SSE2-NEXT: movaps %xmm1, %xmm0
2720 ; SSSE3-LABEL: combine_insertps2:
2722 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,0]
2723 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
2724 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2727 ; SSE41-LABEL: combine_insertps2:
2729 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
2732 ; AVX-LABEL: combine_insertps2:
2734 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
2737 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 1, i32 6, i32 7>
2738 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2742 define <4 x float> @combine_insertps3(<4 x float> %a, <4 x float> %b) {
2743 ; SSE2-LABEL: combine_insertps3:
2745 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
2746 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2749 ; SSSE3-LABEL: combine_insertps3:
2751 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
2752 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2755 ; SSE41-LABEL: combine_insertps3:
2757 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
2760 ; AVX-LABEL: combine_insertps3:
2762 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
2765 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
2766 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 5, i32 3>
2770 define <4 x float> @combine_insertps4(<4 x float> %a, <4 x float> %b) {
2771 ; SSE2-LABEL: combine_insertps4:
2773 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
2774 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
2777 ; SSSE3-LABEL: combine_insertps4:
2779 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
2780 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
2783 ; SSE41-LABEL: combine_insertps4:
2785 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
2788 ; AVX-LABEL: combine_insertps4:
2790 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
2793 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
2794 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 6, i32 5>
2798 define <4 x float> @PR22377(<4 x float> %a, <4 x float> %b) {
2799 ; SSE-LABEL: PR22377:
2800 ; SSE: # BB#0: # %entry
2801 ; SSE-NEXT: movaps %xmm0, %xmm1
2802 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3,1,3]
2803 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,0,2]
2804 ; SSE-NEXT: addps %xmm0, %xmm1
2805 ; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
2808 ; AVX-LABEL: PR22377:
2809 ; AVX: # BB#0: # %entry
2810 ; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[1,3,1,3]
2811 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,0,2]
2812 ; AVX-NEXT: vaddps %xmm0, %xmm1, %xmm1
2813 ; AVX-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
2816 %s1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 1, i32 3>
2817 %s2 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
2818 %r2 = fadd <4 x float> %s1, %s2
2819 %s3 = shufflevector <4 x float> %s2, <4 x float> %r2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
2823 define <4 x float> @PR22390(<4 x float> %a, <4 x float> %b) {
2824 ; SSE2-LABEL: PR22390:
2825 ; SSE2: # BB#0: # %entry
2826 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0,1,2]
2827 ; SSE2-NEXT: movaps %xmm0, %xmm2
2828 ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
2829 ; SSE2-NEXT: addps %xmm0, %xmm2
2830 ; SSE2-NEXT: movaps %xmm2, %xmm0
2833 ; SSSE3-LABEL: PR22390:
2834 ; SSSE3: # BB#0: # %entry
2835 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0,1,2]
2836 ; SSSE3-NEXT: movaps %xmm0, %xmm2
2837 ; SSSE3-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
2838 ; SSSE3-NEXT: addps %xmm0, %xmm2
2839 ; SSSE3-NEXT: movaps %xmm2, %xmm0
2842 ; SSE41-LABEL: PR22390:
2843 ; SSE41: # BB#0: # %entry
2844 ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0,1,2]
2845 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm0[1,2,3]
2846 ; SSE41-NEXT: addps %xmm1, %xmm0
2849 ; AVX-LABEL: PR22390:
2850 ; AVX: # BB#0: # %entry
2851 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,0,1,2]
2852 ; AVX-NEXT: vblendps {{.*#+}} xmm1 = xmm1[0],xmm0[1,2,3]
2853 ; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
2856 %s1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
2857 %s2 = shufflevector <4 x float> %s1, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
2858 %r2 = fadd <4 x float> %s1, %s2
2862 define <8 x float> @PR22412(<8 x float> %a, <8 x float> %b) {
2863 ; SSE2-LABEL: PR22412:
2864 ; SSE2: # BB#0: # %entry
2865 ; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
2866 ; SSE2-NEXT: movapd %xmm2, %xmm0
2867 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm3[3,2]
2868 ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,0],xmm2[3,2]
2869 ; SSE2-NEXT: movaps %xmm3, %xmm1
2872 ; SSSE3-LABEL: PR22412:
2873 ; SSSE3: # BB#0: # %entry
2874 ; SSSE3-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
2875 ; SSSE3-NEXT: movapd %xmm2, %xmm0
2876 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm3[3,2]
2877 ; SSSE3-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,0],xmm2[3,2]
2878 ; SSSE3-NEXT: movaps %xmm3, %xmm1
2881 ; SSE41-LABEL: PR22412:
2882 ; SSE41: # BB#0: # %entry
2883 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm2[1]
2884 ; SSE41-NEXT: movapd %xmm0, %xmm1
2885 ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm3[3,2]
2886 ; SSE41-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,0],xmm0[3,2]
2887 ; SSE41-NEXT: movaps %xmm1, %xmm0
2888 ; SSE41-NEXT: movaps %xmm3, %xmm1
2891 ; AVX1-LABEL: PR22412:
2892 ; AVX1: # BB#0: # %entry
2893 ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
2894 ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
2895 ; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,0],ymm1[3,2],ymm0[5,4],ymm1[7,6]
2898 ; AVX2-LABEL: PR22412:
2899 ; AVX2: # BB#0: # %entry
2900 ; AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
2901 ; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [1,0,7,6,5,4,3,2]
2902 ; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
2905 %s1 = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 1, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
2906 %s2 = shufflevector <8 x float> %s1, <8 x float> undef, <8 x i32> <i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2>