1 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
2 ; RUN: llc < %s -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
3 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
5 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
7 ; Verify that the DAG combiner correctly folds bitwise operations across
8 ; shuffles, nested shuffles with undef, pairs of nested shuffles, and other
9 ; basic and always-safe patterns. Also test that the DAG combiner will combine
10 ; target-specific shuffle instructions where reasonable.
12 target triple = "x86_64-unknown-unknown"
14 declare <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32>, i8)
15 declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8)
16 declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8)
18 define <4 x i32> @combine_pshufd1(<4 x i32> %a) {
19 ; ALL-LABEL: combine_pshufd1:
20 ; ALL: # BB#0: # %entry
23 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
24 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 27)
28 define <4 x i32> @combine_pshufd2(<4 x i32> %a) {
29 ; ALL-LABEL: combine_pshufd2:
30 ; ALL: # BB#0: # %entry
33 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
34 %b.cast = bitcast <4 x i32> %b to <8 x i16>
35 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 -28)
36 %c.cast = bitcast <8 x i16> %c to <4 x i32>
37 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
41 define <4 x i32> @combine_pshufd3(<4 x i32> %a) {
42 ; ALL-LABEL: combine_pshufd3:
43 ; ALL: # BB#0: # %entry
46 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
47 %b.cast = bitcast <4 x i32> %b to <8 x i16>
48 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 -28)
49 %c.cast = bitcast <8 x i16> %c to <4 x i32>
50 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
54 define <4 x i32> @combine_pshufd4(<4 x i32> %a) {
55 ; SSE-LABEL: combine_pshufd4:
56 ; SSE: # BB#0: # %entry
57 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
60 ; AVX-LABEL: combine_pshufd4:
61 ; AVX: # BB#0: # %entry
62 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
65 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -31)
66 %b.cast = bitcast <4 x i32> %b to <8 x i16>
67 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 27)
68 %c.cast = bitcast <8 x i16> %c to <4 x i32>
69 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -31)
73 define <4 x i32> @combine_pshufd5(<4 x i32> %a) {
74 ; SSE-LABEL: combine_pshufd5:
75 ; SSE: # BB#0: # %entry
76 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
79 ; AVX-LABEL: combine_pshufd5:
80 ; AVX: # BB#0: # %entry
81 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
84 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -76)
85 %b.cast = bitcast <4 x i32> %b to <8 x i16>
86 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 27)
87 %c.cast = bitcast <8 x i16> %c to <4 x i32>
88 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -76)
92 define <4 x i32> @combine_pshufd6(<4 x i32> %a) {
93 ; SSE-LABEL: combine_pshufd6:
94 ; SSE: # BB#0: # %entry
95 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
98 ; AVX-LABEL: combine_pshufd6:
99 ; AVX: # BB#0: # %entry
100 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
103 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 0)
104 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 8)
108 define <8 x i16> @combine_pshuflw1(<8 x i16> %a) {
109 ; ALL-LABEL: combine_pshuflw1:
110 ; ALL: # BB#0: # %entry
113 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
114 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
118 define <8 x i16> @combine_pshuflw2(<8 x i16> %a) {
119 ; ALL-LABEL: combine_pshuflw2:
120 ; ALL: # BB#0: # %entry
123 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
124 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 -28)
125 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
129 define <8 x i16> @combine_pshuflw3(<8 x i16> %a) {
130 ; SSE-LABEL: combine_pshuflw3:
131 ; SSE: # BB#0: # %entry
132 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
135 ; AVX-LABEL: combine_pshuflw3:
136 ; AVX: # BB#0: # %entry
137 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
140 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
141 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 27)
142 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
146 define <8 x i16> @combine_pshufhw1(<8 x i16> %a) {
147 ; SSE-LABEL: combine_pshufhw1:
148 ; SSE: # BB#0: # %entry
149 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
152 ; AVX-LABEL: combine_pshufhw1:
153 ; AVX: # BB#0: # %entry
154 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
157 %b = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27)
158 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
159 %d = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %c, i8 27)
163 define <4 x i32> @combine_bitwise_ops_test1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
164 ; SSE-LABEL: combine_bitwise_ops_test1:
166 ; SSE-NEXT: pand %xmm1, %xmm0
167 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
170 ; AVX-LABEL: combine_bitwise_ops_test1:
172 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
173 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
175 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
176 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
177 %and = and <4 x i32> %shuf1, %shuf2
181 define <4 x i32> @combine_bitwise_ops_test2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
182 ; SSE-LABEL: combine_bitwise_ops_test2:
184 ; SSE-NEXT: por %xmm1, %xmm0
185 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
188 ; AVX-LABEL: combine_bitwise_ops_test2:
190 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
191 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
193 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
194 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
195 %or = or <4 x i32> %shuf1, %shuf2
199 define <4 x i32> @combine_bitwise_ops_test3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
200 ; SSE-LABEL: combine_bitwise_ops_test3:
202 ; SSE-NEXT: pxor %xmm1, %xmm0
203 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
206 ; AVX-LABEL: combine_bitwise_ops_test3:
208 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
209 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
211 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
212 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
213 %xor = xor <4 x i32> %shuf1, %shuf2
217 define <4 x i32> @combine_bitwise_ops_test4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
218 ; SSE-LABEL: combine_bitwise_ops_test4:
220 ; SSE-NEXT: pand %xmm1, %xmm0
221 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
224 ; AVX-LABEL: combine_bitwise_ops_test4:
226 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
227 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
229 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
230 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
231 %and = and <4 x i32> %shuf1, %shuf2
235 define <4 x i32> @combine_bitwise_ops_test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
236 ; SSE-LABEL: combine_bitwise_ops_test5:
238 ; SSE-NEXT: por %xmm1, %xmm0
239 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
242 ; AVX-LABEL: combine_bitwise_ops_test5:
244 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
245 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
247 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
248 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
249 %or = or <4 x i32> %shuf1, %shuf2
253 define <4 x i32> @combine_bitwise_ops_test6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
254 ; SSE-LABEL: combine_bitwise_ops_test6:
256 ; SSE-NEXT: pxor %xmm1, %xmm0
257 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
260 ; AVX-LABEL: combine_bitwise_ops_test6:
262 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
263 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
265 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
266 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
267 %xor = xor <4 x i32> %shuf1, %shuf2
272 ; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles
273 ; are not performing a swizzle operations.
275 define <4 x i32> @combine_bitwise_ops_test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
276 ; SSE2-LABEL: combine_bitwise_ops_test1b:
278 ; SSE2-NEXT: andps %xmm1, %xmm0
279 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
280 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
283 ; SSSE3-LABEL: combine_bitwise_ops_test1b:
285 ; SSSE3-NEXT: andps %xmm1, %xmm0
286 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
287 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
290 ; SSE41-LABEL: combine_bitwise_ops_test1b:
292 ; SSE41-NEXT: pand %xmm1, %xmm0
293 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
296 ; AVX1-LABEL: combine_bitwise_ops_test1b:
298 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
299 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
302 ; AVX2-LABEL: combine_bitwise_ops_test1b:
304 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
305 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
307 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
308 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
309 %and = and <4 x i32> %shuf1, %shuf2
313 define <4 x i32> @combine_bitwise_ops_test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
314 ; SSE2-LABEL: combine_bitwise_ops_test2b:
316 ; SSE2-NEXT: orps %xmm1, %xmm0
317 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
318 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
321 ; SSSE3-LABEL: combine_bitwise_ops_test2b:
323 ; SSSE3-NEXT: orps %xmm1, %xmm0
324 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
325 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
328 ; SSE41-LABEL: combine_bitwise_ops_test2b:
330 ; SSE41-NEXT: por %xmm1, %xmm0
331 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
334 ; AVX1-LABEL: combine_bitwise_ops_test2b:
336 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
337 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
340 ; AVX2-LABEL: combine_bitwise_ops_test2b:
342 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
343 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
345 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
346 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
347 %or = or <4 x i32> %shuf1, %shuf2
351 define <4 x i32> @combine_bitwise_ops_test3b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
352 ; SSE2-LABEL: combine_bitwise_ops_test3b:
354 ; SSE2-NEXT: xorps %xmm1, %xmm0
355 ; SSE2-NEXT: xorps %xmm1, %xmm1
356 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
357 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
360 ; SSSE3-LABEL: combine_bitwise_ops_test3b:
362 ; SSSE3-NEXT: xorps %xmm1, %xmm0
363 ; SSSE3-NEXT: xorps %xmm1, %xmm1
364 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
365 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
368 ; SSE41-LABEL: combine_bitwise_ops_test3b:
370 ; SSE41-NEXT: pxor %xmm1, %xmm0
371 ; SSE41-NEXT: pxor %xmm1, %xmm1
372 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
375 ; AVX1-LABEL: combine_bitwise_ops_test3b:
377 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
378 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
379 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
382 ; AVX2-LABEL: combine_bitwise_ops_test3b:
384 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
385 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
386 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
388 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
389 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
390 %xor = xor <4 x i32> %shuf1, %shuf2
394 define <4 x i32> @combine_bitwise_ops_test4b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
395 ; SSE2-LABEL: combine_bitwise_ops_test4b:
397 ; SSE2-NEXT: andps %xmm1, %xmm0
398 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
399 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
400 ; SSE2-NEXT: movaps %xmm2, %xmm0
403 ; SSSE3-LABEL: combine_bitwise_ops_test4b:
405 ; SSSE3-NEXT: andps %xmm1, %xmm0
406 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
407 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
408 ; SSSE3-NEXT: movaps %xmm2, %xmm0
411 ; SSE41-LABEL: combine_bitwise_ops_test4b:
413 ; SSE41-NEXT: pand %xmm1, %xmm0
414 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
417 ; AVX1-LABEL: combine_bitwise_ops_test4b:
419 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
420 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
423 ; AVX2-LABEL: combine_bitwise_ops_test4b:
425 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
426 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
428 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
429 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
430 %and = and <4 x i32> %shuf1, %shuf2
434 define <4 x i32> @combine_bitwise_ops_test5b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
435 ; SSE2-LABEL: combine_bitwise_ops_test5b:
437 ; SSE2-NEXT: orps %xmm1, %xmm0
438 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
439 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
440 ; SSE2-NEXT: movaps %xmm2, %xmm0
443 ; SSSE3-LABEL: combine_bitwise_ops_test5b:
445 ; SSSE3-NEXT: orps %xmm1, %xmm0
446 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
447 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
448 ; SSSE3-NEXT: movaps %xmm2, %xmm0
451 ; SSE41-LABEL: combine_bitwise_ops_test5b:
453 ; SSE41-NEXT: por %xmm1, %xmm0
454 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
457 ; AVX1-LABEL: combine_bitwise_ops_test5b:
459 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
460 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
463 ; AVX2-LABEL: combine_bitwise_ops_test5b:
465 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
466 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
468 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
469 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
470 %or = or <4 x i32> %shuf1, %shuf2
474 define <4 x i32> @combine_bitwise_ops_test6b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
475 ; SSE2-LABEL: combine_bitwise_ops_test6b:
477 ; SSE2-NEXT: xorps %xmm1, %xmm0
478 ; SSE2-NEXT: xorps %xmm1, %xmm1
479 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
480 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
481 ; SSE2-NEXT: movaps %xmm1, %xmm0
484 ; SSSE3-LABEL: combine_bitwise_ops_test6b:
486 ; SSSE3-NEXT: xorps %xmm1, %xmm0
487 ; SSSE3-NEXT: xorps %xmm1, %xmm1
488 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
489 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
490 ; SSSE3-NEXT: movaps %xmm1, %xmm0
493 ; SSE41-LABEL: combine_bitwise_ops_test6b:
495 ; SSE41-NEXT: pxor %xmm1, %xmm0
496 ; SSE41-NEXT: pxor %xmm1, %xmm1
497 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
500 ; AVX1-LABEL: combine_bitwise_ops_test6b:
502 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
503 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
504 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
507 ; AVX2-LABEL: combine_bitwise_ops_test6b:
509 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
510 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
511 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
513 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
514 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
515 %xor = xor <4 x i32> %shuf1, %shuf2
519 define <4 x i32> @combine_bitwise_ops_test1c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
520 ; SSE-LABEL: combine_bitwise_ops_test1c:
522 ; SSE-NEXT: andps %xmm1, %xmm0
523 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
526 ; AVX-LABEL: combine_bitwise_ops_test1c:
528 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
529 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
531 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
532 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
533 %and = and <4 x i32> %shuf1, %shuf2
537 define <4 x i32> @combine_bitwise_ops_test2c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
538 ; SSE-LABEL: combine_bitwise_ops_test2c:
540 ; SSE-NEXT: orps %xmm1, %xmm0
541 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
544 ; AVX-LABEL: combine_bitwise_ops_test2c:
546 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
547 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
549 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
550 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
551 %or = or <4 x i32> %shuf1, %shuf2
555 define <4 x i32> @combine_bitwise_ops_test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
556 ; SSE-LABEL: combine_bitwise_ops_test3c:
558 ; SSE-NEXT: xorps %xmm1, %xmm0
559 ; SSE-NEXT: xorps %xmm1, %xmm1
560 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
563 ; AVX-LABEL: combine_bitwise_ops_test3c:
565 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
566 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
567 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
569 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
570 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
571 %xor = xor <4 x i32> %shuf1, %shuf2
575 define <4 x i32> @combine_bitwise_ops_test4c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
576 ; SSE-LABEL: combine_bitwise_ops_test4c:
578 ; SSE-NEXT: andps %xmm1, %xmm0
579 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
580 ; SSE-NEXT: movaps %xmm2, %xmm0
583 ; AVX-LABEL: combine_bitwise_ops_test4c:
585 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
586 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
588 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
589 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
590 %and = and <4 x i32> %shuf1, %shuf2
594 define <4 x i32> @combine_bitwise_ops_test5c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
595 ; SSE-LABEL: combine_bitwise_ops_test5c:
597 ; SSE-NEXT: orps %xmm1, %xmm0
598 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
599 ; SSE-NEXT: movaps %xmm2, %xmm0
602 ; AVX-LABEL: combine_bitwise_ops_test5c:
604 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
605 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
607 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
608 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
609 %or = or <4 x i32> %shuf1, %shuf2
613 define <4 x i32> @combine_bitwise_ops_test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
614 ; SSE-LABEL: combine_bitwise_ops_test6c:
616 ; SSE-NEXT: xorps %xmm1, %xmm0
617 ; SSE-NEXT: xorps %xmm1, %xmm1
618 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
619 ; SSE-NEXT: movaps %xmm1, %xmm0
622 ; AVX-LABEL: combine_bitwise_ops_test6c:
624 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
625 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
626 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[1,3]
628 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
629 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
630 %xor = xor <4 x i32> %shuf1, %shuf2
634 define <4 x i32> @combine_nested_undef_test1(<4 x i32> %A, <4 x i32> %B) {
635 ; SSE-LABEL: combine_nested_undef_test1:
637 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
640 ; AVX-LABEL: combine_nested_undef_test1:
642 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
644 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
645 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
649 define <4 x i32> @combine_nested_undef_test2(<4 x i32> %A, <4 x i32> %B) {
650 ; SSE-LABEL: combine_nested_undef_test2:
652 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
655 ; AVX-LABEL: combine_nested_undef_test2:
657 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
659 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
660 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
664 define <4 x i32> @combine_nested_undef_test3(<4 x i32> %A, <4 x i32> %B) {
665 ; SSE-LABEL: combine_nested_undef_test3:
667 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
670 ; AVX-LABEL: combine_nested_undef_test3:
672 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
674 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
675 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
679 define <4 x i32> @combine_nested_undef_test4(<4 x i32> %A, <4 x i32> %B) {
680 ; SSE-LABEL: combine_nested_undef_test4:
682 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
685 ; AVX1-LABEL: combine_nested_undef_test4:
687 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
690 ; AVX2-LABEL: combine_nested_undef_test4:
692 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
694 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 7, i32 1>
695 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 3>
699 define <4 x i32> @combine_nested_undef_test5(<4 x i32> %A, <4 x i32> %B) {
700 ; SSE-LABEL: combine_nested_undef_test5:
702 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
705 ; AVX-LABEL: combine_nested_undef_test5:
707 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
709 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 5, i32 5, i32 2, i32 3>
710 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 4, i32 3>
714 define <4 x i32> @combine_nested_undef_test6(<4 x i32> %A, <4 x i32> %B) {
715 ; SSE-LABEL: combine_nested_undef_test6:
717 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
720 ; AVX-LABEL: combine_nested_undef_test6:
722 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
724 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
725 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 4>
729 define <4 x i32> @combine_nested_undef_test7(<4 x i32> %A, <4 x i32> %B) {
730 ; SSE-LABEL: combine_nested_undef_test7:
732 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
735 ; AVX-LABEL: combine_nested_undef_test7:
737 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
739 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
740 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
744 define <4 x i32> @combine_nested_undef_test8(<4 x i32> %A, <4 x i32> %B) {
745 ; SSE-LABEL: combine_nested_undef_test8:
747 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
750 ; AVX-LABEL: combine_nested_undef_test8:
752 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
754 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
755 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
759 define <4 x i32> @combine_nested_undef_test9(<4 x i32> %A, <4 x i32> %B) {
760 ; SSE-LABEL: combine_nested_undef_test9:
762 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
765 ; AVX-LABEL: combine_nested_undef_test9:
767 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
769 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 2, i32 5>
770 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
774 define <4 x i32> @combine_nested_undef_test10(<4 x i32> %A, <4 x i32> %B) {
775 ; SSE-LABEL: combine_nested_undef_test10:
777 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
780 ; AVX-LABEL: combine_nested_undef_test10:
782 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
784 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 5>
785 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 4>
789 define <4 x i32> @combine_nested_undef_test11(<4 x i32> %A, <4 x i32> %B) {
790 ; SSE-LABEL: combine_nested_undef_test11:
792 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
795 ; AVX-LABEL: combine_nested_undef_test11:
797 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
799 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 2, i32 5, i32 4>
800 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 0>
804 define <4 x i32> @combine_nested_undef_test12(<4 x i32> %A, <4 x i32> %B) {
805 ; SSE-LABEL: combine_nested_undef_test12:
807 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
810 ; AVX1-LABEL: combine_nested_undef_test12:
812 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
815 ; AVX2-LABEL: combine_nested_undef_test12:
817 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
819 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 0, i32 2, i32 4>
820 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 0, i32 4>
824 ; The following pair of shuffles is folded into vector %A.
825 define <4 x i32> @combine_nested_undef_test13(<4 x i32> %A, <4 x i32> %B) {
826 ; ALL-LABEL: combine_nested_undef_test13:
829 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 4, i32 2, i32 6>
830 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 0, i32 2, i32 4>
834 ; The following pair of shuffles is folded into vector %B.
835 define <4 x i32> @combine_nested_undef_test14(<4 x i32> %A, <4 x i32> %B) {
836 ; SSE-LABEL: combine_nested_undef_test14:
838 ; SSE-NEXT: movaps %xmm1, %xmm0
841 ; AVX-LABEL: combine_nested_undef_test14:
843 ; AVX-NEXT: vmovaps %xmm1, %xmm0
845 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
846 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 4, i32 1, i32 4>
851 ; Verify that we don't optimize the following cases. We expect more than one shuffle.
853 ; FIXME: Many of these already don't make sense, and the rest should stop
854 ; making sense with th enew vector shuffle lowering. Revisit at least testing for
857 define <4 x i32> @combine_nested_undef_test15(<4 x i32> %A, <4 x i32> %B) {
858 ; SSE-LABEL: combine_nested_undef_test15:
860 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
861 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,1]
862 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
865 ; AVX-LABEL: combine_nested_undef_test15:
867 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
868 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[3,1]
869 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
871 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
872 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
876 define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
877 ; SSE2-LABEL: combine_nested_undef_test16:
879 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
880 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
881 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
884 ; SSSE3-LABEL: combine_nested_undef_test16:
886 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
887 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
888 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
891 ; SSE41-LABEL: combine_nested_undef_test16:
893 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
894 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
897 ; AVX1-LABEL: combine_nested_undef_test16:
899 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
900 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
903 ; AVX2-LABEL: combine_nested_undef_test16:
905 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
906 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
908 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
909 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
913 define <4 x i32> @combine_nested_undef_test17(<4 x i32> %A, <4 x i32> %B) {
914 ; SSE-LABEL: combine_nested_undef_test17:
916 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
917 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
918 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
921 ; AVX-LABEL: combine_nested_undef_test17:
923 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
924 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
925 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
927 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
928 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
932 define <4 x i32> @combine_nested_undef_test18(<4 x i32> %A, <4 x i32> %B) {
933 ; SSE-LABEL: combine_nested_undef_test18:
935 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
938 ; AVX-LABEL: combine_nested_undef_test18:
940 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
942 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
943 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 3>
947 define <4 x i32> @combine_nested_undef_test19(<4 x i32> %A, <4 x i32> %B) {
948 ; SSE-LABEL: combine_nested_undef_test19:
950 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
951 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
952 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
955 ; AVX-LABEL: combine_nested_undef_test19:
957 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
958 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
959 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
961 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
962 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
966 define <4 x i32> @combine_nested_undef_test20(<4 x i32> %A, <4 x i32> %B) {
967 ; SSE-LABEL: combine_nested_undef_test20:
969 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
970 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
973 ; AVX-LABEL: combine_nested_undef_test20:
975 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
976 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
978 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
979 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
983 define <4 x i32> @combine_nested_undef_test21(<4 x i32> %A, <4 x i32> %B) {
984 ; SSE-LABEL: combine_nested_undef_test21:
986 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
987 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
988 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
991 ; AVX-LABEL: combine_nested_undef_test21:
993 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
994 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
995 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,3]
997 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
998 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1003 ; Test that we correctly combine shuffles according to rule
1004 ; shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
1006 define <4 x i32> @combine_nested_undef_test22(<4 x i32> %A, <4 x i32> %B) {
1007 ; SSE-LABEL: combine_nested_undef_test22:
1009 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1012 ; AVX-LABEL: combine_nested_undef_test22:
1014 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1016 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1017 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 3>
1021 define <4 x i32> @combine_nested_undef_test23(<4 x i32> %A, <4 x i32> %B) {
1022 ; SSE-LABEL: combine_nested_undef_test23:
1024 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1027 ; AVX-LABEL: combine_nested_undef_test23:
1029 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1031 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1032 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1036 define <4 x i32> @combine_nested_undef_test24(<4 x i32> %A, <4 x i32> %B) {
1037 ; SSE-LABEL: combine_nested_undef_test24:
1039 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1042 ; AVX-LABEL: combine_nested_undef_test24:
1044 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1046 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1047 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 4>
1051 define <4 x i32> @combine_nested_undef_test25(<4 x i32> %A, <4 x i32> %B) {
1052 ; SSE-LABEL: combine_nested_undef_test25:
1054 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1057 ; AVX1-LABEL: combine_nested_undef_test25:
1059 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1062 ; AVX2-LABEL: combine_nested_undef_test25:
1064 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1066 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 5, i32 2, i32 4>
1067 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 3, i32 1>
1071 define <4 x i32> @combine_nested_undef_test26(<4 x i32> %A, <4 x i32> %B) {
1072 ; SSE-LABEL: combine_nested_undef_test26:
1074 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1077 ; AVX-LABEL: combine_nested_undef_test26:
1079 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1081 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 6, i32 7>
1082 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
1086 define <4 x i32> @combine_nested_undef_test27(<4 x i32> %A, <4 x i32> %B) {
1087 ; SSE-LABEL: combine_nested_undef_test27:
1089 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1092 ; AVX1-LABEL: combine_nested_undef_test27:
1094 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1097 ; AVX2-LABEL: combine_nested_undef_test27:
1099 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1101 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 2, i32 1, i32 5, i32 4>
1102 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
1106 define <4 x i32> @combine_nested_undef_test28(<4 x i32> %A, <4 x i32> %B) {
1107 ; SSE-LABEL: combine_nested_undef_test28:
1109 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1112 ; AVX-LABEL: combine_nested_undef_test28:
1114 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1116 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
1117 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 3, i32 2>
1121 define <4 x float> @combine_test1(<4 x float> %a, <4 x float> %b) {
1122 ; SSE2-LABEL: combine_test1:
1124 ; SSE2-NEXT: movaps %xmm1, %xmm2
1125 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1126 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1127 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,3]
1128 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1129 ; SSE2-NEXT: movaps %xmm2, %xmm0
1132 ; SSSE3-LABEL: combine_test1:
1134 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1137 ; SSE41-LABEL: combine_test1:
1139 ; SSE41-NEXT: movaps %xmm1, %xmm0
1142 ; AVX-LABEL: combine_test1:
1144 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1146 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1147 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1151 define <4 x float> @combine_test2(<4 x float> %a, <4 x float> %b) {
1152 ; SSE2-LABEL: combine_test2:
1154 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1155 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1156 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1157 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1160 ; SSSE3-LABEL: combine_test2:
1162 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1163 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1164 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1165 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1168 ; SSE41-LABEL: combine_test2:
1170 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1173 ; AVX-LABEL: combine_test2:
1175 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1177 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1178 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1182 define <4 x float> @combine_test3(<4 x float> %a, <4 x float> %b) {
1183 ; SSE-LABEL: combine_test3:
1185 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1188 ; AVX-LABEL: combine_test3:
1190 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1192 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1193 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1197 define <4 x float> @combine_test4(<4 x float> %a, <4 x float> %b) {
1198 ; SSE-LABEL: combine_test4:
1200 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1201 ; SSE-NEXT: movapd %xmm1, %xmm0
1204 ; AVX-LABEL: combine_test4:
1206 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1208 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1209 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1213 define <4 x float> @combine_test5(<4 x float> %a, <4 x float> %b) {
1214 ; SSE2-LABEL: combine_test5:
1216 ; SSE2-NEXT: movaps %xmm1, %xmm2
1217 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1218 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1219 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1220 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1221 ; SSE2-NEXT: movaps %xmm2, %xmm0
1224 ; SSSE3-LABEL: combine_test5:
1226 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1227 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1228 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1229 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1230 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1231 ; SSSE3-NEXT: movaps %xmm2, %xmm0
1234 ; SSE41-LABEL: combine_test5:
1236 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1239 ; AVX-LABEL: combine_test5:
1241 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1243 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1244 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1248 define <4 x i32> @combine_test6(<4 x i32> %a, <4 x i32> %b) {
1249 ; SSE2-LABEL: combine_test6:
1251 ; SSE2-NEXT: movaps %xmm1, %xmm2
1252 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1253 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1254 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,3]
1255 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1256 ; SSE2-NEXT: movaps %xmm2, %xmm0
1259 ; SSSE3-LABEL: combine_test6:
1261 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1264 ; SSE41-LABEL: combine_test6:
1266 ; SSE41-NEXT: movaps %xmm1, %xmm0
1269 ; AVX-LABEL: combine_test6:
1271 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1273 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1274 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1278 define <4 x i32> @combine_test7(<4 x i32> %a, <4 x i32> %b) {
1279 ; SSE2-LABEL: combine_test7:
1281 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1282 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1283 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1284 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1287 ; SSSE3-LABEL: combine_test7:
1289 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1290 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1291 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1292 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1295 ; SSE41-LABEL: combine_test7:
1297 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1300 ; AVX1-LABEL: combine_test7:
1302 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1305 ; AVX2-LABEL: combine_test7:
1307 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1309 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1310 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1314 define <4 x i32> @combine_test8(<4 x i32> %a, <4 x i32> %b) {
1315 ; SSE-LABEL: combine_test8:
1317 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1320 ; AVX-LABEL: combine_test8:
1322 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1324 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1325 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1329 define <4 x i32> @combine_test9(<4 x i32> %a, <4 x i32> %b) {
1330 ; SSE-LABEL: combine_test9:
1332 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1333 ; SSE-NEXT: movdqa %xmm1, %xmm0
1336 ; AVX-LABEL: combine_test9:
1338 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1340 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1341 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1345 define <4 x i32> @combine_test10(<4 x i32> %a, <4 x i32> %b) {
1346 ; SSE2-LABEL: combine_test10:
1348 ; SSE2-NEXT: movaps %xmm1, %xmm2
1349 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1350 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1351 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1352 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1353 ; SSE2-NEXT: movaps %xmm2, %xmm0
1356 ; SSSE3-LABEL: combine_test10:
1358 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1359 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1360 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1361 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
1362 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
1363 ; SSSE3-NEXT: movaps %xmm2, %xmm0
1366 ; SSE41-LABEL: combine_test10:
1368 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1371 ; AVX1-LABEL: combine_test10:
1373 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1376 ; AVX2-LABEL: combine_test10:
1378 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1380 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1381 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1385 define <4 x float> @combine_test11(<4 x float> %a, <4 x float> %b) {
1386 ; ALL-LABEL: combine_test11:
1389 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1390 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1394 define <4 x float> @combine_test12(<4 x float> %a, <4 x float> %b) {
1395 ; SSE2-LABEL: combine_test12:
1397 ; SSE2-NEXT: movss %xmm0, %xmm1
1398 ; SSE2-NEXT: movss %xmm0, %xmm1
1399 ; SSE2-NEXT: movaps %xmm1, %xmm0
1402 ; SSSE3-LABEL: combine_test12:
1404 ; SSSE3-NEXT: movss %xmm0, %xmm1
1405 ; SSSE3-NEXT: movss %xmm0, %xmm1
1406 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1409 ; SSE41-LABEL: combine_test12:
1411 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1414 ; AVX-LABEL: combine_test12:
1416 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1418 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1419 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1423 define <4 x float> @combine_test13(<4 x float> %a, <4 x float> %b) {
1424 ; SSE-LABEL: combine_test13:
1426 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1429 ; AVX-LABEL: combine_test13:
1431 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1433 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1434 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1438 define <4 x float> @combine_test14(<4 x float> %a, <4 x float> %b) {
1439 ; SSE-LABEL: combine_test14:
1441 ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1444 ; AVX-LABEL: combine_test14:
1446 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1448 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1449 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1453 define <4 x float> @combine_test15(<4 x float> %a, <4 x float> %b) {
1454 ; SSE2-LABEL: combine_test15:
1456 ; SSE2-NEXT: movaps %xmm0, %xmm2
1457 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1458 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1459 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1460 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1463 ; SSSE3-LABEL: combine_test15:
1465 ; SSSE3-NEXT: movaps %xmm0, %xmm2
1466 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1467 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1468 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1469 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1472 ; SSE41-LABEL: combine_test15:
1474 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1477 ; AVX-LABEL: combine_test15:
1479 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1481 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1482 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1486 define <4 x i32> @combine_test16(<4 x i32> %a, <4 x i32> %b) {
1487 ; ALL-LABEL: combine_test16:
1490 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1491 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1495 define <4 x i32> @combine_test17(<4 x i32> %a, <4 x i32> %b) {
1496 ; SSE2-LABEL: combine_test17:
1498 ; SSE2-NEXT: movss %xmm0, %xmm1
1499 ; SSE2-NEXT: movss %xmm0, %xmm1
1500 ; SSE2-NEXT: movaps %xmm1, %xmm0
1503 ; SSSE3-LABEL: combine_test17:
1505 ; SSSE3-NEXT: movss %xmm0, %xmm1
1506 ; SSSE3-NEXT: movss %xmm0, %xmm1
1507 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1510 ; SSE41-LABEL: combine_test17:
1512 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1515 ; AVX1-LABEL: combine_test17:
1517 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1520 ; AVX2-LABEL: combine_test17:
1522 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1524 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1525 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1529 define <4 x i32> @combine_test18(<4 x i32> %a, <4 x i32> %b) {
1530 ; SSE-LABEL: combine_test18:
1532 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1535 ; AVX-LABEL: combine_test18:
1537 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1539 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1540 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1544 define <4 x i32> @combine_test19(<4 x i32> %a, <4 x i32> %b) {
1545 ; SSE-LABEL: combine_test19:
1547 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1550 ; AVX-LABEL: combine_test19:
1552 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1554 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1555 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1559 define <4 x i32> @combine_test20(<4 x i32> %a, <4 x i32> %b) {
1560 ; SSE2-LABEL: combine_test20:
1562 ; SSE2-NEXT: movaps %xmm0, %xmm2
1563 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1564 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1565 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1566 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1569 ; SSSE3-LABEL: combine_test20:
1571 ; SSSE3-NEXT: movaps %xmm0, %xmm2
1572 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1573 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1574 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1575 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1578 ; SSE41-LABEL: combine_test20:
1580 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1583 ; AVX1-LABEL: combine_test20:
1585 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1588 ; AVX2-LABEL: combine_test20:
1590 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1592 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1593 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1598 ; Check some negative cases.
1599 ; FIXME: Do any of these really make sense? Are they redundant with the above tests?
1601 define <4 x float> @combine_test1b(<4 x float> %a, <4 x float> %b) {
1602 ; SSE2-LABEL: combine_test1b:
1604 ; SSE2-NEXT: movaps %xmm1, %xmm2
1605 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1606 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1607 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm2[0,0]
1608 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[2,0]
1609 ; SSE2-NEXT: movaps %xmm1, %xmm0
1612 ; SSSE3-LABEL: combine_test1b:
1614 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1615 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1616 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1617 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm2[0,0]
1618 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[2,0]
1619 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1622 ; SSE41-LABEL: combine_test1b:
1624 ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1,2,0]
1625 ; SSE41-NEXT: movaps %xmm1, %xmm0
1628 ; AVX-LABEL: combine_test1b:
1630 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm1[0,1,2,0]
1632 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1633 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 0>
1637 define <4 x float> @combine_test2b(<4 x float> %a, <4 x float> %b) {
1638 ; SSE2-LABEL: combine_test2b:
1640 ; SSE2-NEXT: movaps %xmm1, %xmm2
1641 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1642 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1643 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[1,1]
1644 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1645 ; SSE2-NEXT: movaps %xmm2, %xmm0
1648 ; SSSE3-LABEL: combine_test2b:
1650 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1651 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1652 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1653 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[1,1]
1654 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1655 ; SSSE3-NEXT: movaps %xmm2, %xmm0
1658 ; SSE41-LABEL: combine_test2b:
1660 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1661 ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[1,1]
1662 ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1665 ; AVX-LABEL: combine_test2b:
1667 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1668 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[1,1]
1669 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1671 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1672 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 0, i32 5>
1676 define <4 x float> @combine_test3b(<4 x float> %a, <4 x float> %b) {
1677 ; SSE-LABEL: combine_test3b:
1679 ; SSE-NEXT: movaps %xmm1, %xmm2
1680 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[3,0]
1681 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,2]
1682 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[3,3]
1683 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1686 ; AVX-LABEL: combine_test3b:
1688 ; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[2,0],xmm0[3,0]
1689 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,2]
1690 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[3,3]
1691 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1693 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 6, i32 3>
1694 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 7>
1698 define <4 x float> @combine_test4b(<4 x float> %a, <4 x float> %b) {
1699 ; SSE2-LABEL: combine_test4b:
1701 ; SSE2-NEXT: movaps %xmm1, %xmm2
1702 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1703 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1704 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0]
1705 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[0,2]
1706 ; SSE2-NEXT: movaps %xmm1, %xmm0
1709 ; SSSE3-LABEL: combine_test4b:
1711 ; SSSE3-NEXT: movaps %xmm1, %xmm2
1712 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
1713 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
1714 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0]
1715 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[0,2]
1716 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1719 ; SSE41-LABEL: combine_test4b:
1721 ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
1722 ; SSE41-NEXT: movaps %xmm1, %xmm0
1725 ; AVX-LABEL: combine_test4b:
1727 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm1[1,1,2,3]
1729 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1730 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 5, i32 5, i32 2, i32 7>
1735 ; Verify that we correctly fold shuffles even when we use illegal vector types.
1737 define <4 x i8> @combine_test1c(<4 x i8>* %a, <4 x i8>* %b) {
1738 ; SSE2-LABEL: combine_test1c:
1740 ; SSE2-NEXT: movd (%rdi), %xmm0
1741 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1742 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1743 ; SSE2-NEXT: movd (%rsi), %xmm1
1744 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1745 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1746 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1747 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1748 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1749 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1752 ; SSSE3-LABEL: combine_test1c:
1754 ; SSSE3-NEXT: movd (%rdi), %xmm0
1755 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1756 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1757 ; SSSE3-NEXT: movd (%rsi), %xmm1
1758 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1759 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1760 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1761 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1762 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1763 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1766 ; SSE41-LABEL: combine_test1c:
1768 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1769 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1770 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
1773 ; AVX1-LABEL: combine_test1c:
1775 ; AVX1-NEXT: vpmovzxbd (%rdi), %xmm0
1776 ; AVX1-NEXT: vpmovzxbd (%rsi), %xmm1
1777 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1780 ; AVX2-LABEL: combine_test1c:
1782 ; AVX2-NEXT: vpmovzxbd (%rdi), %xmm0
1783 ; AVX2-NEXT: vpmovzxbd (%rsi), %xmm1
1784 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1786 %A = load <4 x i8>* %a
1787 %B = load <4 x i8>* %b
1788 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1789 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1793 define <4 x i8> @combine_test2c(<4 x i8>* %a, <4 x i8>* %b) {
1794 ; SSE2-LABEL: combine_test2c:
1796 ; SSE2-NEXT: movd (%rdi), %xmm0
1797 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1798 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1799 ; SSE2-NEXT: movd (%rsi), %xmm1
1800 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1801 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1802 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1805 ; SSSE3-LABEL: combine_test2c:
1807 ; SSSE3-NEXT: movd (%rdi), %xmm0
1808 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1809 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1810 ; SSSE3-NEXT: movd (%rsi), %xmm1
1811 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1812 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1813 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1816 ; SSE41-LABEL: combine_test2c:
1818 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm0
1819 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm1
1820 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1823 ; AVX-LABEL: combine_test2c:
1825 ; AVX-NEXT: vpmovzxbd (%rdi), %xmm0
1826 ; AVX-NEXT: vpmovzxbd (%rsi), %xmm1
1827 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1829 %A = load <4 x i8>* %a
1830 %B = load <4 x i8>* %b
1831 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 1, i32 5>
1832 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1836 define <4 x i8> @combine_test3c(<4 x i8>* %a, <4 x i8>* %b) {
1837 ; SSE2-LABEL: combine_test3c:
1839 ; SSE2-NEXT: movd (%rdi), %xmm1
1840 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1841 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1842 ; SSE2-NEXT: movd (%rsi), %xmm0
1843 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1844 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1845 ; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1848 ; SSSE3-LABEL: combine_test3c:
1850 ; SSSE3-NEXT: movd (%rdi), %xmm1
1851 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1852 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1853 ; SSSE3-NEXT: movd (%rsi), %xmm0
1854 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1855 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1856 ; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1859 ; SSE41-LABEL: combine_test3c:
1861 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1862 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1863 ; SSE41-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1866 ; AVX-LABEL: combine_test3c:
1868 ; AVX-NEXT: vpmovzxbd (%rdi), %xmm0
1869 ; AVX-NEXT: vpmovzxbd (%rsi), %xmm1
1870 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1872 %A = load <4 x i8>* %a
1873 %B = load <4 x i8>* %b
1874 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1875 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1879 define <4 x i8> @combine_test4c(<4 x i8>* %a, <4 x i8>* %b) {
1880 ; SSE2-LABEL: combine_test4c:
1882 ; SSE2-NEXT: movd (%rdi), %xmm1
1883 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1884 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1885 ; SSE2-NEXT: movd (%rsi), %xmm2
1886 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
1887 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
1888 ; SSE2-NEXT: movdqa %xmm2, %xmm0
1889 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1890 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1891 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm0[2,0]
1892 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
1895 ; SSSE3-LABEL: combine_test4c:
1897 ; SSSE3-NEXT: movd (%rdi), %xmm1
1898 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1899 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1900 ; SSSE3-NEXT: movd (%rsi), %xmm2
1901 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
1902 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
1903 ; SSSE3-NEXT: movdqa %xmm2, %xmm0
1904 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1905 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
1906 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm0[2,0]
1907 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
1910 ; SSE41-LABEL: combine_test4c:
1912 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1913 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1914 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1917 ; AVX1-LABEL: combine_test4c:
1919 ; AVX1-NEXT: vpmovzxbd (%rdi), %xmm0
1920 ; AVX1-NEXT: vpmovzxbd (%rsi), %xmm1
1921 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1924 ; AVX2-LABEL: combine_test4c:
1926 ; AVX2-NEXT: vpmovzxbd (%rdi), %xmm0
1927 ; AVX2-NEXT: vpmovzxbd (%rsi), %xmm1
1928 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1930 %A = load <4 x i8>* %a
1931 %B = load <4 x i8>* %b
1932 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1933 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1938 ; The following test cases are generated from this C++ code
1940 ;__m128 blend_01(__m128 a, __m128 b)
1943 ; s = _mm_blend_ps( s, b, 1<<0 );
1944 ; s = _mm_blend_ps( s, b, 1<<1 );
1948 ;__m128 blend_02(__m128 a, __m128 b)
1951 ; s = _mm_blend_ps( s, b, 1<<0 );
1952 ; s = _mm_blend_ps( s, b, 1<<2 );
1956 ;__m128 blend_123(__m128 a, __m128 b)
1959 ; s = _mm_blend_ps( s, b, 1<<1 );
1960 ; s = _mm_blend_ps( s, b, 1<<2 );
1961 ; s = _mm_blend_ps( s, b, 1<<3 );
1965 ; Ideally, we should collapse the following shuffles into a single one.
1967 define <4 x float> @combine_blend_01(<4 x float> %a, <4 x float> %b) {
1968 ; SSE2-LABEL: combine_blend_01:
1970 ; SSE2-NEXT: movsd %xmm1, %xmm0
1971 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1972 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
1973 ; SSE2-NEXT: movaps %xmm1, %xmm0
1976 ; SSSE3-LABEL: combine_blend_01:
1978 ; SSSE3-NEXT: movsd %xmm1, %xmm0
1979 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1980 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
1981 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1984 ; SSE41-LABEL: combine_blend_01:
1986 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1989 ; AVX-LABEL: combine_blend_01:
1991 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1993 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 undef, i32 2, i32 3>
1994 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1995 ret <4 x float> %shuffle6
1998 define <4 x float> @combine_blend_02(<4 x float> %a, <4 x float> %b) {
1999 ; SSE2-LABEL: combine_blend_02:
2001 ; SSE2-NEXT: movss %xmm1, %xmm0
2002 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
2003 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2006 ; SSSE3-LABEL: combine_blend_02:
2008 ; SSSE3-NEXT: movss %xmm1, %xmm0
2009 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
2010 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2013 ; SSE41-LABEL: combine_blend_02:
2015 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
2018 ; AVX-LABEL: combine_blend_02:
2020 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
2022 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 undef, i32 3>
2023 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
2024 ret <4 x float> %shuffle6
2027 define <4 x float> @combine_blend_123(<4 x float> %a, <4 x float> %b) {
2028 ; SSE2-LABEL: combine_blend_123:
2030 ; SSE2-NEXT: movaps %xmm1, %xmm2
2031 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm0[0,0]
2032 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3]
2033 ; SSE2-NEXT: movsd %xmm2, %xmm1
2034 ; SSE2-NEXT: movaps %xmm1, %xmm0
2037 ; SSSE3-LABEL: combine_blend_123:
2039 ; SSSE3-NEXT: movaps %xmm1, %xmm2
2040 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm0[0,0]
2041 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3]
2042 ; SSSE3-NEXT: movsd %xmm2, %xmm1
2043 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2046 ; SSE41-LABEL: combine_blend_123:
2048 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
2051 ; AVX-LABEL: combine_blend_123:
2053 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
2055 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
2056 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
2057 %shuffle12 = shufflevector <4 x float> %shuffle6, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
2058 ret <4 x float> %shuffle12
2061 define <4 x i32> @combine_test_movhl_1(<4 x i32> %a, <4 x i32> %b) {
2062 ; SSE-LABEL: combine_test_movhl_1:
2064 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2065 ; SSE-NEXT: movdqa %xmm1, %xmm0
2068 ; AVX-LABEL: combine_test_movhl_1:
2070 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2072 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 7, i32 5, i32 3>
2073 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 0, i32 3>
2077 define <4 x i32> @combine_test_movhl_2(<4 x i32> %a, <4 x i32> %b) {
2078 ; SSE-LABEL: combine_test_movhl_2:
2080 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2081 ; SSE-NEXT: movdqa %xmm1, %xmm0
2084 ; AVX-LABEL: combine_test_movhl_2:
2086 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2088 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 0, i32 3, i32 6>
2089 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 3, i32 7, i32 0, i32 2>
2093 define <4 x i32> @combine_test_movhl_3(<4 x i32> %a, <4 x i32> %b) {
2094 ; SSE-LABEL: combine_test_movhl_3:
2096 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2097 ; SSE-NEXT: movdqa %xmm1, %xmm0
2100 ; AVX-LABEL: combine_test_movhl_3:
2102 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2104 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 6, i32 3, i32 2>
2105 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 0, i32 3, i32 2>
2110 ; Verify that we fold shuffles according to rule:
2111 ; (shuffle(shuffle A, Undef, M0), B, M1) -> (shuffle A, B, M2)
2113 define <4 x float> @combine_undef_input_test1(<4 x float> %a, <4 x float> %b) {
2114 ; SSE2-LABEL: combine_undef_input_test1:
2116 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
2117 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
2118 ; SSE2-NEXT: movaps %xmm1, %xmm0
2121 ; SSSE3-LABEL: combine_undef_input_test1:
2123 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
2124 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
2125 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2128 ; SSE41-LABEL: combine_undef_input_test1:
2130 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2133 ; AVX-LABEL: combine_undef_input_test1:
2135 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2137 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2138 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2142 define <4 x float> @combine_undef_input_test2(<4 x float> %a, <4 x float> %b) {
2143 ; SSE-LABEL: combine_undef_input_test2:
2145 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2148 ; AVX-LABEL: combine_undef_input_test2:
2150 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2152 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2153 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2157 define <4 x float> @combine_undef_input_test3(<4 x float> %a, <4 x float> %b) {
2158 ; SSE-LABEL: combine_undef_input_test3:
2160 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2163 ; AVX-LABEL: combine_undef_input_test3:
2165 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2167 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2168 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2172 define <4 x float> @combine_undef_input_test4(<4 x float> %a, <4 x float> %b) {
2173 ; SSE-LABEL: combine_undef_input_test4:
2175 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2176 ; SSE-NEXT: movapd %xmm1, %xmm0
2179 ; AVX-LABEL: combine_undef_input_test4:
2181 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2183 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2184 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2188 define <4 x float> @combine_undef_input_test5(<4 x float> %a, <4 x float> %b) {
2189 ; SSE2-LABEL: combine_undef_input_test5:
2191 ; SSE2-NEXT: movsd %xmm0, %xmm1
2192 ; SSE2-NEXT: movaps %xmm1, %xmm0
2195 ; SSSE3-LABEL: combine_undef_input_test5:
2197 ; SSSE3-NEXT: movsd %xmm0, %xmm1
2198 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2201 ; SSE41-LABEL: combine_undef_input_test5:
2203 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2206 ; AVX-LABEL: combine_undef_input_test5:
2208 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2210 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2211 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2216 ; Verify that we fold shuffles according to rule:
2217 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2219 define <4 x float> @combine_undef_input_test6(<4 x float> %a) {
2220 ; ALL-LABEL: combine_undef_input_test6:
2223 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2224 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2228 define <4 x float> @combine_undef_input_test7(<4 x float> %a) {
2229 ; SSE2-LABEL: combine_undef_input_test7:
2231 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2234 ; SSSE3-LABEL: combine_undef_input_test7:
2236 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2239 ; SSE41-LABEL: combine_undef_input_test7:
2241 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2244 ; AVX-LABEL: combine_undef_input_test7:
2246 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2248 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2249 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2253 define <4 x float> @combine_undef_input_test8(<4 x float> %a) {
2254 ; SSE2-LABEL: combine_undef_input_test8:
2256 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2259 ; SSSE3-LABEL: combine_undef_input_test8:
2261 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2264 ; SSE41-LABEL: combine_undef_input_test8:
2266 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2269 ; AVX-LABEL: combine_undef_input_test8:
2271 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2273 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2274 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2278 define <4 x float> @combine_undef_input_test9(<4 x float> %a) {
2279 ; SSE-LABEL: combine_undef_input_test9:
2281 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2284 ; AVX-LABEL: combine_undef_input_test9:
2286 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2288 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2289 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2293 define <4 x float> @combine_undef_input_test10(<4 x float> %a) {
2294 ; ALL-LABEL: combine_undef_input_test10:
2297 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2298 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2302 define <4 x float> @combine_undef_input_test11(<4 x float> %a, <4 x float> %b) {
2303 ; SSE2-LABEL: combine_undef_input_test11:
2305 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
2306 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
2307 ; SSE2-NEXT: movaps %xmm1, %xmm0
2310 ; SSSE3-LABEL: combine_undef_input_test11:
2312 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
2313 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
2314 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2317 ; SSE41-LABEL: combine_undef_input_test11:
2319 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2322 ; AVX-LABEL: combine_undef_input_test11:
2324 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2326 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2327 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 6>
2331 define <4 x float> @combine_undef_input_test12(<4 x float> %a, <4 x float> %b) {
2332 ; SSE-LABEL: combine_undef_input_test12:
2334 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2337 ; AVX-LABEL: combine_undef_input_test12:
2339 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2341 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2342 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2346 define <4 x float> @combine_undef_input_test13(<4 x float> %a, <4 x float> %b) {
2347 ; SSE-LABEL: combine_undef_input_test13:
2349 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2352 ; AVX-LABEL: combine_undef_input_test13:
2354 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2356 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2357 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 5, i32 0, i32 5>
2361 define <4 x float> @combine_undef_input_test14(<4 x float> %a, <4 x float> %b) {
2362 ; SSE-LABEL: combine_undef_input_test14:
2364 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2365 ; SSE-NEXT: movapd %xmm1, %xmm0
2368 ; AVX-LABEL: combine_undef_input_test14:
2370 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2372 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2373 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2377 define <4 x float> @combine_undef_input_test15(<4 x float> %a, <4 x float> %b) {
2378 ; SSE2-LABEL: combine_undef_input_test15:
2380 ; SSE2-NEXT: movsd %xmm0, %xmm1
2381 ; SSE2-NEXT: movaps %xmm1, %xmm0
2384 ; SSSE3-LABEL: combine_undef_input_test15:
2386 ; SSSE3-NEXT: movsd %xmm0, %xmm1
2387 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2390 ; SSE41-LABEL: combine_undef_input_test15:
2392 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2395 ; AVX-LABEL: combine_undef_input_test15:
2397 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2399 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2400 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2405 ; Verify that shuffles are canonicalized according to rules:
2406 ; shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
2408 ; This allows to trigger the following combine rule:
2409 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2411 ; As a result, all the shuffle pairs in each function below should be
2412 ; combined into a single legal shuffle operation.
2414 define <4 x float> @combine_undef_input_test16(<4 x float> %a) {
2415 ; ALL-LABEL: combine_undef_input_test16:
2418 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2419 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
2423 define <4 x float> @combine_undef_input_test17(<4 x float> %a) {
2424 ; SSE2-LABEL: combine_undef_input_test17:
2426 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2429 ; SSSE3-LABEL: combine_undef_input_test17:
2431 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2434 ; SSE41-LABEL: combine_undef_input_test17:
2436 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2439 ; AVX-LABEL: combine_undef_input_test17:
2441 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2443 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2444 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2448 define <4 x float> @combine_undef_input_test18(<4 x float> %a) {
2449 ; SSE2-LABEL: combine_undef_input_test18:
2451 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2454 ; SSSE3-LABEL: combine_undef_input_test18:
2456 ; SSSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2459 ; SSE41-LABEL: combine_undef_input_test18:
2461 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2464 ; AVX-LABEL: combine_undef_input_test18:
2466 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
2468 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2469 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 0, i32 5>
2473 define <4 x float> @combine_undef_input_test19(<4 x float> %a) {
2474 ; SSE-LABEL: combine_undef_input_test19:
2476 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2479 ; AVX-LABEL: combine_undef_input_test19:
2481 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2483 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2484 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2488 define <4 x float> @combine_undef_input_test20(<4 x float> %a) {
2489 ; ALL-LABEL: combine_undef_input_test20:
2492 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2493 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2497 ; These tests are designed to test the ability to combine away unnecessary
2498 ; operations feeding into a shuffle. The AVX cases are the important ones as
2499 ; they leverage operations which cannot be done naturally on the entire vector
2500 ; and thus are decomposed into multiple smaller operations.
2502 define <8 x i32> @combine_unneeded_subvector1(<8 x i32> %a) {
2503 ; SSE-LABEL: combine_unneeded_subvector1:
2505 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2506 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,2,1,0]
2507 ; SSE-NEXT: movdqa %xmm0, %xmm1
2510 ; AVX1-LABEL: combine_unneeded_subvector1:
2512 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2513 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2514 ; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
2515 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2518 ; AVX2-LABEL: combine_unneeded_subvector1:
2520 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2521 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [7,6,5,4,7,6,5,4]
2522 ; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
2524 %b = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2525 %c = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 7, i32 6, i32 5, i32 4>
2529 define <8 x i32> @combine_unneeded_subvector2(<8 x i32> %a, <8 x i32> %b) {
2530 ; SSE-LABEL: combine_unneeded_subvector2:
2532 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2533 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[3,2,1,0]
2534 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
2537 ; AVX1-LABEL: combine_unneeded_subvector2:
2539 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2540 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2541 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
2542 ; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[3,2,1,0]
2543 ; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
2544 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
2547 ; AVX2-LABEL: combine_unneeded_subvector2:
2549 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2550 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = <7,6,5,4,u,u,u,u>
2551 ; AVX2-NEXT: vpermd %ymm1, %ymm2, %ymm1
2552 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2553 ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
2555 %c = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2556 %d = shufflevector <8 x i32> %b, <8 x i32> %c, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 15, i32 14, i32 13, i32 12>
2560 define <4 x float> @combine_insertps1(<4 x float> %a, <4 x float> %b) {
2561 ; SSE41-LABEL: combine_insertps1:
2563 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
2566 ; AVX-LABEL: combine_insertps1:
2568 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
2571 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 6, i32 2, i32 4>
2572 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32> <i32 5, i32 1, i32 6, i32 3>
2576 define <4 x float> @combine_insertps2(<4 x float> %a, <4 x float> %b) {
2577 ; SSE41-LABEL: combine_insertps2:
2579 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
2582 ; AVX-LABEL: combine_insertps2:
2584 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
2587 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 1, i32 6, i32 7>
2588 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2592 define <4 x float> @combine_insertps3(<4 x float> %a, <4 x float> %b) {
2593 ; SSE41-LABEL: combine_insertps3:
2595 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
2598 ; AVX-LABEL: combine_insertps3:
2600 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
2603 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
2604 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 5, i32 3>
2608 define <4 x float> @combine_insertps4(<4 x float> %a, <4 x float> %b) {
2609 ; SSE41-LABEL: combine_insertps4:
2611 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
2614 ; AVX-LABEL: combine_insertps4:
2616 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
2619 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
2620 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 6, i32 5>