1 ; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=corei7 -mattr=-sse4.1 < %s | FileCheck %s
3 ; Verify that we don't emit packed vector shifts instructions if the
4 ; condition used by the vector select is a vector of constants.
7 define <4 x float> @test1(<4 x float> %a, <4 x float> %b) {
8 %1 = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %a, <4 x float> %b
17 define <4 x float> @test2(<4 x float> %a, <4 x float> %b) {
18 %1 = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
27 define <4 x float> @test3(<4 x float> %a, <4 x float> %b) {
28 %1 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
37 define <4 x float> @test4(<4 x float> %a, <4 x float> %b) {
38 %1 = select <4 x i1> <i1 false, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
44 ; CHECK: movaps %xmm1, %xmm0
48 define <4 x float> @test5(<4 x float> %a, <4 x float> %b) {
49 %1 = select <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
58 define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
59 %1 = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>, <8 x i16> %a, <8 x i16> %a
68 define <8 x i16> @test7(<8 x i16> %a, <8 x i16> %b) {
69 %1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
78 define <8 x i16> @test8(<8 x i16> %a, <8 x i16> %b) {
79 %1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
87 define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
88 %1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
94 ; CHECK: movaps %xmm1, %xmm0
97 define <8 x i16> @test10(<8 x i16> %a, <8 x i16> %b) {
98 %1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
101 ; CHECK-LABEL: test10
106 define <8 x i16> @test11(<8 x i16> %a, <8 x i16> %b) {
107 %1 = select <8 x i1> <i1 false, i1 true, i1 true, i1 false, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
110 ; CHECK-LABEL: test11
115 define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
116 %1 = select <8 x i1> <i1 false, i1 false, i1 undef, i1 false, i1 false, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
119 ; CHECK-LABEL: test12
124 define <8 x i16> @test13(<8 x i16> %a, <8 x i16> %b) {
125 %1 = select <8 x i1> <i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef>, <8 x i16> %a, <8 x i16> %b
128 ; CHECK-LABEL: test13
133 ; Fold (vselect (build_vector AllOnes), N1, N2) -> N1
135 define <4 x float> @test14(<4 x float> %a, <4 x float> %b) {
136 %1 = select <4 x i1> <i1 true, i1 undef, i1 true, i1 undef>, <4 x float> %a, <4 x float> %b
139 ; CHECK-LABEL: test14
145 define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
146 %1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 undef, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
149 ; CHECK-LABEL: test15
155 ; Fold (vselect (build_vector AllZeros), N1, N2) -> N2
157 define <4 x float> @test16(<4 x float> %a, <4 x float> %b) {
158 %1 = select <4 x i1> <i1 false, i1 undef, i1 false, i1 undef>, <4 x float> %a, <4 x float> %b
161 ; CHECK-LABEL: test16
167 define <8 x i16> @test17(<8 x i16> %a, <8 x i16> %b) {
168 %1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 undef, i1 undef, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
171 ; CHECK-LABEL: test17
177 define <4 x float> @test18(<4 x float> %a, <4 x float> %b) {
178 %1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
181 ; CHECK-LABEL: test18
188 define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
189 %1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x i32> %a, <4 x i32> %b
192 ; CHECK-LABEL: test19
199 define <2 x double> @test20(<2 x double> %a, <2 x double> %b) {
200 %1 = select <2 x i1> <i1 false, i1 true>, <2 x double> %a, <2 x double> %b
203 ; CHECK-LABEL: test20
210 define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
211 %1 = select <2 x i1> <i1 false, i1 true>, <2 x i64> %a, <2 x i64> %b
214 ; CHECK-LABEL: test21
221 define <4 x float> @test22(<4 x float> %a, <4 x float> %b) {
222 %1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
225 ; CHECK-LABEL: test22
232 define <4 x i32> @test23(<4 x i32> %a, <4 x i32> %b) {
233 %1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %a, <4 x i32> %b
236 ; CHECK-LABEL: test23
243 define <2 x double> @test24(<2 x double> %a, <2 x double> %b) {
244 %1 = select <2 x i1> <i1 true, i1 false>, <2 x double> %a, <2 x double> %b
247 ; CHECK-LABEL: test24
254 define <2 x i64> @test25(<2 x i64> %a, <2 x i64> %b) {
255 %1 = select <2 x i1> <i1 true, i1 false>, <2 x i64> %a, <2 x i64> %b
258 ; CHECK-LABEL: test25
265 define <4 x float> @select_of_shuffles_0(<2 x float> %a0, <2 x float> %b0, <2 x float> %a1, <2 x float> %b1) {
266 ; CHECK-LABEL: select_of_shuffles_0
267 ; CHECK-DAG: movlhps %xmm2, [[REGA:%xmm[0-9]+]]
268 ; CHECK-DAG: movlhps %xmm3, [[REGB:%xmm[0-9]+]]
269 ; CHECK: subps [[REGB]], [[REGA]]
270 %1 = shufflevector <2 x float> %a0, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
271 %2 = shufflevector <2 x float> %a1, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
272 %3 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %2, <4 x float> %1
273 %4 = shufflevector <2 x float> %b0, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
274 %5 = shufflevector <2 x float> %b1, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
275 %6 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %5, <4 x float> %4
276 %7 = fsub <4 x float> %3, %6
280 ; CHECK-LABEL: @select_illegal
284 define <16 x double> @select_illegal(<16 x double> %a, <16 x double> %b) {
285 %sel = select <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x double> %a, <16 x double> %b
286 ret <16 x double> %sel