1 ; RUN: llc -march=x86 -mcpu=generic -mattr=+sse4.2 < %s | FileCheck %s
2 ; RUN: llc -march=x86 -mcpu=atom < %s | FileCheck -check-prefix=ATOM %s
8 ; Scheduler causes produce a different instruction order
13 ; bitcast a v4i16 to v2i32
15 define void @convert(<2 x i32>* %dst, <4 x i16>* %src) nounwind {
17 %dst.addr = alloca <2 x i32>* ; <<2 x i32>**> [#uses=2]
18 %src.addr = alloca <4 x i16>* ; <<4 x i16>**> [#uses=2]
19 %i = alloca i32, align 4 ; <i32*> [#uses=6]
20 store <2 x i32>* %dst, <2 x i32>** %dst.addr
21 store <4 x i16>* %src, <4 x i16>** %src.addr
25 forcond: ; preds = %forinc, %entry
26 %tmp = load i32* %i ; <i32> [#uses=1]
27 %cmp = icmp slt i32 %tmp, 4 ; <i1> [#uses=1]
28 br i1 %cmp, label %forbody, label %afterfor
30 forbody: ; preds = %forcond
31 %tmp1 = load i32* %i ; <i32> [#uses=1]
32 %tmp2 = load <2 x i32>** %dst.addr ; <<2 x i32>*> [#uses=1]
33 %arrayidx = getelementptr <2 x i32>* %tmp2, i32 %tmp1 ; <<2 x i32>*> [#uses=1]
34 %tmp3 = load i32* %i ; <i32> [#uses=1]
35 %tmp4 = load <4 x i16>** %src.addr ; <<4 x i16>*> [#uses=1]
36 %arrayidx5 = getelementptr <4 x i16>* %tmp4, i32 %tmp3 ; <<4 x i16>*> [#uses=1]
37 %tmp6 = load <4 x i16>* %arrayidx5 ; <<4 x i16>> [#uses=1]
38 %add = add <4 x i16> %tmp6, < i16 1, i16 1, i16 1, i16 1 > ; <<4 x i16>> [#uses=1]
39 %conv = bitcast <4 x i16> %add to <2 x i32> ; <<2 x i32>> [#uses=1]
40 store <2 x i32> %conv, <2 x i32>* %arrayidx
43 forinc: ; preds = %forbody
44 %tmp7 = load i32* %i ; <i32> [#uses=1]
45 %inc = add i32 %tmp7, 1 ; <i32> [#uses=1]
46 store i32 %inc, i32* %i
49 afterfor: ; preds = %forcond