1 ; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+sse42 | FileCheck %s
3 ; Test based on pr5626 to load/store
6 %i32vec3 = type <3 x i32>
8 define void @add3i32(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) {
13 %a = load %i32vec3* %ap, align 16
14 %b = load %i32vec3* %bp, align 16
15 %x = add %i32vec3 %a, %b
16 store %i32vec3 %x, %i32vec3* %ret, align 16
21 define void @add3i32_2(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) {
29 %a = load %i32vec3* %ap, align 8
30 %b = load %i32vec3* %bp, align 8
31 %x = add %i32vec3 %a, %b
32 store %i32vec3 %x, %i32vec3* %ret, align 8
36 %i32vec7 = type <7 x i32>
38 define void @add7i32(%i32vec7* sret %ret, %i32vec7* %ap, %i32vec7* %bp) {
46 %a = load %i32vec7* %ap, align 16
47 %b = load %i32vec7* %bp, align 16
48 %x = add %i32vec7 %a, %b
49 store %i32vec7 %x, %i32vec7* %ret, align 16
54 %i32vec12 = type <12 x i32>
55 define void @add12i32(%i32vec12* sret %ret, %i32vec12* %ap, %i32vec12* %bp) {
65 %a = load %i32vec12* %ap, align 16
66 %b = load %i32vec12* %bp, align 16
67 %x = add %i32vec12 %a, %b
68 store %i32vec12 %x, %i32vec12* %ret, align 16
74 %i16vec3 = type <3 x i16>
75 define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp) nounwind {
81 %a = load %i16vec3* %ap, align 16
82 %b = load %i16vec3* %bp, align 16
83 %x = add %i16vec3 %a, %b
84 store %i16vec3 %x, %i16vec3* %ret, align 16
89 %i16vec4 = type <4 x i16>
90 define void @add4i16(%i16vec4* nocapture sret %ret, %i16vec4* %ap, %i16vec4* %bp) nounwind {
94 %a = load %i16vec4* %ap, align 16
95 %b = load %i16vec4* %bp, align 16
96 %x = add %i16vec4 %a, %b
97 store %i16vec4 %x, %i16vec4* %ret, align 16
102 %i16vec12 = type <12 x i16>
103 define void @add12i16(%i16vec12* nocapture sret %ret, %i16vec12* %ap, %i16vec12* %bp) nounwind {
110 %a = load %i16vec12* %ap, align 16
111 %b = load %i16vec12* %bp, align 16
112 %x = add %i16vec12 %a, %b
113 store %i16vec12 %x, %i16vec12* %ret, align 16
118 %i16vec18 = type <18 x i16>
119 define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18* %bp) nounwind {
129 %a = load %i16vec18* %ap, align 16
130 %b = load %i16vec18* %bp, align 16
131 %x = add %i16vec18 %a, %b
132 store %i16vec18 %x, %i16vec18* %ret, align 16
138 %i8vec3 = type <3 x i8>
139 define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) nounwind {
144 %a = load %i8vec3* %ap, align 16
145 %b = load %i8vec3* %bp, align 16
146 %x = add %i8vec3 %a, %b
147 store %i8vec3 %x, %i8vec3* %ret, align 16
152 %i8vec31 = type <31 x i8>
153 define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp) nounwind {
162 %a = load %i8vec31* %ap, align 16
163 %b = load %i8vec31* %bp, align 16
164 %x = add %i8vec31 %a, %b
165 store %i8vec31 %x, %i8vec31* %ret, align 16
171 %i8vec3pack = type { <3 x i8>, i8 }
172 define %i8vec3pack @rot() nounwind {
173 ; CHECK: movd {{-?[0-9]+}}(%rsp), {{%xmm[0-9]}}
175 %X = alloca %i8vec3pack, align 4
176 %rot = alloca %i8vec3pack, align 4
177 %result = alloca %i8vec3pack, align 4
178 %storetmp = bitcast %i8vec3pack* %X to <3 x i8>*
179 store <3 x i8> <i8 -98, i8 -98, i8 -98>, <3 x i8>* %storetmp
180 %storetmp1 = bitcast %i8vec3pack* %rot to <3 x i8>*
181 store <3 x i8> <i8 1, i8 1, i8 1>, <3 x i8>* %storetmp1
182 %tmp = load %i8vec3pack* %X
183 %extractVec = extractvalue %i8vec3pack %tmp, 0
184 %tmp2 = load %i8vec3pack* %rot
185 %extractVec3 = extractvalue %i8vec3pack %tmp2, 0
186 %shr = lshr <3 x i8> %extractVec, %extractVec3
187 %storetmp4 = bitcast %i8vec3pack* %result to <3 x i8>*
188 store <3 x i8> %shr, <3 x i8>* %storetmp4
189 %tmp5 = load %i8vec3pack* %result
190 ret %i8vec3pack %tmp5