1 ; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+sse42 | FileCheck %s
3 ; Test based on pr5626 to load/store
6 %i32vec3 = type <3 x i32>
8 define void @add3i32(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) {
13 %a = load %i32vec3* %ap, align 16
14 %b = load %i32vec3* %bp, align 16
15 %x = add %i32vec3 %a, %b
16 store %i32vec3 %x, %i32vec3* %ret, align 16
21 define void @add3i32_2(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) {
29 %a = load %i32vec3* %ap, align 8
30 %b = load %i32vec3* %bp, align 8
31 %x = add %i32vec3 %a, %b
32 store %i32vec3 %x, %i32vec3* %ret, align 8
36 %i32vec7 = type <7 x i32>
38 define void @add7i32(%i32vec7* sret %ret, %i32vec7* %ap, %i32vec7* %bp) {
46 %a = load %i32vec7* %ap, align 16
47 %b = load %i32vec7* %bp, align 16
48 %x = add %i32vec7 %a, %b
49 store %i32vec7 %x, %i32vec7* %ret, align 16
54 %i32vec12 = type <12 x i32>
55 define void @add12i32(%i32vec12* sret %ret, %i32vec12* %ap, %i32vec12* %bp) {
65 %a = load %i32vec12* %ap, align 16
66 %b = load %i32vec12* %bp, align 16
67 %x = add %i32vec12 %a, %b
68 store %i32vec12 %x, %i32vec12* %ret, align 16
74 %i16vec3 = type <3 x i16>
75 define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp) nounwind {
80 %a = load %i16vec3* %ap, align 16
81 %b = load %i16vec3* %bp, align 16
82 %x = add %i16vec3 %a, %b
83 store %i16vec3 %x, %i16vec3* %ret, align 16
88 %i16vec4 = type <4 x i16>
89 define void @add4i16(%i16vec4* nocapture sret %ret, %i16vec4* %ap, %i16vec4* %bp) nounwind {
92 %a = load %i16vec4* %ap, align 16
93 %b = load %i16vec4* %bp, align 16
94 %x = add %i16vec4 %a, %b
95 store %i16vec4 %x, %i16vec4* %ret, align 16
100 %i16vec12 = type <12 x i16>
101 define void @add12i16(%i16vec12* nocapture sret %ret, %i16vec12* %ap, %i16vec12* %bp) nounwind {
108 %a = load %i16vec12* %ap, align 16
109 %b = load %i16vec12* %bp, align 16
110 %x = add %i16vec12 %a, %b
111 store %i16vec12 %x, %i16vec12* %ret, align 16
116 %i16vec18 = type <18 x i16>
117 define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18* %bp) nounwind {
127 %a = load %i16vec18* %ap, align 16
128 %b = load %i16vec18* %bp, align 16
129 %x = add %i16vec18 %a, %b
130 store %i16vec18 %x, %i16vec18* %ret, align 16
136 %i8vec3 = type <3 x i8>
137 define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) nounwind {
142 %a = load %i8vec3* %ap, align 16
143 %b = load %i8vec3* %bp, align 16
144 %x = add %i8vec3 %a, %b
145 store %i8vec3 %x, %i8vec3* %ret, align 16
149 ; CHECK-LABEL: add31i8:
150 %i8vec31 = type <31 x i8>
151 define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp) nounwind {
160 %a = load %i8vec31* %ap, align 16
161 %b = load %i8vec31* %bp, align 16
162 %x = add %i8vec31 %a, %b
163 store %i8vec31 %x, %i8vec31* %ret, align 16
169 %i8vec3pack = type { <3 x i8>, i8 }
170 define %i8vec3pack @rot() nounwind {
171 ; CHECK: pmovzxbd {{-?[0-9]+}}(%rsp), {{%xmm[0-9]}}
173 %X = alloca %i8vec3pack, align 4
174 %rot = alloca %i8vec3pack, align 4
175 %result = alloca %i8vec3pack, align 4
176 %storetmp = bitcast %i8vec3pack* %X to <3 x i8>*
177 store <3 x i8> <i8 -98, i8 -98, i8 -98>, <3 x i8>* %storetmp
178 %storetmp1 = bitcast %i8vec3pack* %rot to <3 x i8>*
179 store <3 x i8> <i8 1, i8 1, i8 1>, <3 x i8>* %storetmp1
180 %tmp = load %i8vec3pack* %X
181 %extractVec = extractvalue %i8vec3pack %tmp, 0
182 %tmp2 = load %i8vec3pack* %rot
183 %extractVec3 = extractvalue %i8vec3pack %tmp2, 0
184 %shr = lshr <3 x i8> %extractVec, %extractVec3
185 %storetmp4 = bitcast %i8vec3pack* %result to <3 x i8>*
186 store <3 x i8> %shr, <3 x i8>* %storetmp4
187 %tmp5 = load %i8vec3pack* %result
188 ret %i8vec3pack %tmp5