1 ; RUN: llc < %s -join-physregs -mcpu=generic -mtriple=x86_64-mingw32 | FileCheck %s -check-prefix=M64
2 ; RUN: llc < %s -join-physregs -mcpu=generic -mtriple=x86_64-win32 | FileCheck %s -check-prefix=W64
3 ; RUN: llc < %s -join-physregs -mcpu=generic -mtriple=x86_64-win32-macho | FileCheck %s -check-prefix=EFI
7 ; Passing the same value in two registers creates a false interference that
8 ; only -join-physregs resolves. It could also be handled by a parallel copy.
10 define i64 @foo(i64 %n, i64 %x) nounwind {
13 %buf0 = alloca i8, i64 4096, align 1
15 ; ___chkstk must adjust %rsp.
16 ; M64: movq %rsp, %rbp
18 ; M64: callq ___chkstk
21 ; __chkstk does not adjust %rsp.
22 ; W64: movq %rsp, %rbp
25 ; W64: subq $4096, %rsp
28 ; EFI: movq %rsp, %rbp
29 ; EFI: $[[B0OFS:4096|4104]], %rsp
32 %buf1 = alloca i8, i64 %n, align 1
34 ; M64: leaq 15(%rcx), %rax
35 ; M64: andq $-16, %rax
36 ; M64: callq ___chkstk
38 ; M64: movq %rsp, %rax
40 ; W64: leaq 15(%rcx), %rax
41 ; W64: andq $-16, %rax
43 ; W64: subq %rax, %rsp
44 ; W64: movq %rsp, %rax
46 ; EFI: leaq 15(%rcx), [[R1:%r.*]]
47 ; EFI: andq $-16, [[R1]]
48 ; EFI: movq %rsp, [[R64:%r.*]]
49 ; EFI: subq [[R1]], [[R64]]
50 ; EFI: movq [[R64]], %rsp
52 %r = call i64 @bar(i64 %n, i64 %x, i64 %n, i8* %buf0, i8* %buf1) nounwind
55 ; M64: leaq -4096(%rbp), %r9
56 ; M64: movq %rax, 32(%rsp)
60 ; W64: leaq -4096(%rbp), %r9
61 ; W64: movq %rax, 32(%rsp)
65 ; EFI: leaq -[[B0OFS]](%rbp), %r9
66 ; EFI: movq [[R64]], 32(%rsp)
71 ; M64: movq %rbp, %rsp
73 ; W64: movq %rbp, %rsp
77 declare i64 @bar(i64, i64, i64, i8* nocapture, i8* nocapture) nounwind