1 ; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
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2 ; RUN: llc -mtriple=x86_64-unknown-unknown -O0 < %s | FileCheck %s -check-prefix=CHECK0
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4 %struct.interrupt_frame = type { i64, i64, i64, i64, i64 }
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6 @llvm.used = appending global [3 x i8*] [i8* bitcast (void (%struct.interrupt_frame*)* @test_isr_no_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i64)* @test_isr_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i64)* @test_isr_clobbers to i8*)], section "llvm.metadata"
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8 ; Spills rax, putting original esp at +8.
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9 ; No stack adjustment if declared with no error code
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10 define x86_intrcc void @test_isr_no_ecode(%struct.interrupt_frame* %frame) {
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11 ; CHECK-LABEL: test_isr_no_ecode:
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13 ; CHECK: movq 24(%rsp), %rax
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16 ; CHECK0-LABEL: test_isr_no_ecode:
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17 ; CHECK0: pushq %rax
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18 ; CHECK0: leaq 8(%rsp), %rax
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19 ; CHECK0: movq 16(%rax), %rax
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22 %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2
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23 %flags = load i64, i64* %pflags, align 4
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24 call void asm sideeffect "", "r"(i64 %flags)
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28 ; Spills rax and rcx, putting original rsp at +16. Stack is adjusted up another 8 bytes
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29 ; before return, popping the error code.
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30 define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* %frame, i64 %ecode) {
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31 ; CHECK-LABEL: test_isr_ecode
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34 ; CHECK: movq 16(%rsp), %rax
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35 ; CHECK: movq 40(%rsp), %rcx
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38 ; CHECK: addq $8, %rsp
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40 ; CHECK0-LABEL: test_isr_ecode
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41 ; CHECK0: pushq %rax
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42 ; CHECK0: pushq %rcx
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43 ; CHECK0: movq 16(%rsp), %rax
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44 ; CHECK0: leaq 24(%rsp), %rcx
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45 ; CHECK0: movq 16(%rcx), %rcx
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48 ; CHECK0: addq $8, %rsp
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50 %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2
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51 %flags = load i64, i64* %pflags, align 4
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52 call void asm sideeffect "", "r,r"(i64 %flags, i64 %ecode)
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56 ; All clobbered registers must be saved
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57 define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* %frame, i64 %ecode) {
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58 call void asm sideeffect "", "~{rax},~{rbx},~{rbp},~{r11},~{xmm0}"()
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59 ; CHECK-LABEL: test_isr_clobbers
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60 ; CHECK-SSE-NEXT: pushq %rax
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61 ; CHECK-SSE-NEXT; pushq %r11
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62 ; CHECK-SSE-NEXT: pushq %rbp
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63 ; CHECK-SSE-NEXT: pushq %rbx
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64 ; CHECK-SSE-NEXT: movaps %xmm0
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65 ; CHECK-SSE-NEXT: movaps %xmm0
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66 ; CHECK-SSE-NEXT: popq %rbx
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67 ; CHECK-SSE-NEXT: popq %rbp
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68 ; CHECK-SSE-NEXT: popq %r11
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69 ; CHECK-SSE-NEXT: popq %rax
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70 ; CHECK-SSE-NEXT: addq $8, %rsp
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71 ; CHECK-SSE-NEXT: iretq
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72 ; CHECK0-LABEL: test_isr_clobbers
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73 ; CHECK0-SSE-NEXT: pushq %rax
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74 ; CHECK0-SSE-NEXT; pushq %r11
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75 ; CHECK0-SSE-NEXT: pushq %rbp
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76 ; CHECK0-SSE-NEXT: pushq %rbx
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77 ; CHECK0-SSE-NEXT: movaps %xmm0
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78 ; CHECK0-SSE-NEXT: movaps %xmm0
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79 ; CHECK0-SSE-NEXT: popq %rbx
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80 ; CHECK0-SSE-NEXT: popq %rbp
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81 ; CHECK0-SSE-NEXT: popq %r11
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82 ; CHECK0-SSE-NEXT: popq %rax
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83 ; CHECK0-SSE-NEXT: addq $8, %rsp
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84 ; CHECK0-SSE-NEXT: iretq
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