1 ; RUN: opt < %s -msan -msan-check-access-address=0 -S | FileCheck %s
2 ; RUN: opt < %s -msan -msan-check-access-address=0 -msan-track-origins=1 -S | FileCheck -check-prefix=CHECK-ORIGINS %s
3 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
5 ; Check the presence of __msan_init
6 ; CHECK: @llvm.global_ctors {{.*}} @__msan_init
8 ; Check the presence and the linkage type of __msan_track_origins
9 ; CHECK: @__msan_track_origins = weak_odr constant i32 0
12 ; Check instrumentation of stores
14 define void @Store(i32* nocapture %p, i32 %x) nounwind uwtable {
16 store i32 %x, i32* %p, align 4
21 ; CHECK: load {{.*}} @__msan_param_tls
25 ; CHECK-ORIGINS: @Store
26 ; CHECK-ORIGINS: load {{.*}} @__msan_param_tls
27 ; CHECK-ORIGINS: store
29 ; CHECK-ORIGINS: br i1
30 ; CHECK-ORIGINS: <label>
31 ; CHECK-ORIGINS: store
32 ; CHECK-ORIGINS: br label
33 ; CHECK-ORIGINS: <label>
34 ; CHECK-ORIGINS: store
35 ; CHECK-ORIGINS: ret void
38 ; Check instrumentation of aligned stores
39 ; Shadow store has the same alignment as the original store; origin store
40 ; does not specify explicit alignment.
42 define void @AlignedStore(i32* nocapture %p, i32 %x) nounwind uwtable {
44 store i32 %x, i32* %p, align 32
48 ; CHECK: @AlignedStore
49 ; CHECK: load {{.*}} @__msan_param_tls
50 ; CHECK: store {{.*}} align 32
51 ; CHECK: store {{.*}} align 32
53 ; CHECK-ORIGINS: @AlignedStore
54 ; CHECK-ORIGINS: load {{.*}} @__msan_param_tls
55 ; CHECK-ORIGINS: store {{.*}} align 32
57 ; CHECK-ORIGINS: br i1
58 ; CHECK-ORIGINS: <label>
59 ; CHECK-ORIGINS: store {{.*}} align 32
60 ; CHECK-ORIGINS: br label
61 ; CHECK-ORIGINS: <label>
62 ; CHECK-ORIGINS: store {{.*}} align 32
63 ; CHECK-ORIGINS: ret void
66 ; load followed by cmp: check that we load the shadow and call __msan_warning.
67 define void @LoadAndCmp(i32* nocapture %a) nounwind uwtable {
69 %0 = load i32* %a, align 4
70 %tobool = icmp eq i32 %0, 0
71 br i1 %tobool, label %if.end, label %if.then
73 if.then: ; preds = %entry
74 tail call void (...)* @foo() nounwind
77 if.end: ; preds = %entry, %if.then
81 declare void @foo(...)
86 ; CHECK: call void @__msan_warning_noreturn()
87 ; CHECK-NEXT: call void asm sideeffect
88 ; CHECK-NEXT: unreachable
91 ; Check that we store the shadow for the retval.
92 define i32 @ReturnInt() nounwind uwtable readnone {
98 ; CHECK: store i32 0,{{.*}}__msan_retval_tls
101 ; Check that we get the shadow for the retval.
102 define void @CopyRetVal(i32* nocapture %a) nounwind uwtable {
104 %call = tail call i32 @ReturnInt() nounwind
105 store i32 %call, i32* %a, align 4
110 ; CHECK: load{{.*}}__msan_retval_tls
116 ; Check that we generate PHIs for shadow.
117 define void @FuncWithPhi(i32* nocapture %a, i32* %b, i32* nocapture %c) nounwind uwtable {
119 %tobool = icmp eq i32* %b, null
120 br i1 %tobool, label %if.else, label %if.then
122 if.then: ; preds = %entry
123 %0 = load i32* %b, align 4
126 if.else: ; preds = %entry
127 %1 = load i32* %c, align 4
130 if.end: ; preds = %if.else, %if.then
131 %t.0 = phi i32 [ %0, %if.then ], [ %1, %if.else ]
132 store i32 %t.0, i32* %a, align 4
136 ; CHECK: @FuncWithPhi
143 ; Compute shadow for "x << 10"
144 define void @ShlConst(i32* nocapture %x) nounwind uwtable {
146 %0 = load i32* %x, align 4
148 store i32 %1, i32* %x, align 4
161 ; Compute shadow for "10 << x": it should have 'sext i1'.
162 define void @ShlNonConst(i32* nocapture %x) nounwind uwtable {
164 %0 = load i32* %x, align 4
166 store i32 %1, i32* %x, align 4
170 ; CHECK: @ShlNonConst
179 define void @SExt(i32* nocapture %a, i16* nocapture %b) nounwind uwtable {
181 %0 = load i16* %b, align 2
182 %1 = sext i16 %0 to i32
183 store i32 %1, i32* %a, align 4
198 define void @MemSet(i8* nocapture %x) nounwind uwtable {
200 call void @llvm.memset.p0i8.i64(i8* %x, i8 42, i64 10, i32 1, i1 false)
204 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
207 ; CHECK: call i8* @__msan_memset
212 define void @MemCpy(i8* nocapture %x, i8* nocapture %y) nounwind uwtable {
214 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %x, i8* %y, i64 10, i32 1, i1 false)
218 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
221 ; CHECK: call i8* @__msan_memcpy
225 ; memmove is lowered to a call
226 define void @MemMove(i8* nocapture %x, i8* nocapture %y) nounwind uwtable {
228 call void @llvm.memmove.p0i8.p0i8.i64(i8* %x, i8* %y, i64 10, i32 1, i1 false)
232 declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
235 ; CHECK: call i8* @__msan_memmove
239 ; Check that we propagate shadow for "select"
241 define i32 @Select(i32 %a, i32 %b, i32 %c) nounwind uwtable readnone {
243 %tobool = icmp ne i32 %c, 0
244 %cond = select i1 %tobool, i32 %a, i32 %b
254 ; Check that we propagate origin for "select" with vector condition.
255 ; Select condition is flattened to i1, which is then used to select one of the
258 define <8 x i16> @SelectVector(<8 x i16> %a, <8 x i16> %b, <8 x i1> %c) nounwind uwtable readnone {
260 %cond = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
264 ; CHECK-ORIGINS: @SelectVector
265 ; CHECK-ORIGINS: bitcast <8 x i1> {{.*}} to i8
266 ; CHECK-ORIGINS: icmp ne i8
267 ; CHECK-ORIGINS: select i1
268 ; CHECK-ORIGINS: ret <8 x i16>
271 define i8* @IntToPtr(i64 %x) nounwind uwtable readnone {
273 %0 = inttoptr i64 %x to i8*
278 ; CHECK: load i64*{{.*}}__msan_param_tls
279 ; CHECK-NEXT: inttoptr
280 ; CHECK-NEXT: store i64{{.*}}__msan_retval_tls
284 define i8* @IntToPtr_ZExt(i16 %x) nounwind uwtable readnone {
286 %0 = inttoptr i16 %x to i8*
290 ; CHECK: @IntToPtr_ZExt
292 ; CHECK-NEXT: inttoptr
296 ; Check that we insert exactly one check on udiv
297 ; (2nd arg shadow is checked, 1st arg shadow is propagated)
299 define i32 @Div(i32 %a, i32 %b) nounwind uwtable readnone {
301 %div = udiv i32 %a, %b
307 ; CHECK: call void @__msan_warning
314 ; Check that we propagate shadow for x<0, x>=0, etc (i.e. sign bit tests)
316 define zeroext i1 @ICmpSLT(i32 %x) nounwind uwtable readnone {
317 %1 = icmp slt i32 %x, 0
323 ; CHECK-NOT: call void @__msan_warning
325 ; CHECK-NOT: call void @__msan_warning
328 define zeroext i1 @ICmpSGE(i32 %x) nounwind uwtable readnone {
329 %1 = icmp sge i32 %x, 0
335 ; CHECK-NOT: call void @__msan_warning
337 ; CHECK-NOT: call void @__msan_warning
340 define zeroext i1 @ICmpSGT(i32 %x) nounwind uwtable readnone {
341 %1 = icmp sgt i32 0, %x
347 ; CHECK-NOT: call void @__msan_warning
349 ; CHECK-NOT: call void @__msan_warning
352 define zeroext i1 @ICmpSLE(i32 %x) nounwind uwtable readnone {
353 %1 = icmp sle i32 0, %x
359 ; CHECK-NOT: call void @__msan_warning
361 ; CHECK-NOT: call void @__msan_warning
365 ; Check that loads of shadow have the same aligment as the original loads.
366 ; Check that loads of origin have the aligment of max(4, original alignment).
368 define i32 @ShadowLoadAlignmentLarge() nounwind uwtable {
369 %y = alloca i32, align 64
370 %1 = load volatile i32* %y, align 64
374 ; CHECK: @ShadowLoadAlignmentLarge
375 ; CHECK: load i32* {{.*}} align 64
376 ; CHECK: load volatile i32* {{.*}} align 64
379 define i32 @ShadowLoadAlignmentSmall() nounwind uwtable {
380 %y = alloca i32, align 2
381 %1 = load volatile i32* %y, align 2
385 ; CHECK: @ShadowLoadAlignmentSmall
386 ; CHECK: load i32* {{.*}} align 2
387 ; CHECK: load volatile i32* {{.*}} align 2
390 ; CHECK-ORIGINS: @ShadowLoadAlignmentSmall
391 ; CHECK-ORIGINS: load i32* {{.*}} align 2
392 ; CHECK-ORIGINS: load i32* {{.*}} align 4
393 ; CHECK-ORIGINS: load volatile i32* {{.*}} align 2
394 ; CHECK-ORIGINS: ret i32
397 ; Test vector manipulation instructions.
398 ; Check that the same bit manipulation is applied to the shadow values.
399 ; Check that there is a zero test of the shadow of %idx argument, where present.
401 define i32 @ExtractElement(<4 x i32> %vec, i32 %idx) {
402 %x = extractelement <4 x i32> %vec, i32 %idx
406 ; CHECK: @ExtractElement
407 ; CHECK: extractelement
408 ; CHECK: call void @__msan_warning
409 ; CHECK: extractelement
412 define <4 x i32> @InsertElement(<4 x i32> %vec, i32 %idx, i32 %x) {
413 %vec1 = insertelement <4 x i32> %vec, i32 %x, i32 %idx
417 ; CHECK: @InsertElement
418 ; CHECK: insertelement
419 ; CHECK: call void @__msan_warning
420 ; CHECK: insertelement
421 ; CHECK: ret <4 x i32>
423 define <4 x i32> @ShuffleVector(<4 x i32> %vec, <4 x i32> %vec1) {
424 %vec2 = shufflevector <4 x i32> %vec, <4 x i32> %vec1,
425 <4 x i32> <i32 0, i32 4, i32 1, i32 5>
429 ; CHECK: @ShuffleVector
430 ; CHECK: shufflevector
431 ; CHECK-NOT: call void @__msan_warning
432 ; CHECK: shufflevector
433 ; CHECK: ret <4 x i32>
436 ; Test bswap intrinsic instrumentation
437 define i32 @BSwap(i32 %x) nounwind uwtable readnone {
438 %y = tail call i32 @llvm.bswap.i32(i32 %x)
442 declare i32 @llvm.bswap.i32(i32) nounwind readnone
445 ; CHECK-NOT: call void @__msan_warning
446 ; CHECK: @llvm.bswap.i32
447 ; CHECK-NOT: call void @__msan_warning
448 ; CHECK: @llvm.bswap.i32
449 ; CHECK-NOT: call void @__msan_warning
455 define void @StoreIntrinsic(i8* %p, <4 x float> %x) nounwind uwtable {
456 call void @llvm.x86.sse.storeu.ps(i8* %p, <4 x float> %x)
460 declare void @llvm.x86.sse.storeu.ps(i8*, <4 x float>) nounwind
462 ; CHECK: @StoreIntrinsic
465 ; CHECK: store <4 x i32> {{.*}} align 1
466 ; CHECK: call void @llvm.x86.sse.storeu.ps
472 define <16 x i8> @LoadIntrinsic(i8* %p) nounwind uwtable {
473 %call = call <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %p)
477 declare <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %p) nounwind
479 ; CHECK: @LoadIntrinsic
480 ; CHECK: load <16 x i8>* {{.*}} align 1
483 ; CHECK: call <16 x i8> @llvm.x86.sse3.ldu.dq
484 ; CHECK: store <16 x i8> {{.*}} @__msan_retval_tls
485 ; CHECK: ret <16 x i8>
487 ; CHECK-ORIGINS: @LoadIntrinsic
488 ; CHECK-ORIGINS: [[ORIGIN:%[01-9a-z]+]] = load i32* {{.*}}
489 ; CHECK-ORIGINS: call <16 x i8> @llvm.x86.sse3.ldu.dq
490 ; CHECK-ORIGINS: store i32 {{.*}}[[ORIGIN]], i32* @__msan_retval_origin_tls
491 ; CHECK-ORIGINS: ret <16 x i8>
494 ; Simple NoMem intrinsic
495 ; Check that shadow is OR'ed, and origin is Select'ed
496 ; And no shadow checks!
498 define <8 x i16> @Paddsw128(<8 x i16> %a, <8 x i16> %b) nounwind uwtable {
499 %call = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a, <8 x i16> %b)
503 declare <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a, <8 x i16> %b) nounwind
506 ; CHECK-NEXT: load <8 x i16>* {{.*}} @__msan_param_tls
507 ; CHECK-NEXT: load <8 x i16>* {{.*}} @__msan_param_tls
508 ; CHECK-NEXT: = or <8 x i16>
509 ; CHECK-NEXT: call <8 x i16> @llvm.x86.sse2.padds.w
510 ; CHECK-NEXT: store <8 x i16> {{.*}} @__msan_retval_tls
511 ; CHECK-NEXT: ret <8 x i16>
513 ; CHECK-ORIGINS: @Paddsw128
514 ; CHECK-ORIGINS: load i32* {{.*}} @__msan_param_origin_tls
515 ; CHECK-ORIGINS: load i32* {{.*}} @__msan_param_origin_tls
516 ; CHECK-ORIGINS: = bitcast <8 x i16> {{.*}} to i128
517 ; CHECK-ORIGINS-NEXT: = icmp ne i128 {{.*}}, 0
518 ; CHECK-ORIGINS-NEXT: = select i1 {{.*}}, i32 {{.*}}, i32
519 ; CHECK-ORIGINS: call <8 x i16> @llvm.x86.sse2.padds.w
520 ; CHECK-ORIGINS: store i32 {{.*}} @__msan_retval_origin_tls
521 ; CHECK-ORIGINS: ret <8 x i16>
524 ; Test handling of vectors of pointers.
525 ; Check that shadow of such vector is a vector of integers.
527 define <8 x i8*> @VectorOfPointers(<8 x i8*>* %p) nounwind uwtable {
528 %x = load <8 x i8*>* %p
532 ; CHECK: @VectorOfPointers
533 ; CHECK: load <8 x i64>*
534 ; CHECK: load <8 x i8*>*
535 ; CHECK: store <8 x i64> {{.*}} @__msan_retval_tls
536 ; CHECK: ret <8 x i8*>
538 ; Test handling of va_copy.
540 declare void @llvm.va_copy(i8*, i8*) nounwind
542 define void @VACopy(i8* %p1, i8* %p2) nounwind uwtable {
543 call void @llvm.va_copy(i8* %p1, i8* %p2) nounwind
548 ; CHECK: call void @llvm.memset.p0i8.i64({{.*}}, i8 0, i64 24, i32 8, i1 false)