1 Analysing live variables ...
2 For BB 0x4c6560(L1Done) :
3 Defs: 0x4c65a8(recurse) 0x726cf8
6 For BB 0x4c63f0(L2Done) :
7 Defs: 0x4c6438(j3) 0x4d8120 0x4ddf98 0x727280(PhiCp:)
8 In: 0x4d6478(i3) 0x5ab290(j2)
10 For BB 0x5ab450(L2Body) :
11 Defs: 0x4d6398(i2) 0x4d6478(i3) 0x5ab498(wl) 0x726f20 0x726ff8 0x7271c0
12 In: 0x727388(PhiCp:) 0x727490(PhiCp:)
14 For BB 0x4d82a0(L1Header) :
15 Defs: 0x5ab290(j2) 0x5ab370(i1) 0x727388(PhiCp:) 0x727490(PhiCp:)
16 In: 0x5414e0(j) 0x727280(PhiCp:)
18 For BB 0x501700(Start) :
19 Defs: 0x501748(j1) 0x727280(PhiCp:)
23 After Backward Pass 0...
28 In: 0x4d6478(i3) 0x5ab290(j2)
31 In: 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
32 Out: 0x4d6478(i3) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
34 In: 0x5414e0(j) 0x727280(PhiCp:)
35 Out: 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
38 Out: 0x5414e0(j) 0x727280(PhiCp:)
40 After Backward Pass 1...
45 In: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2)
46 Out: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
48 In: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
49 Out: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
51 In: 0x5414e0(j) 0x727280(PhiCp:)
52 Out: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
55 Out: 0x5414e0(j) 0x727280(PhiCp:)
56 Live Variable Analysis complete!
58 ======For BB Start: Live var sets for instructions======
60 Live var sets before/after instruction nop
61 Before: 0x5414e0(j) 0x727280(PhiCp:)
62 After : 0x5414e0(j) 0x727280(PhiCp:)
64 Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L1Header)
65 Before: 0x5414e0(j) 0x727280(PhiCp:)
66 After : 0x5414e0(j) 0x727280(PhiCp:)
68 Live var sets before/after instruction add %reg(val j1) %reg(23) %reg(val PhiCp:)*
69 Before: 0x501748(j1) 0x5414e0(j)
70 After : 0x5414e0(j) 0x727280(PhiCp:)
72 Live var sets before/after instruction add %reg(23) %reg(23) %reg(val j1)*
74 After : 0x501748(j1) 0x5414e0(j)
76 ======For BB L1Header: Live var sets for instructions======
78 Live var sets before/after instruction nop
79 Before: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
80 After : 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
82 Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L2Body)
83 Before: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
84 After : 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
86 Live var sets before/after instruction add %reg(val i1) %reg(23) %reg(val PhiCp:)*
87 Before: 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1) 0x727388(PhiCp:)
88 After : 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
90 Live var sets before/after instruction add %reg(val j) %reg(23) %reg(val PhiCp:)*
91 Before: 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1)
92 After : 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1) 0x727388(PhiCp:)
94 Live var sets before/after instruction add %reg(23) %reg(23) %reg(val i1)*
95 Before: 0x5414e0(j) 0x5ab290(j2)
96 After : 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1)
98 Live var sets before/after instruction add %reg(val PhiCp:) %reg(23) %reg(val j2)*
99 Before: 0x5414e0(j) 0x727280(PhiCp:)
100 After : 0x5414e0(j) 0x5ab290(j2)
102 ======For BB L2Body: Live var sets for instructions======
104 Live var sets before/after instruction nop
105 Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
106 After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
108 Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L2Body)
109 Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
110 After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
112 Live var sets before/after instruction nop
113 Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
114 After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
116 Live var sets before/after instruction be %ccreg(val 0x726ff8) %disp(label L2Done)
117 Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:) 0x727490(PhiCp:)
118 After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
120 Live var sets before/after instruction add %reg(val i3) %reg(23) %reg(val PhiCp:)*
121 Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:)
122 After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:) 0x727490(PhiCp:)
124 Live var sets before/after instruction add %reg(val wl) %reg(23) %reg(val PhiCp:)*
125 Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726ff8
126 After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:)
128 Live var sets before/after instruction subcc %reg(val i3) %reg(val 0x7271c0) %reg(23)* %ccreg(val 0x726ff8)*
129 Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x7271c0
130 After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726ff8
132 Live var sets before/after instruction setsw 10 %reg(val 0x7271c0)*
133 Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl)
134 After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x7271c0
136 Live var sets before/after instruction add %reg(val i2) %reg(val 0x726f20) %reg(val i3)*
137 Before: 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726f20
138 After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl)
140 Live var sets before/after instruction setsw 1 %reg(val 0x726f20)*
141 Before: 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl)
142 After : 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726f20
144 Live var sets before/after instruction add %reg(val PhiCp:) %reg(23) %reg(val wl)*
145 Before: 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:)
146 After : 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl)
148 Live var sets before/after instruction add %reg(val PhiCp:) %reg(23) %reg(val i2)*
149 Before: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
150 After : 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:)
152 ======For BB L2Done: Live var sets for instructions======
154 Live var sets before/after instruction nop
155 Before: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
156 After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
158 Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L1Header)
159 Before: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
160 After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
162 Live var sets before/after instruction nop
163 Before: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
164 After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
166 Live var sets before/after instruction be %ccreg(val 0x4ddf98) %disp(label L1Done)
167 Before: 0x4c6438(j3) 0x4ddf98 0x5414e0(j) 0x727280(PhiCp:)
168 After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
170 Live var sets before/after instruction add %reg(val j3) %reg(23) %reg(val PhiCp:)*
171 Before: 0x4c6438(j3) 0x4ddf98 0x5414e0(j)
172 After : 0x4c6438(j3) 0x4ddf98 0x5414e0(j) 0x727280(PhiCp:)
174 Live var sets before/after instruction subcc %reg(val j3) %reg(val 0x4d8120) %reg(23)* %ccreg(val 0x4ddf98)*
175 Before: 0x4c6438(j3) 0x4d8120 0x5414e0(j)
176 After : 0x4c6438(j3) 0x4ddf98 0x5414e0(j)
178 Live var sets before/after instruction setsw 100 %reg(val 0x4d8120)*
179 Before: 0x4c6438(j3) 0x5414e0(j)
180 After : 0x4c6438(j3) 0x4d8120 0x5414e0(j)
182 Live var sets before/after instruction add %reg(val j2) %reg(val i3) %reg(val j3)*
183 Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2)
184 After : 0x4c6438(j3) 0x5414e0(j)
186 ======For BB L1Done: Live var sets for instructions======
188 Live var sets before/after instruction nop
192 Live var sets before/after instruction jmpl %reg(22)* 8 %reg(23) Implicit:0x4c65a8
193 Before: 0x4c65a8(recurse)
196 Live var sets before/after instruction nop
197 Before: 0x4c65a8(recurse)
198 After : 0x4c65a8(recurse)
200 Live var sets before/after instruction call %disp(label LoopTest) Implicit:0x4c6438 0x4c6438 0x4c65a8* 0x726cf8*
202 After : 0x4c65a8(recurse)