1 Analysing live variables ...
2 For BB 0x4d6510(L1Done) :
6 For BB 0x5ab408(L1Header) :
7 Defs: 0x4c6528 0x4d6350(i3) 0x4d6398(i4) 0x4ddf50 0x5ab450(i2)
8 In: 0x4d8290(i1) 0x726c68(PhiCp:)
10 For BB 0x4d8248(Start) :
11 Defs: 0x4d8290(i1) 0x726c68(PhiCp:)
12 In: 0x4e4690(j) 0x501658(i)
15 After Backward Pass 0...
20 In: 0x4d8290(i1) 0x726c68(PhiCp:)
21 Out: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
23 In: 0x4e4690(j) 0x501658(i)
24 Out: 0x4d8290(i1) 0x726c68(PhiCp:)
26 After Backward Pass 1...
31 In: 0x4d8290(i1) 0x726c68(PhiCp:)
32 Out: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
34 In: 0x4e4690(j) 0x501658(i)
35 Out: 0x4d8290(i1) 0x726c68(PhiCp:)
36 Live Variable Analysis complete!
38 ======For BB Start: Live var sets for instructions======
40 Live var sets before/after instruction nop
41 Before: 0x4d8290(i1) 0x726c68(PhiCp:)
42 After : 0x4d8290(i1) 0x726c68(PhiCp:)
44 Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L1Header)
45 Before: 0x4d8290(i1) 0x726c68(PhiCp:)
46 After : 0x4d8290(i1) 0x726c68(PhiCp:)
48 Live var sets before/after instruction add %reg(val i1) %reg(23) %reg(val PhiCp:)*
50 After : 0x4d8290(i1) 0x726c68(PhiCp:)
52 Live var sets before/after instruction add %reg(val i) %reg(val j) %reg(val i1)*
53 Before: 0x4e4690(j) 0x501658(i)
56 ======For BB L1Header: Live var sets for instructions======
58 Live var sets before/after instruction nop
59 Before: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
60 After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
62 Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L1Header)
63 Before: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
64 After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
66 Live var sets before/after instruction nop
67 Before: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
68 After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
70 Live var sets before/after instruction bg %ccreg(val 0x4ddf50) %disp(label L1Done)
71 Before: 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50 0x726c68(PhiCp:)
72 After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
74 Live var sets before/after instruction add %reg(val i4) %reg(23) %reg(val PhiCp:)*
75 Before: 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50
76 After : 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50 0x726c68(PhiCp:)
78 Live var sets before/after instruction subcc %reg(val i4) %reg(val 0x4c6528) %reg(23)* %ccreg(val 0x4ddf50)*
79 Before: 0x4c6528 0x4d6398(i4) 0x4d8290(i1)
80 After : 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50
82 Live var sets before/after instruction setsw 10 %reg(val 0x4c6528)*
83 Before: 0x4d6398(i4) 0x4d8290(i1)
84 After : 0x4c6528 0x4d6398(i4) 0x4d8290(i1)
86 Live var sets before/after instruction add %reg(val i2) %reg(val i3) %reg(val i4)*
87 Before: 0x4d6350(i3) 0x4d8290(i1) 0x5ab450(i2)
88 After : 0x4d6398(i4) 0x4d8290(i1)
90 Live var sets before/after instruction add %reg(val i1) %reg(23) %reg(val i3)*
91 Before: 0x4d8290(i1) 0x5ab450(i2)
92 After : 0x4d6350(i3) 0x4d8290(i1) 0x5ab450(i2)
94 Live var sets before/after instruction add %reg(val PhiCp:) %reg(23) %reg(val i2)*
95 Before: 0x4d8290(i1) 0x726c68(PhiCp:)
96 After : 0x4d8290(i1) 0x5ab450(i2)
98 ======For BB L1Done: Live var sets for instructions======
100 Live var sets before/after instruction nop
104 Live var sets before/after instruction jmpl %reg(22)* 8 %reg(23) Implicit:0x4d6398
107 Analysing live variables ...
108 For BB 0x5ab498(bb0) :
109 Defs: 0x4daa90 0x4f2d68 0x4f2df8 0x501768(result)
113 After Backward Pass 0...
117 Live Variable Analysis complete!
119 ======For BB bb0: Live var sets for instructions======
121 Live var sets before/after instruction nop
125 Live var sets before/after instruction jmpl %reg(22)* 8 %reg(23) Implicit:0x501768
126 Before: 0x501768(result)
129 Live var sets before/after instruction nop
130 Before: 0x501768(result)
131 After : 0x501768(result)
133 Live var sets before/after instruction call %disp(label PhiTest) Implicit:0x4f2d68 0x4f2df8 0x501768* 0x4daa90*
134 Before: 0x4f2d68 0x4f2df8
135 After : 0x501768(result)
137 Live var sets before/after instruction setsw 17 %reg(val 0x4f2df8)*
139 After : 0x4f2d68 0x4f2df8
141 Live var sets before/after instruction setsw 9 %reg(val 0x4f2d68)*