ARM assembly parsing of MRS instruction.
[oota-llvm.git] / test / MC / ARM / arm_instructions.s
1 @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s
2
3 @ CHECK: nop
4 @ CHECK: encoding: [0x00,0xf0,0x20,0xe3]
5         nop
6
7 @ CHECK: nopeq
8 @ CHECK: encoding: [0x00,0xf0,0x20,0x03]
9         nopeq
10
11 @ CHECK: trap
12 @ CHECK: encoding: [0xfe,0xde,0xff,0xe7]
13         trap
14
15 @ CHECK: bx     lr
16 @ CHECK: encoding: [0x1e,0xff,0x2f,0xe1]
17         bx lr
18
19 @ CHECK: vqdmull.s32    q8, d17, d16
20 @ CHECK: encoding: [0xa0,0x0d,0xe1,0xf2]
21         vqdmull.s32     q8, d17, d16
22
23 @ CHECK: and    r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
24         and r1,r2,r3
25
26 @ CHECK: ands   r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
27         ands r1,r2,r3
28
29 @ CHECK: eor    r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
30         eor r1,r2,r3
31
32 @ CHECK: eors   r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
33         eors r1,r2,r3
34
35 @ CHECK: sub    r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0]
36         sub r1,r2,r3
37
38 @ CHECK: subs   r1, r2, r3 @ encoding: [0x03,0x10,0x52,0xe0]
39         subs r1,r2,r3
40
41 @ CHECK: add    r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe0]
42         add r1,r2,r3
43
44 @ CHECK: adds   r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe0]
45         adds r1,r2,r3
46
47 @ CHECK: adc    r1, r2, r3 @ encoding: [0x03,0x10,0xa2,0xe0]
48         adc r1,r2,r3
49
50 @ CHECK: sbc    r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe0]
51         sbc r1,r2,r3
52
53 @ CHECK: orr    r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe1]
54         orr r1,r2,r3
55
56 @ CHECK: orrs   r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe1]
57         orrs r1,r2,r3
58
59 @ CHECK: bic    r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1]
60         bic r1,r2,r3
61
62 @ CHECK: bics   r1, r2, r3 @ encoding: [0x03,0x10,0xd2,0xe1]
63         bics r1,r2,r3
64
65 @ CHECK: mov    r1, r2 @ encoding: [0x02,0x10,0xa0,0xe1]
66         mov r1,r2
67
68 @ CHECK: mvn    r1, r2 @ encoding: [0x02,0x10,0xe0,0xe1]
69         mvn r1,r2
70
71 @ CHECK: mvns   r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1]
72         mvns r1,r2
73
74 @ CHECK: rsb    r1, r2, r3 @ encoding: [0x03,0x10,0x62,0xe0]
75         rsb r1,r2,r3
76
77 @ CHECK: rsc    r1, r2, r3 @ encoding: [0x03,0x10,0xe2,0xe0]
78         rsc r1,r2,r3
79
80 @ CHECK: bfi  r0, r0, #5, #7 @ encoding: [0x90,0x02,0xcb,0xe7]
81         bfi  r0, r0, #5, #7
82
83 @ CHECK: bkpt  #10 @ encoding: [0x7a,0x00,0x20,0xe1]
84         bkpt  #10
85
86 @ CHECK: cdp  p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee]
87         cdp  p7, #1, c1, c1, c1, #4
88 @ CHECK: cdp2  p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe]
89         cdp2  p7, #1, c1, c1, c1, #4
90
91 @ CHECK: qadd  r1, r2, r3 @ encoding: [0x52,0x10,0x03,0xe1]
92         qadd  r1, r2, r3
93
94 @ CHECK: qsub  r1, r2, r3 @ encoding: [0x52,0x10,0x23,0xe1]
95         qsub  r1, r2, r3
96
97 @ CHECK: qdadd  r1, r2, r3 @ encoding: [0x52,0x10,0x43,0xe1]
98         qdadd  r1, r2, r3
99
100 @ CHECK: qdsub  r1, r2, r3 @ encoding: [0x52,0x10,0x63,0xe1]
101         qdsub  r1, r2, r3
102
103 @ CHECK: wfe @ encoding: [0x02,0xf0,0x20,0xe3]
104         wfe
105
106 @ CHECK: wfi @ encoding: [0x03,0xf0,0x20,0xe3]
107         wfi
108
109 @ CHECK: yield @ encoding: [0x01,0xf0,0x20,0xe3]
110         yield
111
112 @ CHECK: nop @ encoding: [0x00,0xf0,0x20,0xe3]
113         nop
114
115 @ CHECK: cpsie  aif @ encoding: [0xc0,0x01,0x08,0xf1]
116         cpsie  aif
117
118 @ CHECK: cps  #15 @ encoding: [0x0f,0x00,0x02,0xf1]
119         cps  #15
120
121 @ CHECK: cpsie  if, #10 @ encoding: [0xca,0x00,0x0a,0xf1]
122         cpsie  if, #10
123
124 @ CHECK: msr  cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
125         msr  apsr, r0
126
127 @ CHECK: msr  cpsr_s, r0 @ encoding: [0x00,0xf0,0x24,0xe1]
128         msr  apsr_g, r0
129
130 @ CHECK: msr  cpsr_f, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
131         msr  apsr_nzcvq, r0
132
133 @ CHECK: msr  cpsr_fs, r0 @ encoding: [0x00,0xf0,0x2c,0xe1]
134         msr  apsr_nzcvqg, r0
135
136 @ CHECK: msr  cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
137         msr  cpsr_fc, r0
138
139 @ CHECK: msr  cpsr_c, r0 @ encoding: [0x00,0xf0,0x21,0xe1]
140         msr  cpsr_c, r0
141
142 @ CHECK: msr  cpsr_x, r0 @ encoding: [0x00,0xf0,0x22,0xe1]
143         msr  cpsr_x, r0
144
145 @ CHECK: msr  cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
146         msr  cpsr_fc, r0
147
148 @ CHECK: msr  cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
149         msr  cpsr_all, r0
150
151 @ CHECK: msr  cpsr_fsx, r0 @ encoding: [0x00,0xf0,0x2e,0xe1]
152         msr  cpsr_fsx, r0
153
154 @ CHECK: msr  spsr_fc, r0 @ encoding: [0x00,0xf0,0x69,0xe1]
155         msr  spsr_fc, r0
156
157 @ CHECK: msr  spsr_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1]
158         msr  spsr_fsxc, r0
159
160 @ CHECK: msr  cpsr_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1]
161         msr  cpsr_fsxc, r0
162
163 @ CHECK: add    r1, r2, r3, lsl r4      @ encoding: [0x13,0x14,0x82,0xe0]
164   add r1, r2, r3, lsl r4
165
166 @ CHECK: strexb  r0, r1, [r2] @ encoding: [0x91,0x0f,0xc2,0xe1]
167         strexb  r0, r1, [r2]
168
169 @ CHECK: strexh  r0, r1, [r2] @ encoding: [0x91,0x0f,0xe2,0xe1]
170         strexh  r0, r1, [r2]
171
172 @ CHECK: strex  r0, r1, [r2] @ encoding: [0x91,0x0f,0x82,0xe1]
173         strex  r0, r1, [r2]
174
175 @ CHECK: strexd  r0, r2, r3, [r1] @ encoding: [0x92,0x0f,0xa1,0xe1]
176         strexd  r0, r2, r3, [r1]
177
178 @ CHECK: ldrexb  r0, [r0] @ encoding: [0x9f,0x0f,0xd0,0xe1]
179         ldrexb  r0, [r0]
180
181 @ CHECK: ldrexh  r0, [r0] @ encoding: [0x9f,0x0f,0xf0,0xe1]
182         ldrexh  r0, [r0]
183
184 @ CHECK: ldrex  r0, [r0] @ encoding: [0x9f,0x0f,0x90,0xe1]
185         ldrex  r0, [r0]
186
187 @ CHECK: ldrexd  r0, r1, [r0] @ encoding: [0x9f,0x0f,0xb0,0xe1]
188         ldrexd  r0, r1, [r0]
189
190 @ CHECK: ssat16  r0, #7, r0 @ encoding: [0x30,0x0f,0xa6,0xe6]
191         ssat16  r0, #7, r0
192