1 //RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8.1a -mattr=neon -show-encoding < %s 2>%t | FileCheck %s --check-prefix=CHECK-V81aTHUMB
2 //RUN: FileCheck --check-prefix=CHECK-ERROR <%t %s
3 //RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.1a -mattr=neon -show-encoding < %s 2>%t | FileCheck %s --check-prefix=CHECK-V81aARM
4 //RUN: FileCheck --check-prefix=CHECK-ERROR <%t %s
6 //RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8 -mattr=neon -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8
7 //RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8 -mattr=neon -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8
11 //CHECK-V8THUMB: .text
13 vqrdmlah.i8 q0, q1, q2
14 vqrdmlah.u16 d0, d1, d2
15 vqrdmlsh.f32 q3, q4, q5
16 vqrdmlsh.f64 d3, d5, d5
18 //CHECK-ERROR: error: invalid operand for instruction
19 //CHECK-ERROR: vqrdmlah.i8 q0, q1, q2
21 //CHECK-ERROR: error: invalid operand for instruction
22 //CHECK-ERROR: vqrdmlah.u16 d0, d1, d2
24 //CHECK-ERROR: error: invalid operand for instruction
25 //CHECK-ERROR: vqrdmlsh.f32 q3, q4, q5
27 //CHECK-ERROR: error: invalid operand for instruction
28 //CHECK-ERROR: vqrdmlsh.f64 d3, d5, d5
30 //CHECK-V8: error: invalid operand for instruction
31 //CHECK-V8: vqrdmlah.i8 q0, q1, q2
33 //CHECK-V8: error: invalid operand for instruction
34 //CHECK-V8: vqrdmlah.u16 d0, d1, d2
36 //CHECK-V8: error: invalid operand for instruction
37 //CHECK-V8: vqrdmlsh.f32 q3, q4, q5
39 //CHECK-V8: error: invalid operand for instruction
40 //CHECK-V8: vqrdmlsh.f64 d3, d5, d5
43 vqrdmlah.s16 d0, d1, d2
44 //CHECK-V81aARM: vqrdmlah.s16 d0, d1, d2 @ encoding: [0x12,0x0b,0x11,0xf3]
45 //CHECK-V81aTHUMB: vqrdmlah.s16 d0, d1, d2 @ encoding: [0x11,0xff,0x12,0x0b]
46 //CHECK-V8: error: instruction requires: armv8.1a
47 //CHECK-V8: vqrdmlah.s16 d0, d1, d2
50 vqrdmlah.s32 d0, d1, d2
51 //CHECK-V81aARM: vqrdmlah.s32 d0, d1, d2 @ encoding: [0x12,0x0b,0x21,0xf3]
52 //CHECK-V81aTHUMB: vqrdmlah.s32 d0, d1, d2 @ encoding: [0x21,0xff,0x12,0x0b]
53 //CHECK-V8: error: instruction requires: armv8.1a
54 //CHECK-V8: vqrdmlah.s32 d0, d1, d2
57 vqrdmlah.s16 q0, q1, q2
58 //CHECK-V81aARM: vqrdmlah.s16 q0, q1, q2 @ encoding: [0x54,0x0b,0x12,0xf3]
59 //CHECK-V81aTHUMB: vqrdmlah.s16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0b]
60 //CHECK-V8: error: instruction requires: armv8.1a
61 //CHECK-V8: vqrdmlah.s16 q0, q1, q2
64 vqrdmlah.s32 q2, q3, q0
65 //CHECK-V81aARM: vqrdmlah.s32 q2, q3, q0 @ encoding: [0x50,0x4b,0x26,0xf3]
66 //CHECK-V81aTHUMB: vqrdmlah.s32 q2, q3, q0 @ encoding: [0x26,0xff,0x50,0x4b]
67 //CHECK-V8: error: instruction requires: armv8.1a
68 //CHECK-V8: vqrdmlah.s32 q2, q3, q0
72 vqrdmlsh.s16 d7, d6, d5
73 //CHECK-V81aARM: vqrdmlsh.s16 d7, d6, d5 @ encoding: [0x15,0x7c,0x16,0xf3]
74 //CHECK-V81aTHUMB: vqrdmlsh.s16 d7, d6, d5 @ encoding: [0x16,0xff,0x15,0x7c]
75 //CHECK-V8: error: instruction requires: armv8.1a
76 //CHECK-V8: vqrdmlsh.s16 d7, d6, d5
79 vqrdmlsh.s32 d0, d1, d2
80 //CHECK-V81aARM: vqrdmlsh.s32 d0, d1, d2 @ encoding: [0x12,0x0c,0x21,0xf3]
81 //CHECK-V81aTHUMB: vqrdmlsh.s32 d0, d1, d2 @ encoding: [0x21,0xff,0x12,0x0c]
82 //CHECK-V8: error: instruction requires: armv8.1a
83 //CHECK-V8: vqrdmlsh.s32 d0, d1, d2
86 vqrdmlsh.s16 q0, q1, q2
87 //CHECK-V81aARM: vqrdmlsh.s16 q0, q1, q2 @ encoding: [0x54,0x0c,0x12,0xf3]
88 //CHECK-V81aTHUMB: vqrdmlsh.s16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0c]
89 //CHECK-V8: error: instruction requires: armv8.1a
90 //CHECK-V8: vqrdmlsh.s16 q0, q1, q2
93 vqrdmlsh.s32 q3, q4, q5
94 //CHECK-V81aARM: vqrdmlsh.s32 q3, q4, q5 @ encoding: [0x5a,0x6c,0x28,0xf3]
95 //CHECK-V81aTHUMB: vqrdmlsh.s32 q3, q4, q5 @ encoding: [0x28,0xff,0x5a,0x6c]
96 //CHECK-V8: error: instruction requires: armv8.1a
97 //CHECK-V8: vqrdmlsh.s32 q3, q4, q5
101 vqrdmlah.i8 q0, q1, d9[7]
102 vqrdmlah.u16 d0, d1, d2[3]
103 vqrdmlsh.f32 q3, q4, d5[1]
104 vqrdmlsh.f64 d3, d5, d5[0]
106 //CHECK-ERROR: error: invalid operand for instruction
107 //CHECK-ERROR: vqrdmlah.i8 q0, q1, d9[7]
109 //CHECK-ERROR: error: invalid operand for instruction
110 //CHECK-ERROR: vqrdmlah.u16 d0, d1, d2[3]
112 //CHECK-ERROR: error: invalid operand for instruction
113 //CHECK-ERROR: vqrdmlsh.f32 q3, q4, d5[1]
115 //CHECK-ERROR: error: invalid operand for instruction
116 //CHECK-ERROR: vqrdmlsh.f64 d3, d5, d5[0]
119 vqrdmlah.s16 d0, d1, d2[0]
120 //CHECK-V81aARM: vqrdmlah.s16 d0, d1, d2[0] @ encoding: [0x42,0x0e,0x91,0xf2]
121 //CHECK-V81aTHUMB: vqrdmlah.s16 d0, d1, d2[0] @ encoding: [0x91,0xef,0x42,0x0e]
122 //CHECK-V8: error: instruction requires: armv8.1a
123 //CHECK-V8: vqrdmlah.s16 d0, d1, d2[0]
126 vqrdmlah.s32 d0, d1, d2[0]
127 //CHECK-V81aARM: vqrdmlah.s32 d0, d1, d2[0] @ encoding: [0x42,0x0e,0xa1,0xf2]
128 //CHECK-V81aTHUMB: vqrdmlah.s32 d0, d1, d2[0] @ encoding: [0xa1,0xef,0x42,0x0e]
129 //CHECK-V8: error: instruction requires: armv8.1a
130 //CHECK-V8: vqrdmlah.s32 d0, d1, d2[0]
133 vqrdmlah.s16 q0, q1, d2[0]
134 //CHECK-V81aARM: vqrdmlah.s16 q0, q1, d2[0] @ encoding: [0x42,0x0e,0x92,0xf3]
135 //CHECK-V81aTHUMB: vqrdmlah.s16 q0, q1, d2[0] @ encoding: [0x92,0xff,0x42,0x0e]
136 //CHECK-V8: error: instruction requires: armv8.1a
137 //CHECK-V8: vqrdmlah.s16 q0, q1, d2[0]
140 vqrdmlah.s32 q0, q1, d2[0]
141 //CHECK-V81aARM: vqrdmlah.s32 q0, q1, d2[0] @ encoding: [0x42,0x0e,0xa2,0xf3]
142 //CHECK-V81aTHUMB: vqrdmlah.s32 q0, q1, d2[0] @ encoding: [0xa2,0xff,0x42,0x0e]
143 //CHECK-V8: error: instruction requires: armv8.1a
144 //CHECK-V8: vqrdmlah.s32 q0, q1, d2[0]
148 vqrdmlsh.s16 d0, d1, d2[0]
149 //CHECK-V81aARM: vqrdmlsh.s16 d0, d1, d2[0] @ encoding: [0x42,0x0f,0x91,0xf2]
150 //CHECK-V81aTHUMB: vqrdmlsh.s16 d0, d1, d2[0] @ encoding: [0x91,0xef,0x42,0x0f]
151 //CHECK-V8: error: instruction requires: armv8.1a
152 //CHECK-V8: vqrdmlsh.s16 d0, d1, d2[0]
155 vqrdmlsh.s32 d0, d1, d2[0]
156 //CHECK-V81aARM: vqrdmlsh.s32 d0, d1, d2[0] @ encoding: [0x42,0x0f,0xa1,0xf2]
157 //CHECK-V81aTHUMB: vqrdmlsh.s32 d0, d1, d2[0] @ encoding: [0xa1,0xef,0x42,0x0f]
158 //CHECK-V8: error: instruction requires: armv8.1a
159 //CHECK-V8: vqrdmlsh.s32 d0, d1, d2[0]
162 vqrdmlsh.s16 q0, q1, d2[0]
163 //CHECK-V81aARM: vqrdmlsh.s16 q0, q1, d2[0] @ encoding: [0x42,0x0f,0x92,0xf3]
164 //CHECK-V81aTHUMB: vqrdmlsh.s16 q0, q1, d2[0] @ encoding: [0x92,0xff,0x42,0x0f]
165 //CHECK-V8: error: instruction requires: armv8.1a
166 //CHECK-V8: vqrdmlsh.s16 q0, q1, d2[0]
169 vqrdmlsh.s32 q0, q1, d2[0]
170 //CHECK-V81aARM: vqrdmlsh.s32 q0, q1, d2[0] @ encoding: [0x42,0x0f,0xa2,0xf3]
171 //CHECK-V81aTHUMB: vqrdmlsh.s32 q0, q1, d2[0] @ encoding: [0xa2,0xff,0x42,0x0f]
172 //CHECK-V8: error: instruction requires: armv8.1a
173 //CHECK-V8: vqrdmlsh.s32 q0, q1, d2[0]
177 //CHECK-V81aTHUMB: setpan #0 @ encoding: [0x10,0xb6]
178 //CHECK-V81aARM: setpan #0 @ encoding: [0x00,0x00,0x10,0xf1]
179 //CHECK-V8: error: instruction requires: armv8.1a
180 //CHECK-V8: setpan #0
184 //CHECK-V81aTHUMB: setpan #1 @ encoding: [0x18,0xb6]
185 //CHECK-V81aARM: setpan #1 @ encoding: [0x00,0x02,0x10,0xf1]
186 //CHECK-V8: error: instruction requires: armv8.1a
187 //CHECK-V8: setpan #1
192 //CHECK-ERROR: error: too few operands for instruction
193 //CHECK-ERROR: setpan
195 //CHECK-ERROR: error: invalid operand for instruction
196 //CHECK-ERROR: setpan #-1
198 //CHECK-ERROR: error: invalid operand for instruction
199 //CHECK-ERROR: setpan #2
204 //CHECK-THUMB-ERROR: error: instruction 'setpan' is not predicable, but condition code specified
205 //CHECK-THUMB-ERROR: setpaneq #0
206 //CHECK-THUMB-ERROR: ^