1 @ RUN: llvm-mc -triple=armv7-apple-darwin -show-encoding < %s | FileCheck %s
5 @ Check that the assembler can handle the documented syntax from the ARM ARM.
6 @ For complex constructs like shifter operands, check more thoroughly for them
7 @ once then spot check that following instructions accept the form generally.
8 @ This gives us good coverage while keeping the overall size of the test
14 @------------------------------------------------------------------------------
16 @------------------------------------------------------------------------------
23 adc r1, r2, #0xf000000
24 adc r1, r2, #0xf0000000
25 adc r1, r2, #0xf000000f
30 @ CHECK: adc r1, r2, #15 @ encoding: [0x0f,0x10,0xa2,0xe2]
31 @ CHECK: adc r1, r2, #240 @ encoding: [0xf0,0x10,0xa2,0xe2]
32 @ CHECK: adc r1, r2, #3840 @ encoding: [0x0f,0x1c,0xa2,0xe2]
33 @ CHECK: adc r1, r2, #61440 @ encoding: [0x0f,0x1a,0xa2,0xe2]
34 @ CHECK: adc r1, r2, #983040 @ encoding: [0x0f,0x18,0xa2,0xe2]
35 @ CHECK: adc r1, r2, #15728640 @ encoding: [0x0f,0x16,0xa2,0xe2]
36 @ CHECK: adc r1, r2, #251658240 @ encoding: [0x0f,0x14,0xa2,0xe2]
37 @ CHECK: adc r1, r2, #4026531840 @ encoding: [0x0f,0x12,0xa2,0xe2]
38 @ CHECK: adc r1, r2, #4026531855 @ encoding: [0xff,0x12,0xa2,0xe2]
40 @ CHECK: adcs r1, r2, #3840 @ encoding: [0x0f,0x1c,0xb2,0xe2]
41 @ CHECK: adcseq r1, r2, #3840 @ encoding: [0x0f,0x1c,0xb2,0x02]
42 @ CHECK: adceq r1, r2, #3840 @ encoding: [0x0f,0x1c,0xa2,0x02]
44 @------------------------------------------------------------------------------
46 @ ADC (shifted register)
47 @------------------------------------------------------------------------------
50 adc r4, r5, r6, lsl #1
51 adc r4, r5, r6, lsl #31
52 adc r4, r5, r6, lsr #1
53 adc r4, r5, r6, lsr #31
54 adc r4, r5, r6, lsr #32
55 adc r4, r5, r6, asr #1
56 adc r4, r5, r6, asr #31
57 adc r4, r5, r6, asr #32
58 adc r4, r5, r6, ror #1
59 adc r4, r5, r6, ror #31
62 adc r6, r7, r8, lsl r9
63 adc r6, r7, r8, lsr r9
64 adc r6, r7, r8, asr r9
65 adc r6, r7, r8, ror r9
68 @ Destination register is optional
87 @ CHECK: adc r4, r5, r6 @ encoding: [0x06,0x40,0xa5,0xe0]
89 @ CHECK: adc r4, r5, r6, lsl #1 @ encoding: [0x86,0x40,0xa5,0xe0]
90 @ CHECK: adc r4, r5, r6, lsl #31 @ encoding: [0x86,0x4f,0xa5,0xe0]
91 @ CHECK: adc r4, r5, r6, lsr #1 @ encoding: [0xa6,0x40,0xa5,0xe0]
92 @ CHECK: adc r4, r5, r6, lsr #31 @ encoding: [0xa6,0x4f,0xa5,0xe0]
93 @ CHECK: adc r4, r5, r6, lsr #32 @ encoding: [0x26,0x40,0xa5,0xe0]
94 @ CHECK: adc r4, r5, r6, asr #1 @ encoding: [0xc6,0x40,0xa5,0xe0]
95 @ CHECK: adc r4, r5, r6, asr #31 @ encoding: [0xc6,0x4f,0xa5,0xe0]
96 @ CHECK: adc r4, r5, r6, asr #32 @ encoding: [0x46,0x40,0xa5,0xe0]
97 @ CHECK: adc r4, r5, r6, ror #1 @ encoding: [0xe6,0x40,0xa5,0xe0]
98 @ CHECK: adc r4, r5, r6, ror #31 @ encoding: [0xe6,0x4f,0xa5,0xe0]
100 @ CHECK: adc r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0xa7,0xe0]
101 @ CHECK: adc r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0xa7,0xe0]
102 @ CHECK: adc r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0xa7,0xe0]
103 @ CHECK: adc r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0xa7,0xe0]
104 @ CHECK: adc r4, r5, r6, rrx @ encoding: [0x66,0x40,0xa5,0xe0]
106 @ CHECK: adc r5, r5, r6 @ encoding: [0x06,0x50,0xa5,0xe0]
107 @ CHECK: adc r4, r4, r5, lsl #1 @ encoding: [0x85,0x40,0xa4,0xe0]
108 @ CHECK: adc r4, r4, r5, lsl #31 @ encoding: [0x85,0x4f,0xa4,0xe0]
109 @ CHECK: adc r4, r4, r5, lsr #1 @ encoding: [0xa5,0x40,0xa4,0xe0]
110 @ CHECK: adc r4, r4, r5, lsr #31 @ encoding: [0xa5,0x4f,0xa4,0xe0]
111 @ CHECK: adc r4, r4, r5, lsr #32 @ encoding: [0x25,0x40,0xa4,0xe0]
112 @ CHECK: adc r4, r4, r5, asr #1 @ encoding: [0xc5,0x40,0xa4,0xe0]
113 @ CHECK: adc r4, r4, r5, asr #31 @ encoding: [0xc5,0x4f,0xa4,0xe0]
114 @ CHECK: adc r4, r4, r5, asr #32 @ encoding: [0x45,0x40,0xa4,0xe0]
115 @ CHECK: adc r4, r4, r5, ror #1 @ encoding: [0xe5,0x40,0xa4,0xe0]
116 @ CHECK: adc r4, r4, r5, ror #31 @ encoding: [0xe5,0x4f,0xa4,0xe0]
117 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
118 @ CHECK: adc r6, r6, r7, lsl r9 @ encoding: [0x17,0x69,0xa6,0xe0]
119 @ CHECK: adc r6, r6, r7, lsr r9 @ encoding: [0x37,0x69,0xa6,0xe0]
120 @ CHECK: adc r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0xa6,0xe0]
121 @ CHECK: adc r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0xa6,0xe0]
122 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
125 @------------------------------------------------------------------------------
127 @------------------------------------------------------------------------------
129 @------------------------------------------------------------------------------
131 @------------------------------------------------------------------------------
134 add r4, r5, r6, lsl #5
135 add r4, r5, r6, lsr #5
136 add r4, r5, r6, lsr #5
137 add r4, r5, r6, asr #5
138 add r4, r5, r6, ror #5
139 add r6, r7, r8, lsl r9
140 add r6, r7, r8, lsr r9
141 add r6, r7, r8, asr r9
142 add r6, r7, r8, ror r9
145 @ destination register is optional
159 @ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2]
160 @ CHECK: add r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe0]
161 @ CHECK: add r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe0]
162 @ CHECK: add r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe0]
163 @ CHECK: add r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe0]
164 @ CHECK: add r4, r5, r6, asr #5 @ encoding: [0xc6,0x42,0x85,0xe0]
165 @ CHECK: add r4, r5, r6, ror #5 @ encoding: [0xe6,0x42,0x85,0xe0]
166 @ CHECK: add r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0x87,0xe0]
167 @ CHECK: add r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0x87,0xe0]
168 @ CHECK: add r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0x87,0xe0]
169 @ CHECK: add r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0x87,0xe0]
170 @ CHECK: add r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe0]
173 @ CHECK: add r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe2]
174 @ CHECK: add r4, r4, r5 @ encoding: [0x05,0x40,0x84,0xe0]
175 @ CHECK: add r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x84,0xe0]
176 @ CHECK: add r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x84,0xe0]
177 @ CHECK: add r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x84,0xe0]
178 @ CHECK: add r4, r4, r5, asr #5 @ encoding: [0xc5,0x42,0x84,0xe0]
179 @ CHECK: add r4, r4, r5, ror #5 @ encoding: [0xe5,0x42,0x84,0xe0]
180 @ CHECK: add r6, r6, r7, lsl r9 @ encoding: [0x17,0x69,0x86,0xe0]
181 @ CHECK: add r6, r6, r7, lsr r9 @ encoding: [0x37,0x69,0x86,0xe0]
182 @ CHECK: add r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0x86,0xe0]
183 @ CHECK: add r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x86,0xe0]
184 @ CHECK: add r4, r4, r5, rrx @ encoding: [0x65,0x40,0x84,0xe0]
187 @------------------------------------------------------------------------------
189 @------------------------------------------------------------------------------
192 and r10, r1, r6, lsl #10
193 and r10, r1, r6, lsr #10
194 and r10, r1, r6, lsr #10
195 and r10, r1, r6, asr #10
196 and r10, r1, r6, ror #10
197 and r6, r7, r8, lsl r2
198 and r6, r7, r8, lsr r2
199 and r6, r7, r8, asr r2
200 and r6, r7, r8, ror r2
203 @ destination register is optional
217 @ CHECK: and r10, r1, #15 @ encoding: [0x0f,0xa0,0x01,0xe2]
218 @ CHECK: and r10, r1, r6 @ encoding: [0x06,0xa0,0x01,0xe0]
219 @ CHECK: and r10, r1, r6, lsl #10 @ encoding: [0x06,0xa5,0x01,0xe0]
220 @ CHECK: and r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0x01,0xe0]
221 @ CHECK: and r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0x01,0xe0]
222 @ CHECK: and r10, r1, r6, asr #10 @ encoding: [0x46,0xa5,0x01,0xe0]
223 @ CHECK: and r10, r1, r6, ror #10 @ encoding: [0x66,0xa5,0x01,0xe0]
224 @ CHECK: and r6, r7, r8, lsl r2 @ encoding: [0x18,0x62,0x07,0xe0]
225 @ CHECK: and r6, r7, r8, lsr r2 @ encoding: [0x38,0x62,0x07,0xe0]
226 @ CHECK: and r6, r7, r8, asr r2 @ encoding: [0x58,0x62,0x07,0xe0]
227 @ CHECK: and r6, r7, r8, ror r2 @ encoding: [0x78,0x62,0x07,0xe0]
228 @ CHECK: and r10, r1, r6, rrx @ encoding: [0x66,0xa0,0x01,0xe0]
230 @ CHECK: and r1, r1, #15 @ encoding: [0x0f,0x10,0x01,0xe2]
231 @ CHECK: and r10, r10, r1 @ encoding: [0x01,0xa0,0x0a,0xe0]
232 @ CHECK: and r10, r10, r1, lsl #10 @ encoding: [0x01,0xa5,0x0a,0xe0]
233 @ CHECK: and r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0x0a,0xe0]
234 @ CHECK: and r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0x0a,0xe0]
235 @ CHECK: and r10, r10, r1, asr #10 @ encoding: [0x41,0xa5,0x0a,0xe0]
236 @ CHECK: and r10, r10, r1, ror #10 @ encoding: [0x61,0xa5,0x0a,0xe0]
237 @ CHECK: and r6, r6, r7, lsl r2 @ encoding: [0x17,0x62,0x06,0xe0]
238 @ CHECK: and r6, r6, r7, lsr r2 @ encoding: [0x37,0x62,0x06,0xe0]
239 @ CHECK: and r6, r6, r7, asr r2 @ encoding: [0x57,0x62,0x06,0xe0]
240 @ CHECK: and r6, r6, r7, ror r2 @ encoding: [0x77,0x62,0x06,0xe0]
241 @ CHECK: and r10, r10, r1, rrx @ encoding: [0x61,0xa0,0x0a,0xe0]
243 @------------------------------------------------------------------------------
245 @------------------------------------------------------------------------------
246 @------------------------------------------------------------------------------
248 @------------------------------------------------------------------------------
249 @------------------------------------------------------------------------------
251 @------------------------------------------------------------------------------
252 @------------------------------------------------------------------------------
254 @------------------------------------------------------------------------------
256 @------------------------------------------------------------------------------
258 @------------------------------------------------------------------------------
261 bic r10, r1, r6, lsl #10
262 bic r10, r1, r6, lsr #10
263 bic r10, r1, r6, lsr #10
264 bic r10, r1, r6, asr #10
265 bic r10, r1, r6, ror #10
266 bic r6, r7, r8, lsl r2
267 bic r6, r7, r8, lsr r2
268 bic r6, r7, r8, asr r2
269 bic r6, r7, r8, ror r2
272 @ destination register is optional
286 @ CHECK: bic r10, r1, #15 @ encoding: [0x0f,0xa0,0xc1,0xe3]
287 @ CHECK: bic r10, r1, r6 @ encoding: [0x06,0xa0,0xc1,0xe1]
288 @ CHECK: bic r10, r1, r6, lsl #10 @ encoding: [0x06,0xa5,0xc1,0xe1]
289 @ CHECK: bic r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0xc1,0xe1]
290 @ CHECK: bic r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0xc1,0xe1]
291 @ CHECK: bic r10, r1, r6, asr #10 @ encoding: [0x46,0xa5,0xc1,0xe1]
292 @ CHECK: bic r10, r1, r6, ror #10 @ encoding: [0x66,0xa5,0xc1,0xe1]
293 @ CHECK: bic r6, r7, r8, lsl r2 @ encoding: [0x18,0x62,0xc7,0xe1]
294 @ CHECK: bic r6, r7, r8, lsr r2 @ encoding: [0x38,0x62,0xc7,0xe1]
295 @ CHECK: bic r6, r7, r8, asr r2 @ encoding: [0x58,0x62,0xc7,0xe1]
296 @ CHECK: bic r6, r7, r8, ror r2 @ encoding: [0x78,0x62,0xc7,0xe1]
297 @ CHECK: bic r10, r1, r6, rrx @ encoding: [0x66,0xa0,0xc1,0xe1]
300 @ CHECK: bic r1, r1, #15 @ encoding: [0x0f,0x10,0xc1,0xe3]
301 @ CHECK: bic r10, r10, r1 @ encoding: [0x01,0xa0,0xca,0xe1]
302 @ CHECK: bic r10, r10, r1, lsl #10 @ encoding: [0x01,0xa5,0xca,0xe1]
303 @ CHECK: bic r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0xca,0xe1]
304 @ CHECK: bic r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0xca,0xe1]
305 @ CHECK: bic r10, r10, r1, asr #10 @ encoding: [0x41,0xa5,0xca,0xe1]
306 @ CHECK: bic r10, r10, r1, ror #10 @ encoding: [0x61,0xa5,0xca,0xe1]
307 @ CHECK: bic r6, r6, r7, lsl r2 @ encoding: [0x17,0x62,0xc6,0xe1]
308 @ CHECK: bic r6, r6, r7, lsr r2 @ encoding: [0x37,0x62,0xc6,0xe1]
309 @ CHECK: bic r6, r6, r7, asr r2 @ encoding: [0x57,0x62,0xc6,0xe1]
310 @ CHECK: bic r6, r6, r7, ror r2 @ encoding: [0x77,0x62,0xc6,0xe1]
311 @ CHECK: bic r10, r10, r1, rrx @ encoding: [0x61,0xa0,0xca,0xe1]
313 @------------------------------------------------------------------------------
315 @------------------------------------------------------------------------------
319 @ CHECK: bkpt #10 @ encoding: [0x7a,0x00,0x20,0xe1]
320 @ CHECK: bkpt #65535 @ encoding: [0x7f,0xff,0x2f,0xe1]
322 @------------------------------------------------------------------------------
324 @------------------------------------------------------------------------------
329 @ CHECK: bl _bar @ encoding: [A,A,A,0xeb]
330 @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch
332 @------------------------------------------------------------------------------
334 @------------------------------------------------------------------------------
338 @ CHECK: blx r2 @ encoding: [0x32,0xff,0x2f,0xe1]
339 @ CHECK: blxne r2 @ encoding: [0x32,0xff,0x2f,0x11]
341 @------------------------------------------------------------------------------
343 @------------------------------------------------------------------------------
348 @ CHECK: bx r2 @ encoding: [0x12,0xff,0x2f,0xe1]
349 @ CHECK: bxne r2 @ encoding: [0x12,0xff,0x2f,0x11]
351 @------------------------------------------------------------------------------
353 @------------------------------------------------------------------------------
358 @ CHECK: bxj r2 @ encoding: [0x22,0xff,0x2f,0xe1]
359 @ CHECK: bxjne r2 @ encoding: [0x22,0xff,0x2f,0x11]
361 @------------------------------------------------------------------------------
363 @------------------------------------------------------------------------------
366 @------------------------------------------------------------------------------
368 @------------------------------------------------------------------------------
369 cdp p7, #1, c1, c1, c1, #4
370 cdp2 p7, #1, c1, c1, c1, #4
372 @ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee]
373 @ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe]
376 @------------------------------------------------------------------------------
378 @------------------------------------------------------------------------------
381 @ CHECK: clrex @ encoding: [0x1f,0xf0,0x7f,0xf5]
384 @------------------------------------------------------------------------------
386 @------------------------------------------------------------------------------
390 @ CHECK: clz r1, r2 @ encoding: [0x12,0x1f,0x6f,0xe1]
391 @ CHECK: clzeq r1, r2 @ encoding: [0x12,0x1f,0x6f,0x01]