1 @ RUN: llvm-mc -triple=thumbv6-apple-darwin -show-encoding < %s | FileCheck %s
5 @ Check that the assembler can handle the documented syntax from the ARM ARM.
6 @ For complex constructs like shifter operands, check more thoroughly for them
7 @ once then spot check that following instructions accept the form generally.
8 @ This gives us good coverage while keeping the overall size of the test
14 @------------------------------------------------------------------------------
16 @------------------------------------------------------------------------------
19 @ CHECK: adcs r4, r6 @ encoding: [0x74,0x41]
22 @------------------------------------------------------------------------------
24 @------------------------------------------------------------------------------
29 @ CHECK: adds r1, r2, #3 @ encoding: [0xd1,0x1c]
30 @ CHECK: adds r2, r2, #3 @ encoding: [0xd2,0x1c]
31 @ CHECK: adds r2, #8 @ encoding: [0x08,0x32]
34 @------------------------------------------------------------------------------
36 @------------------------------------------------------------------------------
40 @ CHECK: adds r1, r2, r3 @ encoding: [0xd1,0x18]
41 @ CHECK: add r2, r8 @ encoding: [0x42,0x44]
44 @------------------------------------------------------------------------------
45 @ FIXME: ADD (SP plus immediate)
46 @------------------------------------------------------------------------------
47 @------------------------------------------------------------------------------
48 @ FIXME: ADD (SP plus register)
49 @------------------------------------------------------------------------------
52 @------------------------------------------------------------------------------
54 @------------------------------------------------------------------------------
57 @ CHECK: adr r2, _baz @ encoding: [A,0xa2]
58 @ fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10
61 @------------------------------------------------------------------------------
63 @------------------------------------------------------------------------------
68 @ CHECK: asrs r2, r3, #32 @ encoding: [0x1a,0x10]
69 @ CHECK: asrs r2, r3, #5 @ encoding: [0x5a,0x11]
70 @ CHECK: asrs r2, r3, #1 @ encoding: [0x5a,0x10]
73 @------------------------------------------------------------------------------
75 @------------------------------------------------------------------------------
78 @ CHECK: asrs r5, r2 @ encoding: [0x15,0x41]