1 ; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
3 define <8 x i8> @vabss8(<8 x i8>* %A) nounwind {
4 %tmp1 = load <8 x i8>* %A
5 ; CHECK: vabs.s8 d16, d16 @ encoding: [0x20,0x03,0xf1,0xf3]
6 %tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1)
10 define <4 x i16> @vabss16(<4 x i16>* %A) nounwind {
11 %tmp1 = load <4 x i16>* %A
12 ; CHECK: vabs.s16 d16, d16 @ encoding: [0x20,0x03,0xf5,0xf3]
13 %tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1)
17 define <2 x i32> @vabss32(<2 x i32>* %A) nounwind {
18 %tmp1 = load <2 x i32>* %A
19 ; CHECK: vabs.s32 d16, d16 @ encoding: [0x20,0x03,0xf9,0xf3]
20 %tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1)
24 define <2 x float> @vabsf32(<2 x float>* %A) nounwind {
25 %tmp1 = load <2 x float>* %A
26 ; CHECK: vabs.f32 d16, d16 @ encoding: [0x20,0x07,0xf9,0xf3]
27 %tmp2 = call <2 x float> @llvm.arm.neon.vabs.v2f32(<2 x float> %tmp1)
31 define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind {
32 %tmp1 = load <16 x i8>* %A
33 ; CHECK: vabs.s8 q8, q8 @ encoding: [0x60,0x03,0xf1,0xf3]
34 %tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1)
38 define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind {
39 %tmp1 = load <8 x i16>* %A
40 ; CHECK: vabs.s16 q8, q8 @ encoding: [0x60,0x03,0xf5,0xf3]
41 %tmp2 = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %tmp1)
45 define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind {
46 %tmp1 = load <4 x i32>* %A
47 ; CHECK: vabs.s32 q8, q8 @ encoding: [0x60,0x03,0xf9,0xf3]
48 %tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1)
52 define <4 x float> @vabsQf32(<4 x float>* %A) nounwind {
53 %tmp1 = load <4 x float>* %A
54 ; CHECK: vabs.f32 q8, q8 @ encoding: [0x60,0x07,0xf9,0xf3]
55 %tmp2 = call <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float> %tmp1)
59 declare <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8>) nounwind readnone
60 declare <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16>) nounwind readnone
61 declare <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32>) nounwind readnone
62 declare <2 x float> @llvm.arm.neon.vabs.v2f32(<2 x float>) nounwind readnone
64 declare <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8>) nounwind readnone
65 declare <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16>) nounwind readnone
66 declare <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32>) nounwind readnone
67 declare <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float>) nounwind readnone
69 define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind {
70 %tmp1 = load <8 x i8>* %A
71 ; CHECK: vqabs.s8 d16, d16 @ encoding: [0x20,0x07,0xf0,0xf3]
72 %tmp2 = call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %tmp1)
76 define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind {
77 %tmp1 = load <4 x i16>* %A
78 ; CHECK: vqabs.s16 d16, d16 @ encoding: [0x20,0x07,0xf4,0xf3]
79 %tmp2 = call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %tmp1)
83 define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind {
84 %tmp1 = load <2 x i32>* %A
85 ; CHECK: vqabs.s32 d16, d16 @ encoding: [0x20,0x07,0xf8,0xf3]
86 %tmp2 = call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %tmp1)
90 define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind {
91 %tmp1 = load <16 x i8>* %A
92 ; CHECK: vqabs.s8 q8, q8 @ encoding: [0x60,0x07,0xf0,0xf3]
93 %tmp2 = call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %tmp1)
97 define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind {
98 %tmp1 = load <8 x i16>* %A
99 ; CHECK: vqabs.s16 q8, q8 @ encoding: [0x60,0x07,0xf4,0xf3]
100 %tmp2 = call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %tmp1)
104 define <4 x i32> @vqabsQs32(<4 x i32>* %A) nounwind {
105 %tmp1 = load <4 x i32>* %A
106 ; CHECK: vqabs.s32 q8, q8 @ encoding: [0x60,0x07,0xf8,0xf3]
107 %tmp2 = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %tmp1)
111 declare <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8>) nounwind readnone
112 declare <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16>) nounwind readnone
113 declare <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32>) nounwind readnone
115 declare <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8>) nounwind readnone
116 declare <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16>) nounwind readnone
117 declare <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32>) nounwind readnone