1 ; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
3 declare <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
4 declare <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
5 declare <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
8 define <8 x i8> @vabds_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
9 %tmp1 = load <8 x i8>* %A
10 %tmp2 = load <8 x i8>* %B
11 ; CHECK: vabd.s8 d16, d16, d17 @ encoding: [0xa1,0x07,0x40,0xf2]
12 %tmp3 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
17 define <4 x i16> @vabds_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
18 %tmp1 = load <4 x i16>* %A
19 %tmp2 = load <4 x i16>* %B
20 ; CHECK: vabd.s16 d16, d16, d17 @ encoding: [0xa1,0x07,0x50,0xf2]
21 %tmp3 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
26 define <2 x i32> @vabds_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
27 %tmp1 = load <2 x i32>* %A
28 %tmp2 = load <2 x i32>* %B
29 ; CHECK: vabd.s32 d16, d16, d17 @ encoding: [0xa1,0x07,0x60,0xf2]
30 %tmp3 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
34 declare <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
35 declare <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
36 declare <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
39 define <8 x i8> @vabdu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
40 %tmp1 = load <8 x i8>* %A
41 %tmp2 = load <8 x i8>* %B
42 ; CHECK: vabd.u8 d16, d16, d17 @ encoding: [0xa1,0x07,0x40,0xf3]
43 %tmp3 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
48 define <4 x i16> @vabdu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
49 %tmp1 = load <4 x i16>* %A
50 %tmp2 = load <4 x i16>* %B
51 ; CHECK: vabd.u16 d16, d16, d17 @ encoding: [0xa1,0x07,0x50,0xf3]
52 %tmp3 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
57 define <2 x i32> @vabdu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
58 %tmp1 = load <2 x i32>* %A
59 %tmp2 = load <2 x i32>* %B
60 ; CHECK: vabd.u32 d16, d16, d17 @ encoding: [0xa1,0x07,0x60,0xf3]
61 %tmp3 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
65 declare <2 x float> @llvm.arm.neon.vabds.v2f32(<2 x float>, <2 x float>) nounwind readnone
68 define <2 x float> @vabd_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
69 %tmp1 = load <2 x float>* %A
70 %tmp2 = load <2 x float>* %B
71 ; CHECK: vabd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x60,0xf3]
72 %tmp3 = call <2 x float> @llvm.arm.neon.vabds.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
76 declare <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
77 declare <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
78 declare <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
81 define <16 x i8> @vabds_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
82 %tmp1 = load <16 x i8>* %A
83 %tmp2 = load <16 x i8>* %B
84 ; CHECK: vabd.s8 q8, q8, q9 @ encoding: [0xe2,0x07,0x40,0xf2]
85 %tmp3 = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
90 define <8 x i16> @vabds_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
91 %tmp1 = load <8 x i16>* %A
92 %tmp2 = load <8 x i16>* %B
93 ; CHECK: vabd.s16 q8, q8, q9 @ encoding: [0xe2,0x07,0x50,0xf2]
94 %tmp3 = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
99 define <4 x i32> @vabds_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
100 %tmp1 = load <4 x i32>* %A
101 %tmp2 = load <4 x i32>* %B
102 ; CHECK: vabd.s32 q8, q8, q9 @ encoding: [0xe2,0x07,0x60,0xf2]
103 %tmp3 = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
107 declare <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
108 declare <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
109 declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
112 define <16 x i8> @vabdu_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
113 %tmp1 = load <16 x i8>* %A
114 %tmp2 = load <16 x i8>* %B
115 ; CHECK: vabd.u8 q8, q8, q9 @ encoding: [0xe2,0x07,0x40,0xf3]
116 %tmp3 = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
121 define <8 x i16> @vabdu_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
122 %tmp1 = load <8 x i16>* %A
123 %tmp2 = load <8 x i16>* %B
124 ; CHECK: vabd.u16 q8, q8, q9 @ encoding: [0xe2,0x07,0x50,0xf3]
125 %tmp3 = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
130 define <4 x i32> @vabdu_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
131 %tmp1 = load <4 x i32>* %A
132 %tmp2 = load <4 x i32>* %B
133 ; CHECK: vabd.u32 q8, q8, q9 @ encoding: [0xe2,0x07,0x60,0xf3]
134 %tmp3 = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
138 declare <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float>, <4 x float>) nounwind readnone
140 ; CHECK: vabd_4xfloat
141 define <4 x float> @vabd_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind {
142 %tmp1 = load <4 x float>* %A
143 %tmp2 = load <4 x float>* %B
144 ; CHECK: vabd.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x60,0xf3]
145 %tmp3 = call <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
146 ret <4 x float> %tmp3
150 define <8 x i16> @vabdls_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
151 %tmp1 = load <8 x i8>* %A
152 %tmp2 = load <8 x i8>* %B
153 ; CHECK: vabdl.s8 q8, d16, d17 @ encoding: [0xa1,0x07,0xc0,0xf2]
154 %tmp3 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
155 %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
159 ; CHECK: vabdls_4xi16
160 define <4 x i32> @vabdls_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
161 %tmp1 = load <4 x i16>* %A
162 %tmp2 = load <4 x i16>* %B
163 ; CHECK: vabdl.s16 q8, d16, d17 @ encoding: [0xa1,0x07,0xd0,0xf2]
164 %tmp3 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
165 %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
169 ; CHECK: vabdls_2xi32
170 define <2 x i64> @vabdls_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
171 %tmp1 = load <2 x i32>* %A
172 %tmp2 = load <2 x i32>* %B
173 ; CHECK: vabdl.s32 q8, d16, d17 @ encoding: [0xa1,0x07,0xe0,0xf2]
174 %tmp3 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
175 %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
180 define <8 x i16> @vabdlu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
181 %tmp1 = load <8 x i8>* %A
182 %tmp2 = load <8 x i8>* %B
183 ; CHECK: vabdl.u8 q8, d16, d17 @ encoding: [0xa1,0x07,0xc0,0xf3]
184 %tmp3 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
185 %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
189 ; CHECK: vabdlu_4xi16
190 define <4 x i32> @vabdlu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
191 %tmp1 = load <4 x i16>* %A
192 %tmp2 = load <4 x i16>* %B
193 ; CHECK: vabdl.u16 q8, d16, d17 @ encoding: [0xa1,0x07,0xd0,0xf3]
194 %tmp3 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
195 %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
200 define <2 x i64> @vabdlu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
201 %tmp1 = load <2 x i32>* %A
202 %tmp2 = load <2 x i32>* %B
203 %tmp3 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
204 %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
209 define <8 x i8> @vabas_8xi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
210 %tmp1 = load <8 x i8>* %A
211 %tmp2 = load <8 x i8>* %B
212 %tmp3 = load <8 x i8>* %C
213 ; CHECK: vaba.s8 d16, d18, d17 @ encoding: [0xb1,0x07,0x42,0xf2]
214 %tmp4 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
215 %tmp5 = add <8 x i8> %tmp1, %tmp4
220 define <4 x i16> @vabas_4xi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
221 %tmp1 = load <4 x i16>* %A
222 %tmp2 = load <4 x i16>* %B
223 %tmp3 = load <4 x i16>* %C
224 ; CHECK: vaba.s16 d16, d18, d17 @ encoding: [0xb1,0x07,0x52,0xf2]
225 %tmp4 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
226 %tmp5 = add <4 x i16> %tmp1, %tmp4
231 define <2 x i32> @vabas_2xi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
232 %tmp1 = load <2 x i32>* %A
233 %tmp2 = load <2 x i32>* %B
234 %tmp3 = load <2 x i32>* %C
235 ; CHECK: vaba.s32 d16, d18, d17 @ encoding: [0xb1,0x07,0x62,0xf2]
236 %tmp4 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
237 %tmp5 = add <2 x i32> %tmp1, %tmp4
242 define <8 x i8> @vabau_8xi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
243 %tmp1 = load <8 x i8>* %A
244 %tmp2 = load <8 x i8>* %B
245 %tmp3 = load <8 x i8>* %C
246 ; CHECK: vaba.u8 d16, d18, d17 @ encoding: [0xb1,0x07,0x42,0xf3]
247 %tmp4 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
248 %tmp5 = add <8 x i8> %tmp1, %tmp4
253 define <4 x i16> @vabau_4xi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
254 %tmp1 = load <4 x i16>* %A
255 %tmp2 = load <4 x i16>* %B
256 %tmp3 = load <4 x i16>* %C
257 ; CHECK: vaba.u16 d16, d18, d17 @ encoding: [0xb1,0x07,0x52,0xf3]
258 %tmp4 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
259 %tmp5 = add <4 x i16> %tmp1, %tmp4
264 define <2 x i32> @vabau_2xi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
265 %tmp1 = load <2 x i32>* %A
266 %tmp2 = load <2 x i32>* %B
267 %tmp3 = load <2 x i32>* %C
268 ; CHECK: vaba.u32 d16, d18, d17 @ encoding: [0xb1,0x07,0x62,0xf3]
269 %tmp4 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
270 %tmp5 = add <2 x i32> %tmp1, %tmp4
275 define <16 x i8> @vabas_16xi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
276 %tmp1 = load <16 x i8>* %A
277 %tmp2 = load <16 x i8>* %B
278 %tmp3 = load <16 x i8>* %C
279 ; CHECK: vaba.s8 q9, q8, q10 @ encoding: [0xf4,0x27,0x40,0xf2]
280 %tmp4 = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> %tmp2, <16 x i8> %tmp3)
281 %tmp5 = add <16 x i8> %tmp1, %tmp4
286 define <8 x i16> @vabas_8xi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
287 %tmp1 = load <8 x i16>* %A
288 %tmp2 = load <8 x i16>* %B
289 %tmp3 = load <8 x i16>* %C
290 ; CHECK: vaba.s16 q9, q8, q10 @ encoding: [0xf4,0x27,0x50,0xf2]
291 %tmp4 = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp3)
292 %tmp5 = add <8 x i16> %tmp1, %tmp4
297 define <4 x i32> @vabas_4xi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
298 %tmp1 = load <4 x i32>* %A
299 %tmp2 = load <4 x i32>* %B
300 %tmp3 = load <4 x i32>* %C
301 ; CHECK: vaba.s32 q9, q8, q10 @ encoding: [0xf4,0x27,0x60,0xf2]
302 %tmp4 = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> %tmp2, <4 x i32> %tmp3)
303 %tmp5 = add <4 x i32> %tmp1, %tmp4
308 define <16 x i8> @vabau_16xi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
309 %tmp1 = load <16 x i8>* %A
310 %tmp2 = load <16 x i8>* %B
311 %tmp3 = load <16 x i8>* %C
312 ; CHECK: vaba.u8 q9, q8, q10 @ encoding: [0xf4,0x27,0x40,0xf3]
313 %tmp4 = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %tmp2, <16 x i8> %tmp3)
314 %tmp5 = add <16 x i8> %tmp1, %tmp4
319 define <8 x i16> @vabau_8xi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
320 %tmp1 = load <8 x i16>* %A
321 %tmp2 = load <8 x i16>* %B
322 %tmp3 = load <8 x i16>* %C
323 ; CHECK: vaba.u16 q9, q8, q10 @ encoding: [0xf4,0x27,0x50,0xf3]
324 %tmp4 = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp3)
325 %tmp5 = add <8 x i16> %tmp1, %tmp4
330 define <4 x i32> @vabau_4xi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
331 %tmp1 = load <4 x i32>* %A
332 %tmp2 = load <4 x i32>* %B
333 %tmp3 = load <4 x i32>* %C
334 ; CHECK: vaba.u32 q9, q8, q10 @ encoding: [0xf4,0x27,0x60,0xf3]
335 %tmp4 = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> %tmp2, <4 x i32> %tmp3)
336 %tmp5 = add <4 x i32> %tmp1, %tmp4
341 define <8 x i16> @vabals_8xi8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
342 %tmp1 = load <8 x i16>* %A
343 %tmp2 = load <8 x i8>* %B
344 %tmp3 = load <8 x i8>* %C
345 ; CHECK: vabal.s8 q8, d19, d18 @ encoding: [0xa2,0x05,0xc3,0xf2]
346 %tmp4 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
347 %tmp5 = zext <8 x i8> %tmp4 to <8 x i16>
348 %tmp6 = add <8 x i16> %tmp1, %tmp5
352 ; CHECK: vabals_4xi16
353 define <4 x i32> @vabals_4xi16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
354 %tmp1 = load <4 x i32>* %A
355 %tmp2 = load <4 x i16>* %B
356 %tmp3 = load <4 x i16>* %C
357 ; CHECK: vabal.s16 q8, d19, d18 @ encoding: [0xa2,0x05,0xd3,0xf2]
358 %tmp4 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
359 %tmp5 = zext <4 x i16> %tmp4 to <4 x i32>
360 %tmp6 = add <4 x i32> %tmp1, %tmp5
364 ; CHECK: vabals_2xi32
365 define <2 x i64> @vabals_2xi32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
366 %tmp1 = load <2 x i64>* %A
367 %tmp2 = load <2 x i32>* %B
368 %tmp3 = load <2 x i32>* %C
369 ; CHECK: vabal.s32 q8, d19, d18 @ encoding: [0xa2,0x05,0xe3,0xf2]
370 %tmp4 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
371 %tmp5 = zext <2 x i32> %tmp4 to <2 x i64>
372 %tmp6 = add <2 x i64> %tmp1, %tmp5
377 define <8 x i16> @vabalu_8xi8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
378 %tmp1 = load <8 x i16>* %A
379 %tmp2 = load <8 x i8>* %B
380 %tmp3 = load <8 x i8>* %C
381 ; CHECK: vabal.u8 q8, d19, d18 @ encoding: [0xa2,0x05,0xc3,0xf3]
382 %tmp4 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
383 %tmp5 = zext <8 x i8> %tmp4 to <8 x i16>
384 %tmp6 = add <8 x i16> %tmp1, %tmp5
388 ; CHECK: vabalu_4xi16
389 define <4 x i32> @vabalu_4xi16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
390 %tmp1 = load <4 x i32>* %A
391 %tmp2 = load <4 x i16>* %B
392 %tmp3 = load <4 x i16>* %C
393 ; CHECK: vabal.u16 q8, d19, d18 @ encoding: [0xa2,0x05,0xd3,0xf3]
394 %tmp4 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
395 %tmp5 = zext <4 x i16> %tmp4 to <4 x i32>
396 %tmp6 = add <4 x i32> %tmp1, %tmp5
400 ; CHECK: vabalu_2xi32
401 define <2 x i64> @vabalu_2xi32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
402 %tmp1 = load <2 x i64>* %A
403 %tmp2 = load <2 x i32>* %B
404 %tmp3 = load <2 x i32>* %C
405 ; CHECK: vabal.u32 q8, d19, d18 @ encoding: [0xa2,0x05,0xe3,0xf3]
406 %tmp4 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
407 %tmp5 = zext <2 x i32> %tmp4 to <2 x i64>
408 %tmp6 = add <2 x i64> %tmp1, %tmp5