1 ; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
3 define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
4 %tmp1 = load <2 x float>* %A
5 ; CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3]
6 %tmp2 = fptosi <2 x float> %tmp1 to <2 x i32>
10 define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
11 %tmp1 = load <2 x float>* %A
12 ; CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3]
13 %tmp2 = fptoui <2 x float> %tmp1 to <2 x i32>
17 define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
18 %tmp1 = load <2 x i32>* %A
19 ; CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3]
20 %tmp2 = sitofp <2 x i32> %tmp1 to <2 x float>
24 define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
25 %tmp1 = load <2 x i32>* %A
26 ; CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3]
27 %tmp2 = uitofp <2 x i32> %tmp1 to <2 x float>
31 define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
32 %tmp1 = load <4 x float>* %A
33 ; CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3]
34 %tmp2 = fptosi <4 x float> %tmp1 to <4 x i32>
38 define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
39 %tmp1 = load <4 x float>* %A
40 ; CHECK: vcvt.u32.f32 q8, q8 @ encoding: [0xe0,0x07,0xfb,0xf3]
41 %tmp2 = fptoui <4 x float> %tmp1 to <4 x i32>
45 define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
46 %tmp1 = load <4 x i32>* %A
47 ; CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0x60,0x06,0xfb,0xf3]
48 %tmp2 = sitofp <4 x i32> %tmp1 to <4 x float>
52 define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
53 %tmp1 = load <4 x i32>* %A
54 ; CHECK: vcvt.f32.u32 q8, q8 @ encoding: [0xe0,0x06,0xfb,0xf3]
55 %tmp2 = uitofp <4 x i32> %tmp1 to <4 x float>
59 define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind {
60 %tmp1 = load <2 x float>* %A
61 ; CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf2
62 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1)
66 define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind {
67 %tmp1 = load <2 x float>* %A
68 ; CHECK: vcvt.u32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf3]
69 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1)
73 define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind {
74 %tmp1 = load <2 x i32>* %A
75 ; CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf2]
76 %tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
80 define <2 x float> @vcvt_n_u32tof32(<2 x i32>* %A) nounwind {
81 %tmp1 = load <2 x i32>* %A
82 ; CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf3]
83 %tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
87 declare <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float>, i32) nounwind readnone
88 declare <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float>, i32) nounwind readnone
89 declare <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
90 declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
92 define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind {
93 %tmp1 = load <4 x float>* %A
94 ; CHECK: vcvt.s32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf2]
95 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1)
99 define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind {
100 %tmp1 = load <4 x float>* %A
101 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1)
105 define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind {
106 %tmp1 = load <4 x i32>* %A
107 ; CHECK: vcvt.u32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf3]
108 %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
109 ret <4 x float> %tmp2
112 define <4 x float> @vcvtQ_n_u32tof32(<4 x i32>* %A) nounwind {
113 %tmp1 = load <4 x i32>* %A
114 ; CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf3]
115 %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
116 ret <4 x float> %tmp2
119 declare <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) nounwind readnone
120 declare <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwind readnone
121 declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
122 declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone