1 ; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
3 declare <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
4 declare <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
5 declare <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
8 define <8 x i8> @vmins_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
9 %tmp1 = load <8 x i8>* %A
10 %tmp2 = load <8 x i8>* %B
11 ; CHECK: vmin.s8 d16, d16, d17 @ encoding: [0xb1,0x06,0x40,0xf2]
12 %tmp3 = call <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
17 define <4 x i16> @vmins_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
18 %tmp1 = load <4 x i16>* %A
19 %tmp2 = load <4 x i16>* %B
20 ; CHECK: vmin.s16 d16, d16, d17 @ encoding: [0xb1,0x06,0x50,0xf2]
21 %tmp3 = call <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
26 define <2 x i32> @vmins_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
27 %tmp1 = load <2 x i32>* %A
28 %tmp2 = load <2 x i32>* %B
29 ; CHECK: vmin.s32 d16, d16, d17 @ encoding: [0xb1,0x06,0x60,0xf2]
30 %tmp3 = call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
34 declare <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
35 declare <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
36 declare <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
39 define <8 x i8> @vminu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
40 %tmp1 = load <8 x i8>* %A
41 %tmp2 = load <8 x i8>* %B
42 ; CHECK: vmin.u8 d16, d16, d17 @ encoding: [0xb1,0x06,0x40,0xf3]
43 %tmp3 = call <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
48 define <4 x i16> @vminu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
49 %tmp1 = load <4 x i16>* %A
50 %tmp2 = load <4 x i16>* %B
51 ; CHECK: vmin.u16 d16, d16, d17 @ encoding: [0xb1,0x06,0x50,0xf3]
52 %tmp3 = call <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
57 define <2 x i32> @vminu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
58 %tmp1 = load <2 x i32>* %A
59 %tmp2 = load <2 x i32>* %B
60 ; CHECK: vmin.u32 d16, d16, d17 @ encoding: [0xb1,0x06,0x60,0xf3]
61 %tmp3 = call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
65 declare <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float>, <2 x float>) nounwind readnone
68 define <2 x float> @vmin_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
69 %tmp1 = load <2 x float>* %A
70 %tmp2 = load <2 x float>* %B
71 ; CHECK: vmin.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x60,0xf2]
72 %tmp3 = call <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
76 declare <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
77 declare <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
78 declare <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
81 define <16 x i8> @vmins_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
82 %tmp1 = load <16 x i8>* %A
83 %tmp2 = load <16 x i8>* %B
84 ; CHECK: vmin.s8 q8, q8, q9 @ encoding: [0xf2,0x06,0x40,0xf2]
85 %tmp3 = call <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
90 define <8 x i16> @vmins_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
91 %tmp1 = load <8 x i16>* %A
92 %tmp2 = load <8 x i16>* %B
93 ; CHECK: vmin.s16 q8, q8, q9 @ encoding: [0xf2,0x06,0x50,0xf2]
94 %tmp3 = call <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
99 define <4 x i32> @vmins_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
100 %tmp1 = load <4 x i32>* %A
101 %tmp2 = load <4 x i32>* %B
102 ; CHECK: vmin.s32 q8, q8, q9 @ encoding: [0xf2,0x06,0x60,0xf2]
103 %tmp3 = call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
107 declare <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
108 declare <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
109 declare <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
112 define <16 x i8> @vminu_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
113 %tmp1 = load <16 x i8>* %A
114 %tmp2 = load <16 x i8>* %B
115 ; CHECK: vmin.u8 q8, q8, q9 @ encoding: [0xf2,0x06,0x40,0xf3]
116 %tmp3 = call <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
121 define <8 x i16> @vminu_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
122 %tmp1 = load <8 x i16>* %A
123 %tmp2 = load <8 x i16>* %B
124 ; CHECK: vmin.u16 q8, q8, q9 @ encoding: [0xf2,0x06,0x50,0xf3]
125 %tmp3 = call <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
130 define <4 x i32> @vminu_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
131 %tmp1 = load <4 x i32>* %A
132 %tmp2 = load <4 x i32>* %B
133 ; CHECK: vmin.u32 q8, q8, q9 @ encoding: [0xf2,0x06,0x60,0xf3]
134 %tmp3 = call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
138 declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
140 ; CHECK: vmin_4xfloat
141 define <4 x float> @vmin_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind {
142 %tmp1 = load <4 x float>* %A
143 %tmp2 = load <4 x float>* %B
144 ; CHECK: vmin.f32 q8, q8, q9 @ encoding: [0xe2,0x0f,0x60,0xf2]
145 %tmp3 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
146 ret <4 x float> %tmp3
149 declare <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
150 declare <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
151 declare <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
154 define <8 x i8> @vmaxs_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
155 %tmp1 = load <8 x i8>* %A
156 %tmp2 = load <8 x i8>* %B
157 ; CHECK: vmax.s8 d16, d16, d17 @ encoding: [0xa1,0x06,0x40,0xf2]
158 %tmp3 = call <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
163 define <4 x i16> @vmaxs_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
164 %tmp1 = load <4 x i16>* %A
165 %tmp2 = load <4 x i16>* %B
166 ; CHECK: vmax.s16 d16, d16, d17 @ encoding: [0xa1,0x06,0x50,0xf2]
167 %tmp3 = call <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
172 define <2 x i32> @vmaxs_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
173 %tmp1 = load <2 x i32>* %A
174 %tmp2 = load <2 x i32>* %B
175 ; CHECK: vmax.s32 d16, d16, d17 @ encoding: [0xa1,0x06,0x60,0xf2]
176 %tmp3 = call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
180 declare <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
181 declare <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
182 declare <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
185 define <8 x i8> @vmaxu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
186 %tmp1 = load <8 x i8>* %A
187 %tmp2 = load <8 x i8>* %B
188 ; CHECK: vmax.u8 d16, d16, d17 @ encoding: [0xa1,0x06,0x40,0xf3]
189 %tmp3 = call <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
194 define <4 x i16> @vmaxu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
195 %tmp1 = load <4 x i16>* %A
196 %tmp2 = load <4 x i16>* %B
197 ; CHECK: vmax.u16 d16, d16, d17 @ encoding: [0xa1,0x06,0x50,0xf3]
198 %tmp3 = call <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
203 define <2 x i32> @vmaxu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
204 %tmp1 = load <2 x i32>* %A
205 %tmp2 = load <2 x i32>* %B
206 ; CHECK: vmax.u32 d16, d16, d17 @ encoding: [0xa1,0x06,0x60,0xf3]
207 %tmp3 = call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
211 declare <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float>, <2 x float>) nounwind readnone
213 ; CHECK: vmax_2xfloat
214 define <2 x float> @vmax_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
215 %tmp1 = load <2 x float>* %A
216 %tmp2 = load <2 x float>* %B
217 ; CHECK: vmax.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x40,0xf2]
218 %tmp3 = call <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
219 ret <2 x float> %tmp3
222 declare <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
223 declare <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
224 declare <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
227 define <16 x i8> @vmaxs_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
228 %tmp1 = load <16 x i8>* %A
229 %tmp2 = load <16 x i8>* %B
230 ; CHECK: vmax.s8 q8, q8, q9 @ encoding: [0xe2,0x06,0x40,0xf2]
231 %tmp3 = call <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
236 define <8 x i16> @vmaxs_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
237 %tmp1 = load <8 x i16>* %A
238 %tmp2 = load <8 x i16>* %B
239 ; CHECK: vmax.s16 q8, q8, q9 @ encoding: [0xe2,0x06,0x50,0xf2]
240 %tmp3 = call <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
245 define <4 x i32> @vmaxs_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
246 %tmp1 = load <4 x i32>* %A
247 %tmp2 = load <4 x i32>* %B
248 ; CHECK: vmax.s32 q8, q8, q9 @ encoding: [0xe2,0x06,0x60,0xf2]
249 %tmp3 = call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
253 declare <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
254 declare <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
255 declare <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
258 define <16 x i8> @vmaxu_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
259 %tmp1 = load <16 x i8>* %A
260 %tmp2 = load <16 x i8>* %B
261 ; CHECK: vmax.u8 q8, q8, q9 @ encoding: [0xe2,0x06,0x40,0xf3]
262 %tmp3 = call <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
267 define <8 x i16> @vmaxu_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
268 %tmp1 = load <8 x i16>* %A
269 %tmp2 = load <8 x i16>* %B
270 ; CHECK: vmax.u16 q8, q8, q9 @ encoding: [0xe2,0x06,0x50,0xf3]
271 %tmp3 = call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
276 define <4 x i32> @vmaxu_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
277 %tmp1 = load <4 x i32>* %A
278 %tmp2 = load <4 x i32>* %B
279 ; CHECK: vmax.u32 q8, q8, q9 @ encoding: [0xe2,0x06,0x60,0xf3]
280 %tmp3 = call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
284 declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone
286 ; CHECK: vmax_4xfloat
287 define <4 x float> @vmax_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind {
288 %tmp1 = load <4 x float>* %A
289 %tmp2 = load <4 x float>* %B
290 ; CHECK: vmax.f32 q8, q8, q9 @ encoding: [0xe2,0x0f,0x40,0xf2]
291 %tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
292 ret <4 x float> %tmp3