1 ; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
4 define <8 x i8> @vmov_8xi8() nounwind {
5 ; CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2]
6 ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
10 define <4 x i16> @vmov_4xi16a() nounwind {
11 ; CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xf2]
12 ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
16 define <4 x i16> @vmov_4xi16b() nounwind {
17 ; CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xf2]
18 ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
22 define <2 x i32> @vmov_2xi32a() nounwind {
23 ; CHECK: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xf2]
24 ret <2 x i32> < i32 32, i32 32 >
28 define <2 x i32> @vmov_2xi32b() nounwind {
29 ; CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2]
30 ret <2 x i32> < i32 8192, i32 8192 >
34 define <2 x i32> @vmov_2xi32c() nounwind {
35 ; CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2]
36 ret <2 x i32> < i32 2097152, i32 2097152 >
40 define <2 x i32> @vmov_2xi32d() nounwind {
41 ; CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2]
42 ret <2 x i32> < i32 536870912, i32 536870912 >
46 define <2 x i32> @vmov_2xi32e() nounwind {
47 ; CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2]
48 ret <2 x i32> < i32 8447, i32 8447 >
52 define <2 x i32> @vmov_2xi32f() nounwind {
53 ; CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2]
54 ret <2 x i32> < i32 2162687, i32 2162687 >
58 define <1 x i64> @vmov_1xi64() nounwind {
59 ; CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3]
60 ret <1 x i64> < i64 18374687574888349695 >
64 define <16 x i8> @vmov_16xi8() nounwind {
65 ; CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xf2]
66 ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
70 define <8 x i16> @vmov_8xi16a() nounwind {
71 ; CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xf2]
72 ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
76 define <8 x i16> @vmov_8xi16b() nounwind {
77 ; CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xf2]
78 ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
82 define <4 x i32> @vmov_4xi32a() nounwind {
83 ; CHECK: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xf2]
84 ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
88 define <4 x i32> @vmov_4xi32b() nounwind {
89 ; CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2]
90 ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
94 define <4 x i32> @vmov_4xi32c() nounwind {
95 ; CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2]
96 ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
100 define <4 x i32> @vmov_4xi32d() nounwind {
101 ; CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2]
102 ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
106 define <4 x i32> @vmov_4xi32e() nounwind {
107 ; CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2]
108 ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
112 define <4 x i32> @vmov_4xi32f() nounwind {
113 ; CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2]
114 ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
118 define <2 x i64> @vmov_2xi64() nounwind {
119 ; CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3]
120 ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
124 define <4 x i16> @vmvn_4xi16a() nounwind {
125 ; CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xf2]
126 ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
130 define <4 x i16> @vmvn_4xi16b() nounwind {
131 ; CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xf2]
132 ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
136 define <2 x i32> @vmvn_2xi32a() nounwind {
137 ; CHECK: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xf2]
138 ret <2 x i32> < i32 4294967263, i32 4294967263 >
142 define <2 x i32> @vmvn_2xi32b() nounwind {
143 ; CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2]
144 ret <2 x i32> < i32 4294959103, i32 4294959103 >
148 define <2 x i32> @vmvn_2xi32c() nounwind {
149 ; CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2]
150 ret <2 x i32> < i32 4292870143, i32 4292870143 >
154 define <2 x i32> @vmvn_2xi32d() nounwind {
155 ; CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2]
156 ret <2 x i32> < i32 3758096383, i32 3758096383 >
160 define <2 x i32> @vmvn_2xi32e() nounwind {
161 ; CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2]
162 ret <2 x i32> < i32 4294958848, i32 4294958848 >
166 define <2 x i32> @vmvn_2xi32f() nounwind {
167 ; CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2]
168 ret <2 x i32> < i32 4292804608, i32 4292804608 >