1 ; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
3 declare <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32>) nounwind readnone
4 declare <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32>) nounwind readnone
7 define <2 x i32> @vrecpe_2xi32(<2 x i32>* %A) nounwind {
8 %tmp1 = load <2 x i32>* %A
9 ; CHECK: vrecpe.u32 d16, d16 @ encoding: [0x20,0x04,0xfb,0xf3]
10 %tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1)
15 define <4 x i32> @vrecpe_4xi32(<4 x i32>* %A) nounwind {
16 %tmp1 = load <4 x i32>* %A
17 ; CHECK: vrecpe.u32 q8, q8 @ encoding: [0x60,0x04,0xfb,0xf3]
18 %tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1)
22 declare <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float>) nounwind readnone
23 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
25 ; CHECK: vrecpe_2xfloat
26 define <2 x float> @vrecpe_2xfloat(<2 x float>* %A) nounwind {
27 %tmp1 = load <2 x float>* %A
28 ; CHECK: vrecpe.f32 d16, d16 @ encoding: [0x20,0x05,0xfb,0xf3]
29 %tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1)
33 ; CHECK: vrecpe_4xfloat
34 define <4 x float> @vrecpe_4xfloat(<4 x float>* %A) nounwind {
35 %tmp1 = load <4 x float>* %A
36 ; CHECK: vrecpe.f32 q8, q8 @ encoding: [0x60,0x05,0xfb,0xf3]
37 %tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
41 declare <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float>, <2 x float>) nounwind readnone
42 declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
44 ; CHECK: vrecps_2xfloat
45 define <2 x float> @vrecps_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
46 %tmp1 = load <2 x float>* %A
47 %tmp2 = load <2 x float>* %B
48 ; CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x40,0xf2]
49 %tmp3 = call <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
53 ; CHECK: vrecps_4xfloat
54 define <4 x float> @vrecps_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind {
55 %tmp1 = load <4 x float>* %A
56 %tmp2 = load <4 x float>* %B
57 ; CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x40,0xf2]
58 %tmp3 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
62 declare <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32>) nounwind readnone
63 declare <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32>) nounwind readnone
65 ; CHECK: vrsqrte_2xi32
66 define <2 x i32> @vrsqrte_2xi32(<2 x i32>* %A) nounwind {
67 %tmp1 = load <2 x i32>* %A
68 ; CHECK: vrsqrte.u32 d16, d16 @ encoding: [0xa0,0x04,0xfb,0xf3]
69 %tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
73 ; CHECK: vrsqrte_4xi32
74 define <4 x i32> @vrsqrte_4xi32(<4 x i32>* %A) nounwind {
75 %tmp1 = load <4 x i32>* %A
76 ; CHECK: vrsqrte.u32 q8, q8 @ encoding: [0xe0,0x04,0xfb,0xf3]
77 %tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
81 declare <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float>) nounwind readnone
82 declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
84 ; CHECK: vrsqrte_2xfloat
85 define <2 x float> @vrsqrte_2xfloat(<2 x float>* %A) nounwind {
86 %tmp1 = load <2 x float>* %A
87 ; CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xa0,0x05,0xfb,0xf3]
88 %tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1)
92 ; CHECK: vrsqrte_4xfloat
93 define <4 x float> @vrsqrte_4xfloat(<4 x float>* %A) nounwind {
94 %tmp1 = load <4 x float>* %A
95 ; CHECK: vrsqrte.f32 q8, q8 @ encoding: [0xe0,0x05,0xfb,0xf3]
96 %tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
100 declare <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float>, <2 x float>) nounwind readnone
101 declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
103 ; CHECK: vrsqrts_2xfloat
104 define <2 x float> @vrsqrts_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
105 %tmp1 = load <2 x float>* %A
106 %tmp2 = load <2 x float>* %B
107 ; CHECK: vrsqrts.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x60,0xf2]
108 %tmp3 = call <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
109 ret <2 x float> %tmp3
112 ; CHECK: vrsqrts_4xfloat
113 define <4 x float> @vrsqrts_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind {
114 %tmp1 = load <4 x float>* %A
115 %tmp2 = load <4 x float>* %B
116 ; CHECK: vrsqrts.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x60,0xf2]
117 %tmp3 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
118 ret <4 x float> %tmp3