Mark ARM subtarget features that are available for the assembler.
[oota-llvm.git] / test / MC / ARM / neon-reciprocal-encoding.s
1 // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
2
3 // CHECK: vrecpe.u32    d16, d16        @ encoding: [0x20,0x04,0xfb,0xf3]
4         vrecpe.u32      d16, d16
5 // CHECK: vrecpe.u32    q8, q8          @ encoding: [0x60,0x04,0xfb,0xf3]
6         vrecpe.u32      q8, q8
7 // CHECK: vrecpe.f32    d16, d16        @ encoding: [0x20,0x05,0xfb,0xf3]
8         vrecpe.f32      d16, d16
9 // CHECK: vrecpe.f32    q8, q8          @ encoding: [0x60,0x05,0xfb,0xf3]
10         vrecpe.f32      q8, q8
11 // CHECK: vrecps.f32    d16, d16, d17   @ encoding: [0xb1,0x0f,0x40,0xf2]
12         vrecps.f32      d16, d16, d17
13 // CHECK: vrecps.f32    q8, q8, q9      @ encoding: [0xf2,0x0f,0x40,0xf2]
14         vrecps.f32      q8, q8, q9
15 // CHECK: vrsqrte.u32   d16, d16        @ encoding: [0xa0,0x04,0xfb,0xf3]
16         vrsqrte.u32     d16, d16
17 // CHECK: vrsqrte.u32   q8, q8          @ encoding: [0xe0,0x04,0xfb,0xf3]
18         vrsqrte.u32     q8, q8
19 // CHECK: vrsqrte.f32   d16, d16        @ encoding: [0xa0,0x05,0xfb,0xf3]
20         vrsqrte.f32     d16, d16
21 // CHECK: vrsqrte.f32   q8, q8          @ encoding: [0xe0,0x05,0xfb,0xf3]
22         vrsqrte.f32     q8, q8
23 // CHECK: vrsqrts.f32   d16, d16, d17   @ encoding: [0xb1,0x0f,0x60,0xf2]
24         vrsqrts.f32     d16, d16, d17
25 // CHECK: vrsqrts.f32   q8, q8, q9      @ encoding: [0xf2,0x0f,0x60,0xf2]
26         vrsqrts.f32     q8, q8, q9