1 ; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
4 define <8 x i8> @vsub_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
5 %tmp1 = load <8 x i8>* %A
6 %tmp2 = load <8 x i8>* %B
7 ; CHECK: vsub.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xf3]
8 %tmp3 = sub <8 x i8> %tmp1, %tmp2
13 define <4 x i16> @vsub_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
14 %tmp1 = load <4 x i16>* %A
15 %tmp2 = load <4 x i16>* %B
16 ; CHECK: vsub.i16 d16, d17, d16 @ encoding: [0xa0,0x08,0x51,0xf3]
17 %tmp3 = sub <4 x i16> %tmp1, %tmp2
22 define <2 x i32> @vsub_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
23 %tmp1 = load <2 x i32>* %A
24 ; CHECK: vsub.i32 d16, d17, d16 @ encoding: [0xa0,0x08,0x61,0xf3]
25 %tmp2 = load <2 x i32>* %B
26 %tmp3 = sub <2 x i32> %tmp1, %tmp2
31 define <1 x i64> @vsub_1xi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
32 %tmp1 = load <1 x i64>* %A
33 %tmp2 = load <1 x i64>* %B
34 ; CHECK: vsub.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xf3]
35 %tmp3 = sub <1 x i64> %tmp1, %tmp2
39 ; CHECK: vsub_2xifloat
40 define <2 x float> @vsub_2xifloat(<2 x float>* %A, <2 x float>* %B) nounwind {
41 %tmp1 = load <2 x float>* %A
42 %tmp2 = load <2 x float>* %B
43 ; CHECK: vsub.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x60,0xf2]
44 %tmp3 = fsub <2 x float> %tmp1, %tmp2
49 define <16 x i8> @vsub_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
50 %tmp1 = load <16 x i8>* %A
51 %tmp2 = load <16 x i8>* %B
52 ; CHECK: vsub.i8 q8, q8, q9 @ encoding: [0xe2,0x08,0x40,0xf3]
53 %tmp3 = sub <16 x i8> %tmp1, %tmp2
58 define <8 x i16> @vsub_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
59 %tmp1 = load <8 x i16>* %A
60 %tmp2 = load <8 x i16>* %B
61 ; CHECK: vsub.i16 q8, q8, q9 @ encoding: [0xe2,0x08,0x50,0xf3]
62 %tmp3 = sub <8 x i16> %tmp1, %tmp2
67 define <4 x i32> @vsub_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
68 %tmp1 = load <4 x i32>* %A
69 %tmp2 = load <4 x i32>* %B
70 ; CHECK: vsub.i32 q8, q8, q9 @ encoding: [0xe2,0x08,0x60,0xf3]
71 %tmp3 = sub <4 x i32> %tmp1, %tmp2
76 define <2 x i64> @vsub_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
77 %tmp1 = load <2 x i64>* %A
78 %tmp2 = load <2 x i64>* %B
79 ; CHECK: vsub.i64 q8, q8, q9 @ encoding: [0xe2,0x08,0x70,0xf3]
80 %tmp3 = sub <2 x i64> %tmp1, %tmp2
85 define <4 x float> @vsub_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind {
86 %tmp1 = load <4 x float>* %A
87 %tmp2 = load <4 x float>* %B
88 ; CHECK: vsub.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x60,0xf2]
89 %tmp3 = fsub <4 x float> %tmp1, %tmp2
94 define <8 x i16> @vsubls_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
95 %tmp1 = load <8 x i8>* %A
96 %tmp2 = load <8 x i8>* %B
97 %tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
98 %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
99 ; CHECK: vsubl.s8 q8, d17, d16 @ encoding: [0xa0,0x02,0xc1,0xf2]
100 %tmp5 = sub <8 x i16> %tmp3, %tmp4
104 ; CHECK: vsubls_4xi16
105 define <4 x i32> @vsubls_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
106 %tmp1 = load <4 x i16>* %A
107 %tmp2 = load <4 x i16>* %B
108 %tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
109 %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
110 ; CHECK: vsubl.s16 q8, d17, d16 @ encoding: [0xa0,0x02,0xd1,0xf2]
111 %tmp5 = sub <4 x i32> %tmp3, %tmp4
115 ; CHECK: vsubls_2xi32
116 define <2 x i64> @vsubls_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
117 %tmp1 = load <2 x i32>* %A
118 %tmp2 = load <2 x i32>* %B
119 %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
120 %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
121 ; CHECK: vsubl.s32 q8, d17, d16 @ encoding: [0xa0,0x02,0xe1,0xf2]
122 %tmp5 = sub <2 x i64> %tmp3, %tmp4
127 define <8 x i16> @vsublu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
128 %tmp1 = load <8 x i8>* %A
129 %tmp2 = load <8 x i8>* %B
130 %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
131 %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
132 ; CHECK: vsubl.u8 q8, d17, d16 @ encoding: [0xa0,0x02,0xc1,0xf3]
133 %tmp5 = sub <8 x i16> %tmp3, %tmp4
137 ; CHECK: vsublu_4xi16
138 define <4 x i32> @vsublu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
139 %tmp1 = load <4 x i16>* %A
140 %tmp2 = load <4 x i16>* %B
141 %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
142 %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
143 ; CHECK: vsubl.u16 q8, d17, d16 @ encoding: [0xa0,0x02,0xd1,0xf3]
144 %tmp5 = sub <4 x i32> %tmp3, %tmp4
148 ; CHECK: vsublu_2xi32
149 define <2 x i64> @vsublu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
150 %tmp1 = load <2 x i32>* %A
151 %tmp2 = load <2 x i32>* %B
152 %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
153 %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
154 ; CHECK: vsubl.u32 q8, d17, d16 @ encoding: [0xa0,0x02,0xe1,0xf3]
155 %tmp5 = sub <2 x i64> %tmp3, %tmp4
160 define <8 x i16> @vsubws_8xi8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
161 %tmp1 = load <8 x i16>* %A
162 %tmp2 = load <8 x i8>* %B
163 %tmp3 = sext <8 x i8> %tmp2 to <8 x i16>
164 ; CHECK: vsubw.s8 q8, q8, d18 @ encoding: [0xa2,0x03,0xc0,0xf2]
165 %tmp4 = sub <8 x i16> %tmp1, %tmp3
169 ; CHECK: vsubws_4xi16
170 define <4 x i32> @vsubws_4xi16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
171 %tmp1 = load <4 x i32>* %A
172 %tmp2 = load <4 x i16>* %B
173 %tmp3 = sext <4 x i16> %tmp2 to <4 x i32>
174 ; CHECK: vsubw.s16 q8, q8, d18 @ encoding: [0xa2,0x03,0xd0,0xf2]
175 %tmp4 = sub <4 x i32> %tmp1, %tmp3
179 ; CHECK: vsubws_2xi32
180 define <2 x i64> @vsubws_2xi32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
181 %tmp1 = load <2 x i64>* %A
182 %tmp2 = load <2 x i32>* %B
183 %tmp3 = sext <2 x i32> %tmp2 to <2 x i64>
184 ; CHECK: vsubw.s32 q8, q8, d18 @ encoding: [0xa2,0x03,0xe0,0xf2]
185 %tmp4 = sub <2 x i64> %tmp1, %tmp3
190 define <8 x i16> @vsubwu_8xi8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
191 %tmp1 = load <8 x i16>* %A
192 %tmp2 = load <8 x i8>* %B
193 %tmp3 = zext <8 x i8> %tmp2 to <8 x i16>
194 ; CHECK: vsubw.u8 q8, q8, d18 @ encoding: [0xa2,0x03,0xc0,0xf3]
195 %tmp4 = sub <8 x i16> %tmp1, %tmp3
199 ; CHECK: vsubwu_4xi16
200 define <4 x i32> @vsubwu_4xi16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
201 %tmp1 = load <4 x i32>* %A
202 %tmp2 = load <4 x i16>* %B
203 %tmp3 = zext <4 x i16> %tmp2 to <4 x i32>
204 ; CHECK: vsubw.u16 q8, q8, d18 @ encoding: [0xa2,0x03,0xd0,0xf3]
205 %tmp4 = sub <4 x i32> %tmp1, %tmp3
209 ; CHECK: vsubwu_2xi32
210 define <2 x i64> @vsubwu_2xi32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
211 %tmp1 = load <2 x i64>* %A
212 %tmp2 = load <2 x i32>* %B
213 %tmp3 = zext <2 x i32> %tmp2 to <2 x i64>
214 ; CHECK: vsubw.u32 q8, q8, d18 @ encoding: [0xa2,0x03,0xe0,0xf3]
215 %tmp4 = sub <2 x i64> %tmp1, %tmp3
219 declare <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
220 declare <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
221 declare <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
224 define <8 x i8> @vhsubs_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
225 %tmp1 = load <8 x i8>* %A
226 %tmp2 = load <8 x i8>* %B
227 ; CHECK: vhsub.s8 d16, d16, d17 @ encoding: [0xa1,0x02,0x40,0xf2]
228 %tmp3 = call <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
232 ; CHECK: vhsubs_4xi16
233 define <4 x i16> @vhsubs_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
234 %tmp1 = load <4 x i16>* %A
235 %tmp2 = load <4 x i16>* %B
236 ; CHECK: vhsub.s16 d16, d16, d17 @ encoding: [0xa1,0x02,0x50,0xf2]
237 %tmp3 = call <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
241 ; CHECK: vhsubs_2xi32
242 define <2 x i32> @vhsubs_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
243 %tmp1 = load <2 x i32>* %A
244 %tmp2 = load <2 x i32>* %B
245 ; CHECK: vhsub.s32 d16, d16, d17 @ encoding: [0xa1,0x02,0x60,0xf2]
246 %tmp3 = call <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
250 declare <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
251 declare <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
252 declare <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
255 define <8 x i8> @vhsubu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
256 %tmp1 = load <8 x i8>* %A
257 %tmp2 = load <8 x i8>* %B
258 ; CHECK: vhsub.u8 d16, d16, d17 @ encoding: [0xa1,0x02,0x40,0xf3]
259 %tmp3 = call <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
263 ; CHECK: vhsubu_4xi16
264 define <4 x i16> @vhsubu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
265 %tmp1 = load <4 x i16>* %A
266 %tmp2 = load <4 x i16>* %B
267 ; CHECK: vhsub.u16 d16, d16, d17 @ encoding: [0xa1,0x02,0x50,0xf3]
268 %tmp3 = call <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
272 ; CHECK: vhsubu_2xi32
273 define <2 x i32> @vhsubu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
274 %tmp1 = load <2 x i32>* %A
275 %tmp2 = load <2 x i32>* %B
276 ; CHECK: vhsub.u32 d16, d16, d17 @ encoding: [0xa1,0x02,0x60,0xf3]
277 %tmp3 = call <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
281 declare <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
282 declare <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
283 declare <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
285 ; CHECK: vhsubs_16xi8
286 define <16 x i8> @vhsubs_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
287 %tmp1 = load <16 x i8>* %A
288 %tmp2 = load <16 x i8>* %B
289 ; CHECK: vhsub.s8 q8, q8, q9 @ encoding: [0xe2,0x02,0x40,0xf2]
290 %tmp3 = call <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
294 ; CHECK: vhsubs_8xi16
295 define <8 x i16> @vhsubs_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
296 %tmp1 = load <8 x i16>* %A
297 %tmp2 = load <8 x i16>* %B
298 ; CHECK: vhsub.s16 q8, q8, q9 @ encoding: [0xe2,0x02,0x50,0xf2]
299 %tmp3 = call <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
303 ; CHECK: vhsubs_4xi32
304 define <4 x i32> @vhsubs_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
305 %tmp1 = load <4 x i32>* %A
306 %tmp2 = load <4 x i32>* %B
307 ; CHECK: vhsub.s32 q8, q8, q9 @ encoding: [0xe2,0x02,0x60,0xf2]
308 %tmp3 = call <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
312 declare <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
313 declare <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
314 declare <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
315 declare <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
318 define <8 x i8> @vqsubs_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
319 %tmp1 = load <8 x i8>* %A
320 %tmp2 = load <8 x i8>* %B
321 ; CHECK: vqsub.s8 d16, d16, d17 @ encoding: [0xb1,0x02,0x40,0xf2]
322 %tmp3 = call <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
326 ; CHECK: vqsubs_4xi16
327 define <4 x i16> @vqsubs_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
328 %tmp1 = load <4 x i16>* %A
329 %tmp2 = load <4 x i16>* %B
330 ; CHECK: vqsub.s16 d16, d16, d17 @ encoding: [0xb1,0x02,0x50,0xf2]
331 %tmp3 = call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
335 ; CHECK: vqsubs_2xi32
336 define <2 x i32> @vqsubs_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
337 %tmp1 = load <2 x i32>* %A
338 %tmp2 = load <2 x i32>* %B
339 ; CHECK: vqsub.s32 d16, d16, d17 @ encoding: [0xb1,0x02,0x60,0xf2]
340 %tmp3 = call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
344 ; CHECK: vqsubs_1xi64
345 define <1 x i64> @vqsubs_1xi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
346 %tmp1 = load <1 x i64>* %A
347 %tmp2 = load <1 x i64>* %B
348 ; CHECK: vqsub.s64 d16, d16, d17 @ encoding: [0xb1,0x02,0x70,0xf2]
349 %tmp3 = call <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
353 declare <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
354 declare <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
355 declare <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
356 declare <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
359 define <8 x i8> @vqsubu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
360 %tmp1 = load <8 x i8>* %A
361 %tmp2 = load <8 x i8>* %B
362 ; CHECK: vqsub.u8 d16, d16, d17 @ encoding: [0xb1,0x02,0x40,0xf3]
363 %tmp3 = call <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
367 ; CHECK: vqsubu_4xi16
368 define <4 x i16> @vqsubu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
369 %tmp1 = load <4 x i16>* %A
370 %tmp2 = load <4 x i16>* %B
371 ; CHECK: vqsub.u16 d16, d16, d17 @ encoding: [0xb1,0x02,0x50,0xf3]
372 %tmp3 = call <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
376 ; CHECK: vqsubu_2xi32
377 define <2 x i32> @vqsubu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
378 %tmp1 = load <2 x i32>* %A
379 %tmp2 = load <2 x i32>* %B
380 ; CHECK: vqsub.u32 d16, d16, d17 @ encoding: [0xb1,0x02,0x60,0xf3]
381 %tmp3 = call <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
385 ; CHECK: vqsubu_1xi64
386 define <1 x i64> @vqsubu_1xi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
387 %tmp1 = load <1 x i64>* %A
388 %tmp2 = load <1 x i64>* %B
389 ; CHECK: vqsub.u64 d16, d16, d17 @ encoding: [0xb1,0x02,0x70,0xf3]
390 %tmp3 = call <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
394 declare <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
395 declare <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
396 declare <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
397 declare <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
399 ; CHECK: vqsubs_16xi8
400 define <16 x i8> @vqsubs_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
401 %tmp1 = load <16 x i8>* %A
402 %tmp2 = load <16 x i8>* %B
403 ; CHECK: vqsub.s8 q8, q8, q9 @ encoding: [0xf2,0x02,0x40,0xf2]
404 %tmp3 = call <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
408 ; CHECK: vqsubs_8xi16
409 define <8 x i16> @vqsubs_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
410 %tmp1 = load <8 x i16>* %A
411 %tmp2 = load <8 x i16>* %B
412 ; CHECK: vqsub.s16 q8, q8, q9 @ encoding: [0xf2,0x02,0x50,0xf2]
413 %tmp3 = call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
417 ; CHECK: vqsubs_4xi32
418 define <4 x i32> @vqsubs_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
419 %tmp1 = load <4 x i32>* %A
420 %tmp2 = load <4 x i32>* %B
421 ; CHECK: vqsub.s32 q8, q8, q9 @ encoding: [0xf2,0x02,0x60,0xf2]
422 %tmp3 = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
426 ; CHECK: vqsubs_2xi64
427 define <2 x i64> @vqsubs_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
428 %tmp1 = load <2 x i64>* %A
429 %tmp2 = load <2 x i64>* %B
430 ; CHECK: vqsub.s64 q8, q8, q9 @ encoding: [0xf2,0x02,0x70,0xf2]
431 %tmp3 = call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
435 declare <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
436 declare <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
437 declare <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
438 declare <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
440 ; CHECK: vqsubu_16xi8
441 define <16 x i8> @vqsubu_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
442 %tmp1 = load <16 x i8>* %A
443 %tmp2 = load <16 x i8>* %B
444 ; CHECK: vqsub.u8 q8, q8, q9 @ encoding: [0xf2,0x02,0x40,0xf3]
445 %tmp3 = call <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
449 ; CHECK: vqsubu_8xi16
450 define <8 x i16> @vqsubu_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
451 %tmp1 = load <8 x i16>* %A
452 %tmp2 = load <8 x i16>* %B
453 ; CHECK: vqsub.u16 q8, q8, q9 @ encoding: [0xf2,0x02,0x50,0xf3]
454 %tmp3 = call <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
458 ; CHECK: vqsubu_4xi32
459 define <4 x i32> @vqsubu_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
460 %tmp1 = load <4 x i32>* %A
461 %tmp2 = load <4 x i32>* %B
462 ; CHECK: vqsub.u32 q8, q8, q9 @ encoding: [0xf2,0x02,0x60,0xf3]
463 %tmp3 = call <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
467 ; CHECK: vqsubu_2xi64
468 define <2 x i64> @vqsubu_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
469 %tmp1 = load <2 x i64>* %A
470 %tmp2 = load <2 x i64>* %B
471 ; CHECK: vqsub.u64 q8, q8, q9 @ encoding: [0xf2,0x02,0x70,0xf3]
472 %tmp3 = call <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
476 declare <8 x i8> @llvm.arm.neon.vsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
477 declare <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
478 declare <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
480 ; CHECK: vsubhn_8xi16
481 define <8 x i8> @vsubhn_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
482 %tmp1 = load <8 x i16>* %A
483 %tmp2 = load <8 x i16>* %B
484 ; CHECK: vsubhn.i16 d16, q8, q9 @ encoding: [0xa2,0x06,0xc0,0xf2]
485 %tmp3 = call <8 x i8> @llvm.arm.neon.vsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
489 ; CHECK: vsubhn_4xi32
490 define <4 x i16> @vsubhn_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
491 %tmp1 = load <4 x i32>* %A
492 %tmp2 = load <4 x i32>* %B
493 ; CHECK: vsubhn.i32 d16, q8, q9 @ encoding: [0xa2,0x06,0xd0,0xf2]
494 %tmp3 = call <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
498 ; CHECK: vsubhn_2xi64
499 define <2 x i32> @vsubhn_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
500 %tmp1 = load <2 x i64>* %A
501 %tmp2 = load <2 x i64>* %B
502 ; CHECK: vsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf2]
503 %tmp3 = call <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
507 declare <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
508 declare <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
509 declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
511 ; CHECK: vrsubhn_8xi16
512 define <8 x i8> @vrsubhn_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
513 %tmp1 = load <8 x i16>* %A
514 %tmp2 = load <8 x i16>* %B
515 ; CHECK: vrsubhn.i16 d16, q8, q9 @ encoding: [0xa2,0x06,0xc0,0xf3]
516 %tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
520 ; CHECK: vrsubhn_4xi32
521 define <4 x i16> @vrsubhn_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
522 %tmp1 = load <4 x i32>* %A
523 %tmp2 = load <4 x i32>* %B
524 ; CHECK: vrsubhn.i32 d16, q8, q9 @ encoding: [0xa2,0x06,0xd0,0xf3]
525 %tmp3 = call <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
529 ; CHECK: vrsubhn_2xi64
530 define <2 x i32> @vrsubhn_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
531 %tmp1 = load <2 x i64>* %A
532 %tmp2 = load <2 x i64>* %B
533 ; CHECK: vrsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf3]
534 %tmp3 = call <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)