ARM vmul assembly parsing for the lane index operand.
[oota-llvm.git] / test / MC / ARM / neont2-mul-encoding.s
1 @ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
2
3 .code 16
4
5 @ CHECK: vmul.i8        d16, d16, d17           @ encoding: [0x40,0xef,0xb1,0x09]
6         vmul.i8 d16, d16, d17
7 @ CHECK: vmul.i16       d16, d16, d17   @ encoding: [0x50,0xef,0xb1,0x09]
8         vmul.i16        d16, d16, d17
9 @ CHECK: vmul.i32       d16, d16, d17   @ encoding: [0x60,0xef,0xb1,0x09]
10         vmul.i32        d16, d16, d17
11 @ CHECK: vmul.f32       d16, d16, d17   @ encoding: [0x40,0xff,0xb1,0x0d]
12         vmul.f32        d16, d16, d17
13 @ CHECK: vmul.i8        q8, q8, q9              @ encoding: [0x40,0xef,0xf2,0x09]
14         vmul.i8 q8, q8, q9
15 @ CHECK: vmul.i16       q8, q8, q9      @ encoding: [0x50,0xef,0xf2,0x09]
16         vmul.i16        q8, q8, q9
17 @ CHECK: vmul.i32       q8, q8, q9      @ encoding: [0x60,0xef,0xf2,0x09]
18         vmul.i32        q8, q8, q9
19 @ CHECK: vmul.f32       q8, q8, q9      @ encoding: [0x40,0xff,0xf2,0x0d]
20         vmul.f32        q8, q8, q9
21 @ CHECK: vmul.p8        d16, d16, d17           @ encoding: [0x40,0xff,0xb1,0x09]
22         vmul.p8 d16, d16, d17
23 @ CHECK: vmul.p8        q8, q8, q9              @ encoding: [0x40,0xff,0xf2,0x09]
24         vmul.p8 q8, q8, q9
25
26         vmul.i16        d18, d8, d0[3]
27 @ CHECK: vmul.i16       d18, d8, d0[3]    @ encoding: [0xd8,0xef,0x68,0x28]
28
29 @ CHECK: vqdmulh.s16    d16, d16, d17   @ encoding: [0x50,0xef,0xa1,0x0b]
30         vqdmulh.s16     d16, d16, d17
31 @ CHECK: vqdmulh.s32    d16, d16, d17   @ encoding: [0x60,0xef,0xa1,0x0b]
32         vqdmulh.s32     d16, d16, d17
33 @ CHECK: vqdmulh.s16    q8, q8, q9      @ encoding: [0x50,0xef,0xe2,0x0b]
34         vqdmulh.s16     q8, q8, q9
35 @ CHECK: vqdmulh.s32    q8, q8, q9      @ encoding: [0x60,0xef,0xe2,0x0b]
36         vqdmulh.s32     q8, q8, q9
37 @ CHECK: vqrdmulh.s16   d16, d16, d17   @ encoding: [0x50,0xff,0xa1,0x0b]
38         vqrdmulh.s16    d16, d16, d17
39 @ CHECK: vqrdmulh.s32   d16, d16, d17   @ encoding: [0x60,0xff,0xa1,0x0b]
40         vqrdmulh.s32    d16, d16, d17
41 @ CHECK: vqrdmulh.s16   q8, q8, q9      @ encoding: [0x50,0xff,0xe2,0x0b]
42         vqrdmulh.s16    q8, q8, q9
43 @ CHECK: vqrdmulh.s32   q8, q8, q9      @ encoding: [0x60,0xff,0xe2,0x0b]
44         vqrdmulh.s32    q8, q8, q9
45 @ CHECK: vmull.s8       q8, d16, d17    @ encoding: [0xc0,0xef,0xa1,0x0c]
46         vmull.s8        q8, d16, d17
47 @ CHECK: vmull.s16      q8, d16, d17    @ encoding: [0xd0,0xef,0xa1,0x0c]
48         vmull.s16       q8, d16, d17
49 @ CHECK: vmull.s32      q8, d16, d17    @ encoding: [0xe0,0xef,0xa1,0x0c]
50         vmull.s32       q8, d16, d17
51 @ CHECK: vmull.u8       q8, d16, d17    @ encoding: [0xc0,0xff,0xa1,0x0c]
52         vmull.u8        q8, d16, d17
53 @ CHECK: vmull.u16      q8, d16, d17    @ encoding: [0xd0,0xff,0xa1,0x0c]
54         vmull.u16       q8, d16, d17
55 @ CHECK: vmull.u32      q8, d16, d17    @ encoding: [0xe0,0xff,0xa1,0x0c]
56         vmull.u32       q8, d16, d17
57 @ CHECK: vmull.p8       q8, d16, d17    @ encoding: [0xc0,0xef,0xa1,0x0e]
58         vmull.p8        q8, d16, d17
59 @ CHECK: vqdmull.s16    q8, d16, d17    @ encoding: [0xd0,0xef,0xa1,0x0d]
60         vqdmull.s16     q8, d16, d17
61 @ CHECK: vqdmull.s32    q8, d16, d17    @ encoding: [0xe0,0xef,0xa1,0x0d]
62         vqdmull.s32     q8, d16, d17
63
64 @       vmla.i32        q12, q8, d3[0]
65 @       vqdmulh.s16     d11, d2, d3[0]
66 @ FIXME: vmla.i32       q12, q8, d3[0]    @ encoding: [0xe0,0xff,0xc3,0x80]
67 @ FIXME: vqdmulh.s16    d11, d2, d3[0]    @ encoding: [0x92,0xef,0x43,0xbc]