1 ;RUN: llc -mtriple=armv7-apple-darwin -mcpu=cortex-a8 -mattr=-neonfp -show-mc-encoding < %s | FileCheck %s
4 ; FIXME: Once the ARM integrated assembler is up and going, these sorts of tests
5 ; should run on .s source files rather than using llc to generate the
9 define double @f1(double %a, double %b) nounwind readnone {
12 ; CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee]
13 %add = fadd double %a, %b
17 define float @f2(float %a, float %b) nounwind readnone {
20 ; CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee]
21 %add = fadd float %a, %b
25 define double @f3(double %a, double %b) nounwind readnone {
28 ; CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee]
29 %sub = fsub double %a, %b
33 define float @f4(float %a, float %b) nounwind readnone {
36 ; CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee]
37 %sub = fsub float %a, %b
41 define double @f5(double %a, double %b) nounwind readnone {
44 ; CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee]
45 %div = fdiv double %a, %b
49 define float @f6(float %a, float %b) nounwind readnone {
52 ; CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee]
53 %div = fdiv float %a, %b
57 define double @f7(double %a, double %b) nounwind readnone {
60 ; CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee]
61 %mul = fmul double %a, %b
65 define float @f8(float %a, float %b) nounwind readnone {
68 ; CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee]
69 %mul = fmul float %a, %b
73 define double @f9(double %a, double %b) nounwind readnone {
76 ; CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee]
77 %mul = fmul double %a, %b
78 %sub = fsub double -0.000000e+00, %mul
82 define void @f10(float %a, float %b, float* %c) nounwind readnone {
85 ; CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee]
86 %mul = fmul float %a, %b
87 %sub = fsub float -0.000000e+00, %mul
88 store float %sub, float* %c, align 4
92 define i1 @f11(double %a, double %b) nounwind readnone {
95 ; CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee]
96 %cmp = fcmp oeq double %a, %b
100 define i1 @f12(float %a, float %b) nounwind readnone {
103 ; CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee]
104 %cmp = fcmp oeq float %a, %b
108 define i1 @f13(double %a) nounwind readnone {
111 ; CHECK: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee]
112 %cmp = fcmp oeq double %a, 0.000000e+00
116 define i1 @f14(float %a) nounwind readnone {
119 ; CHECK: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee]
120 %cmp = fcmp oeq float %a, 0.000000e+00
124 define double @f15(double %a) nounwind {
127 ; CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee]
128 %call = tail call double @fabsl(double %a)
132 declare double @fabsl(double)
134 define float @f16(float %a) nounwind {
137 ; This call generates a "bfc" instruction instead of "vabs.f32".
138 %call = tail call float @fabsf(float %a)
142 declare float @fabsf(float)
144 define float @f17(double %a) nounwind readnone {
147 ; CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee]
148 %conv = fptrunc double %a to float
152 define double @f18(float %a) nounwind readnone {
155 ; CHECK: vcvt.f64.f32 d16, s0 @ encoding: [0xc0,0x0a,0xf7,0xee]
156 %conv = fpext float %a to double