1 # RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s
3 # None of these instructions should be classified as unpredictable:
5 # CHECK-NOT: potentially undefined instruction encoding
7 # Stores from duplicated registers should be fine.
9 # CHECK: stp x3, x3, [sp], #0
11 # d5 != x5 so "ldp d5, d6, [x5], #24" is fine.
13 # CHECK: ldp d5, d6, [x5], #24
15 # xzr != sp so "stp xzr, xzr, [sp], #8" is fine.
17 # CHECK: stp xzr, xzr, [sp], #8