Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more...
[oota-llvm.git] / test / MC / Disassembler / ARM / thumb1.txt
1 # RUN: llvm-mc -triple=thumbv6-apple-darwin -disassemble < %s | FileCheck %s
2
3 #------------------------------------------------------------------------------
4 # ADC (register)
5 #------------------------------------------------------------------------------
6 # CHECK: adcs r4, r6
7
8 0x74 0x41
9
10
11 #------------------------------------------------------------------------------
12 # ADD (immediate)
13 #------------------------------------------------------------------------------
14 # CHECK: adds r1, r2, #3
15 # CHECK: adds r2, r2, #3
16 # CHECK: adds r2, #8
17
18 0xd1 0x1c
19 0xd2 0x1c
20 0x08 0x32
21
22 #------------------------------------------------------------------------------
23 # ADD (register)
24 #------------------------------------------------------------------------------
25 # CHECK: adds r1, r2, r3
26 # CHECK: add r2, r8
27
28 0xd1 0x18
29 0x42 0x44
30
31 #------------------------------------------------------------------------------
32 # ASR (immediate)
33 #------------------------------------------------------------------------------
34 # CHECK: asrs r2, r3, #32
35 # CHECK: asrs r2, r3, #5
36 # CHECK: asrs r2, r3, #1
37
38 0x1a 0x10
39 0x5a 0x11
40 0x5a 0x10
41
42 #------------------------------------------------------------------------------
43 # ASR (register)
44 #------------------------------------------------------------------------------
45 # CHECK: asrs r5, r2
46
47 0x15 0x41
48
49 #------------------------------------------------------------------------------
50 # BICS
51 #------------------------------------------------------------------------------
52 # CHECK: bics r1, r6
53
54 0xb1 0x43
55
56 #------------------------------------------------------------------------------
57 # BKPT
58 #------------------------------------------------------------------------------
59 # CHECK: bkpt #0
60 # CHECK: bkpt #255
61
62 0x00 0xbe
63 0xff 0xbe
64
65 #------------------------------------------------------------------------------
66 # BLX (register)
67 #------------------------------------------------------------------------------
68 # CHECK: blx r4
69
70 0xa0 0x47
71
72 #------------------------------------------------------------------------------
73 # BX
74 #------------------------------------------------------------------------------
75 # CHECK: bx r2
76
77 0x10 0x47
78
79 #------------------------------------------------------------------------------
80 # CMN
81 #------------------------------------------------------------------------------
82 # CHECK: cmn r5, r1
83
84 0xcd 0x42
85
86 #------------------------------------------------------------------------------
87 # CMP
88 #------------------------------------------------------------------------------
89 # CHECK: cmp r6, #32
90 # CHECK: cmp r3, r4
91 # CHECK: cmp r8, r1
92
93 0x20 0x2e
94 0xa3 0x42
95 0x88 0x45
96
97 #------------------------------------------------------------------------------
98 # EOR
99 #------------------------------------------------------------------------------
100 # CHECK: eors r4, r5
101
102 0x6c 0x40
103
104 #------------------------------------------------------------------------------
105 # LDM
106 #------------------------------------------------------------------------------
107 # CHECK: ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7}
108 # CHECK: ldm r2!, {r1, r3, r4, r5, r7}
109 # CHECK: ldm r1, {r1}
110
111 0xff 0xcb
112 0xba 0xca
113 0x02 0xc9
114
115
116 #------------------------------------------------------------------------------
117 # LDR (immediate)
118 #------------------------------------------------------------------------------
119 # CHECK: ldr r1, [r5]
120 # CHECK: ldr r2, [r6, #32]
121 # CHECK: ldr r3, [r7, #124]
122 # CHECK: ldr r1, [sp]
123 # CHECK: ldr r2, [sp, #24]
124 # CHECK: ldr r3, [sp, #1020]
125
126
127 0x29 0x68
128 0x32 0x6a
129 0xfb 0x6f
130 0x00 0x99
131 0x06 0x9a
132 0xff 0x9b
133