1 # RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
3 #==---------------------------------------------------------------------------==
4 # 5.4.2 Logical (immediate)
5 #==---------------------------------------------------------------------------==
17 # CHECK: and w0, w0, #0x1
18 # CHECK: and x0, x0, #0x1
19 # CHECK: and w1, w2, #0xf
20 # CHECK: and x1, x2, #0xf
21 # CHECK: and sp, x5, #0xfffffffffffffff0
22 # CHECK: ands w0, w0, #0x1
23 # CHECK: ands x0, x0, #0x1
24 # CHECK: ands w1, w2, #0xf
25 # CHECK: ands x1, x2, #0xf
30 # CHECK: eor w1, w2, #0x4000
31 # CHECK: eor x1, x2, #0x8000
36 # CHECK: orr w1, w2, #0x4000
37 # CHECK: orr x1, x2, #0x8000
39 #==---------------------------------------------------------------------------==
40 # 5.5.3 Logical (shifted register)
41 #==---------------------------------------------------------------------------==
54 # CHECK: and w1, w2, w3
55 # CHECK: and x1, x2, x3
56 # CHECK: and w1, w2, w3, lsl #2
57 # CHECK: and x1, x2, x3, lsl #2
58 # CHECK: and w1, w2, w3, lsr #2
59 # CHECK: and x1, x2, x3, lsr #2
60 # CHECK: and w1, w2, w3, asr #2
61 # CHECK: and x1, x2, x3, asr #2
62 # CHECK: and w1, w2, w3, ror #2
63 # CHECK: and x1, x2, x3, ror #2
76 # CHECK: ands w1, w2, w3
77 # CHECK: ands x1, x2, x3
78 # CHECK: ands w1, w2, w3, lsl #2
79 # CHECK: ands x1, x2, x3, lsl #2
80 # CHECK: ands w1, w2, w3, lsr #2
81 # CHECK: ands x1, x2, x3, lsr #2
82 # CHECK: ands w1, w2, w3, asr #2
83 # CHECK: ands x1, x2, x3, asr #2
84 # CHECK: ands w1, w2, w3, ror #2
85 # CHECK: ands x1, x2, x3, ror #2
98 # CHECK: bic w1, w2, w3
99 # CHECK: bic x1, x2, x3
100 # CHECK: bic w1, w2, w3, lsl #3
101 # CHECK: bic x1, x2, x3, lsl #3
102 # CHECK: bic w1, w2, w3, lsr #3
103 # CHECK: bic x1, x2, x3, lsr #3
104 # CHECK: bic w1, w2, w3, asr #3
105 # CHECK: bic x1, x2, x3, asr #3
106 # CHECK: bic w1, w2, w3, ror #3
107 # CHECK: bic x1, x2, x3, ror #3
120 # CHECK: bics w1, w2, w3
121 # CHECK: bics x1, x2, x3
122 # CHECK: bics w1, w2, w3, lsl #3
123 # CHECK: bics x1, x2, x3, lsl #3
124 # CHECK: bics w1, w2, w3, lsr #3
125 # CHECK: bics x1, x2, x3, lsr #3
126 # CHECK: bics w1, w2, w3, asr #3
127 # CHECK: bics x1, x2, x3, asr #3
128 # CHECK: bics w1, w2, w3, ror #3
129 # CHECK: bics x1, x2, x3, ror #3
142 # CHECK: eon w1, w2, w3
143 # CHECK: eon x1, x2, x3
144 # CHECK: eon w1, w2, w3, lsl #4
145 # CHECK: eon x1, x2, x3, lsl #4
146 # CHECK: eon w1, w2, w3, lsr #4
147 # CHECK: eon x1, x2, x3, lsr #4
148 # CHECK: eon w1, w2, w3, asr #4
149 # CHECK: eon x1, x2, x3, asr #4
150 # CHECK: eon w1, w2, w3, ror #4
151 # CHECK: eon x1, x2, x3, ror #4
164 # CHECK: eor w1, w2, w3
165 # CHECK: eor x1, x2, x3
166 # CHECK: eor w1, w2, w3, lsl #5
167 # CHECK: eor x1, x2, x3, lsl #5
168 # CHECK: eor w1, w2, w3, lsr #5
169 # CHECK: eor x1, x2, x3, lsr #5
170 # CHECK: eor w1, w2, w3, asr #5
171 # CHECK: eor x1, x2, x3, asr #5
172 # CHECK: eor w1, w2, w3, ror #5
173 # CHECK: eor x1, x2, x3, ror #5
186 # CHECK: orr w1, w2, w3
187 # CHECK: orr x1, x2, x3
188 # CHECK: orr w1, w2, w3, lsl #6
189 # CHECK: orr x1, x2, x3, lsl #6
190 # CHECK: orr w1, w2, w3, lsr #6
191 # CHECK: orr x1, x2, x3, lsr #6
192 # CHECK: orr w1, w2, w3, asr #6
193 # CHECK: orr x1, x2, x3, asr #6
194 # CHECK: orr w1, w2, w3, ror #6
195 # CHECK: orr x1, x2, x3, ror #6
208 # CHECK: orn w1, w2, w3
209 # CHECK: orn x1, x2, x3
210 # CHECK: orn w1, w2, w3, lsl #7
211 # CHECK: orn x1, x2, x3, lsl #7
212 # CHECK: orn w1, w2, w3, lsr #7
213 # CHECK: orn x1, x2, x3, lsr #7
214 # CHECK: orn w1, w2, w3, asr #7
215 # CHECK: orn x1, x2, x3, asr #7
216 # CHECK: orn w1, w2, w3, ror #7
217 # CHECK: orn x1, x2, x3, ror #7