ARM: Fix pseudo-instructions for SRS (Store Return State).
[oota-llvm.git] / test / MC / Mips / micromips-shift-instructions.s
1 # RUN: llvm-mc %s -triple=mipsel -show-encoding -mcpu=mips32r2 -mattr=micromips | FileCheck %s
2 # Check that the assembler can handle the documented syntax
3 # for shift instructions.
4 #------------------------------------------------------------------------------
5 # Shift Instructions
6 #------------------------------------------------------------------------------
7 # CHECK: sll    $4, $3, 7      # encoding: [0x00,0x38,0x83,0x00]
8 # CHECK: sllv   $2, $3, $5     # encoding: [0x10,0x10,0x65,0x00]
9 # CHECK: sra    $4, $3, 7      # encoding: [0x80,0x38,0x83,0x00]
10 # CHECK: srav   $2, $3, $5     # encoding: [0x90,0x10,0x65,0x00]
11 # CHECK: srl    $4, $3, 7      # encoding: [0x40,0x38,0x83,0x00]
12 # CHECK: srlv   $2, $3, $5     # encoding: [0x50,0x10,0x65,0x00]
13 # CHECK: rotr   $9, $6, 7      # encoding: [0xc0,0x38,0x26,0x01]
14 # CHECK: rotrv  $9, $6, $7     # encoding: [0xd0,0x48,0xc7,0x00]
15      sll    $4, $3, 7
16      sllv   $2, $3, $5
17      sra    $4, $3, 7
18      srav   $2, $3, $5
19      srl    $4, $3, 7
20      srlv   $2, $3, $5
21      rotr   $9, $6, 7
22      rotrv  $9, $6, $7