1 ; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -mattr=n64 %s -o - \
2 ; RUN: | llvm-objdump -disassemble -triple mips64el -mattr +mips64r2 - \
5 define i64 @dext(i64 %i) nounwind readnone {
7 ; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
9 %and = and i64 %shr, 1023
13 define i64 @dextu(i64 %i) nounwind readnone {
15 ; CHECK: dextu ${{[0-9]+}}, ${{[0-9]+}}, 2, 6
16 %shr = lshr i64 %i, 34
17 %and = and i64 %shr, 63
21 define i64 @dextm(i64 %i) nounwind readnone {
23 ; CHECK: dextm ${{[0-9]+}}, ${{[0-9]+}}, 5, 2
25 %and = and i64 %shr, 17179869183
29 define i64 @dins(i64 %i, i64 %j) nounwind readnone {
31 ; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10
33 %and = and i64 %shl2, 261888
34 %and3 = and i64 %i, -261889
35 %or = or i64 %and3, %and
39 define i64 @dinsm(i64 %i, i64 %j) nounwind readnone {
41 ; CHECK: dinsm ${{[0-9]+}}, ${{[0-9]+}}, 10, 1
42 %shl4 = shl i64 %j, 10
43 %and = and i64 %shl4, 8796093021184
44 %and5 = and i64 %i, -8796093021185
45 %or = or i64 %and5, %and
49 define i64 @dinsu(i64 %i, i64 %j) nounwind readnone {
51 ; CHECK: dinsu ${{[0-9]+}}, ${{[0-9]+}}, 8, 13
52 %shl4 = shl i64 %j, 40
53 %and = and i64 %shl4, 9006099743113216
54 %and5 = and i64 %i, -9006099743113217
55 %or = or i64 %and5, %and