1 # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-nacl %s \
2 # RUN: | llvm-objdump -triple mipsel -disassemble -no-show-raw-insn - \
5 # This test tests that address-masking sandboxing is added when given assembly
9 # Test that address-masking sandboxing is added before indirect branches and
23 # CHECK: and $4, $4, $14
26 # Check that additional nop is inserted, to align mask and jr to the next
32 # CHECK: and $ra, $ra, $14
37 # Test that address-masking sandboxing is added before load instructions.
60 # CHECK: and $1, $1, $15
61 # CHECK-NEXT: lb $4, 0($1)
63 # Check that additional nop is inserted, to align mask and load to the next
69 # CHECK: and $2, $2, $15
70 # CHECK-NEXT: lbu $4, 0($2)
72 # CHECK: and $3, $3, $15
73 # CHECK-NEXT: lh $4, 0($3)
75 # CHECK: and $4, $4, $15
76 # CHECK-NEXT: lhu $1, 0($4)
78 # CHECK: and $5, $5, $15
79 # CHECK-NEXT: lw $4, 0($5)
81 # CHECK: and $6, $6, $15
82 # CHECK-NEXT: lwc1 $f0, 0($6)
84 # CHECK: and $7, $7, $15
85 # CHECK-NEXT: ldc1 $f2, 0($7)
87 # CHECK: and $8, $8, $15
88 # CHECK-NEXT: ll $4, 0($8)
90 # CHECK: and $9, $9, $15
91 # CHECK-NEXT: lwl $4, 0($9)
93 # CHECK: and $10, $10, $15
94 # CHECK-NEXT: lwr $4, 0($10)
97 # Check that loads where base register is $sp or $t8 (thread pointer register)
101 # CHECK: lw $4, 0($sp)
103 # CHECK: lw $4, 0($24)
107 # Test that address-masking sandboxing is added before store instructions.
126 # CHECK-LABEL: test3:
128 # CHECK: and $1, $1, $15
129 # CHECK-NEXT: sb $4, 0($1)
131 # Check that additional nop is inserted, to align mask and store to the next
137 # CHECK: and $2, $2, $15
138 # CHECK-NEXT: sh $4, 0($2)
140 # CHECK: and $3, $3, $15
141 # CHECK-NEXT: sw $4, 0($3)
143 # CHECK: and $4, $4, $15
144 # CHECK-NEXT: swc1 $f0, 0($4)
146 # CHECK: and $5, $5, $15
147 # CHECK-NEXT: sdc1 $f2, 0($5)
149 # CHECK: and $6, $6, $15
150 # CHECK-NEXT: swl $4, 0($6)
152 # CHECK: and $7, $7, $15
153 # CHECK-NEXT: swr $4, 0($7)
155 # CHECK: and $8, $8, $15
156 # CHECK-NEXT: sc $4, 0($8)
159 # Check that stores where base register is $sp or $t8 (thread pointer register)
163 # CHECK: sw $4, 0($sp)
165 # CHECK: sw $4, 0($24)
169 # Test that address-masking sandboxing is added after instructions that change
183 # CHECK-LABEL: test4:
185 # CHECK: addiu $sp, $sp, 24
186 # CHECK-NEXT: and $sp, $sp, $15
188 # Check that additional nop is inserted, to align instruction and mask to the
194 # CHECK: addu $sp, $sp, $1
195 # CHECK-NEXT: and $sp, $sp, $15
197 # Since we next check sandboxing sequence which consists of 3 instructions,
198 # check that 2 additional nops are inserted, to align it to the next bundle.
204 # Check that for instructions that change stack-pointer and load from memory
205 # masks are added before and after the instruction.
207 # CHECK: and $2, $2, $15
208 # CHECK-NEXT: lw $sp, 0($2)
209 # CHECK-NEXT: and $sp, $sp, $15
211 # For loads where $sp is destination and base, check that mask is added after
215 # CHECK: lw $sp, 123($sp)
216 # CHECK-NEXT: and $sp, $sp, $15
218 # For stores where $sp is destination and base, check that mask is added neither
222 # CHECK: sw $sp, 123($sp)
227 # Test that call + branch delay is aligned at bundle end. Test that mask is
228 # added before indirect calls.
258 # CHECK-LABEL: test5:
260 # CHECK-NEXT: addiu $4, $zero, 1
265 # CHECK-NEXT: addiu $4, $zero, 2
270 # CHECK-NEXT: addiu $4, $zero, 3
280 # CHECK-NEXT: addiu $4, $zero, 4
283 # CHECK-NEXT: and $25, $25, $14
284 # CHECK-NEXT: jalr $25
285 # CHECK-NEXT: addiu $4, $zero, 5
289 # Test that we can put non-dangerous loads and stores in branch delay slot.
308 # CHECK-LABEL: test6:
310 # CHECK-NEXT: sw $4, 0($sp)
315 # CHECK-NEXT: lw $5, 0($24)
318 # CHECK-NEXT: and $25, $25, $14
320 # CHECK-NEXT: sw $sp, 0($sp)