[mips][microMIPS] Implement LBUX, LHX, LWX, MAQ_S[A].W.PHL, MAQ_S[A].W.PHR, MFHI...
[oota-llvm.git] / test / MC / Mips / rotations32.s
1 # RUN: llvm-mc  %s -arch=mips -mcpu=mips32 -show-encoding | FileCheck %s -check-prefix=CHECK-32
2 # RUN: llvm-mc  %s -arch=mips -mcpu=mips32r2 -show-encoding | FileCheck %s -check-prefix=CHECK-32R
3 # RUN: llvm-mc  %s -arch=mips -mcpu=mips32r3 -show-encoding | FileCheck %s -check-prefix=CHECK-32R
4 # RUN: llvm-mc  %s -arch=mips -mcpu=mips32r5 -show-encoding | FileCheck %s -check-prefix=CHECK-32R
5 # RUN: llvm-mc  %s -arch=mips -mcpu=mips32r6 -show-encoding | FileCheck %s -check-prefix=CHECK-32R
6
7   .text
8 foo:
9   rol $4,$5
10 # CHECK-32:     negu    $1, $5              # encoding: [0x00,0x05,0x08,0x23]
11 # CHECK-32:     srlv    $1, $4, $1          # encoding: [0x00,0x24,0x08,0x06]
12 # CHECK-32:     sllv    $4, $4, $5          # encoding: [0x00,0xa4,0x20,0x04]
13 # CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
14 # CHECK-32R:    negu    $1, $5              # encoding: [0x00,0x05,0x08,0x23]
15 # CHECK-32R:    rotrv   $4, $4, $1          # encoding: [0x00,0x24,0x20,0x46]
16   rol $4,$5,$6
17 # CHECK-32:     negu    $1, $6              # encoding: [0x00,0x06,0x08,0x23]
18 # CHECK-32:     srlv    $1, $5, $1          # encoding: [0x00,0x25,0x08,0x06]
19 # CHECK-32:     sllv    $4, $5, $6          # encoding: [0x00,0xc5,0x20,0x04]
20 # CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
21 # CHECK-32R:    negu    $4, $6              # encoding: [0x00,0x06,0x20,0x23]
22 # CHECK-32R:    rotrv   $4, $5, $4          # encoding: [0x00,0x85,0x20,0x46]
23   rol $4,0
24 # CHECK-32:     srl     $4, $4, 0           # encoding: [0x00,0x04,0x20,0x02]
25 # CHECK-32R:    rotr    $4, $4, 0           # encoding: [0x00,0x24,0x20,0x02]
26   rol $4,$5,0
27 # CHECK-32:     srl     $4, $5, 0           # encoding: [0x00,0x05,0x20,0x02]
28 # CHECK-32R:    rotr    $4, $5, 0           # encoding: [0x00,0x25,0x20,0x02]
29   rol $4,1
30 # CHECK-32:     sll     $1, $4, 1           # encoding: [0x00,0x04,0x08,0x40]
31 # CHECK-32:     srl     $4, $4, 31          # encoding: [0x00,0x04,0x27,0xc2]
32 # CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
33 # CHECK-32R:    rotr    $4, $4, 31          # encoding: [0x00,0x24,0x27,0xc2]
34   rol $4,$5,1
35 # CHECK-32:     sll     $1, $5, 1           # encoding: [0x00,0x05,0x08,0x40]
36 # CHECK-32:     srl     $4, $5, 31          # encoding: [0x00,0x05,0x27,0xc2]
37 # CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
38 # CHECK-32R:    rotr    $4, $5, 31          # encoding: [0x00,0x25,0x27,0xc2]
39   rol $4,2
40 # CHECK-32:     sll     $1, $4, 2           # encoding: [0x00,0x04,0x08,0x80]
41 # CHECK-32:     srl     $4, $4, 30          # encoding: [0x00,0x04,0x27,0x82]
42 # CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
43 # CHECK-32R:    rotr    $4, $4, 30          # encoding: [0x00,0x24,0x27,0x82]
44   rol $4,$5,2
45 # CHECK-32:     sll     $1, $5, 2           # encoding: [0x00,0x05,0x08,0x80]
46 # CHECK-32:     srl     $4, $5, 30          # encoding: [0x00,0x05,0x27,0x82]
47 # CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
48 # CHECK-32R:    rotr    $4, $5, 30          # encoding: [0x00,0x25,0x27,0x82]
49
50   ror $4,$5
51 # CHECK-32:     negu    $1, $5              # encoding: [0x00,0x05,0x08,0x23]
52 # CHECK-32:     sllv    $1, $4, $1          # encoding: [0x00,0x24,0x08,0x04]
53 # CHECK-32:     srlv    $4, $4, $5          # encoding: [0x00,0xa4,0x20,0x06]
54 # CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
55 # CHECK-32R:    rotrv   $4, $4, $5          # encoding: [0x00,0xa4,0x20,0x46]
56   ror $4,$5,$6
57 # CHECK-32:     negu    $1, $6              # encoding: [0x00,0x06,0x08,0x23]
58 # CHECK-32:     sllv    $1, $5, $1          # encoding: [0x00,0x25,0x08,0x04]
59 # CHECK-32:     srlv    $4, $5, $6          # encoding: [0x00,0xc5,0x20,0x06]
60 # CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
61 # CHECK-32R:    rotrv   $4, $5, $6          # encoding: [0x00,0xc5,0x20,0x46]
62   ror $4,0
63 # CHECK-32:     srl     $4, $4, 0           # encoding: [0x00,0x04,0x20,0x02]
64 # CHECK-32R:    rotr    $4, $4, 0           # encoding: [0x00,0x24,0x20,0x02]
65   ror $4,$5,0
66 # CHECK-32:     srl     $4, $5, 0           # encoding: [0x00,0x05,0x20,0x02]
67 # CHECK-32R:    rotr    $4, $5, 0           # encoding: [0x00,0x25,0x20,0x02]
68   ror $4,1
69 # CHECK-32:     srl     $1, $4, 1           # encoding: [0x00,0x04,0x08,0x42]
70 # CHECK-32:     sll     $4, $4, 31          # encoding: [0x00,0x04,0x27,0xc0]
71 # CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
72 # CHECK-32R:    rotr    $4, $4, 1           # encoding: [0x00,0x24,0x20,0x42]
73   ror $4,$5,1
74 # CHECK-32:     srl     $1, $5, 1           # encoding: [0x00,0x05,0x08,0x42]
75 # CHECK-32:     sll     $4, $5, 31          # encoding: [0x00,0x05,0x27,0xc0]
76 # CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
77 # CHECK-32R:    rotr    $4, $5, 1           # encoding: [0x00,0x25,0x20,0x42]
78   ror $4,2
79 # CHECK-32:     srl     $1, $4, 2           # encoding: [0x00,0x04,0x08,0x82]
80 # CHECK-32:     sll     $4, $4, 30          # encoding: [0x00,0x04,0x27,0x80]
81 # CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
82 # CHECK-32R:    rotr    $4, $4, 2           # encoding: [0x00,0x24,0x20,0x82]
83   ror $4,$5,2
84 # CHECK-32:     srl     $1, $5, 2           # encoding: [0x00,0x05,0x08,0x82]
85 # CHECK-32:     sll     $4, $5, 30          # encoding: [0x00,0x05,0x27,0x80]
86 # CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
87 # CHECK-32R:    rotr    $4, $5, 2           # encoding: [0x00,0x25,0x20,0x82]