1 ; This test makes sure that urem instructions are properly eliminated.
3 ; RUN: opt < %s -instcombine -S | FileCheck %s
6 define i32 @test1(i32 %A) {
8 ; CHECK-NEXT: ret i32 0
9 %B = srem i32 %A, 1 ; ISA constant 0
13 define i32 @test2(i32 %A) { ; 0 % X = 0, we don't need to preserve traps
14 ; CHECK-LABEL: @test2(
15 ; CHECK-NEXT: ret i32 0
20 define i32 @test3(i32 %A) {
21 ; CHECK-LABEL: @test3(
22 ; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 7
23 ; CHECK-NEXT: ret i32 [[AND]]
28 define i1 @test3a(i32 %A) {
29 ; CHECK-LABEL: @test3a(
30 ; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 7
31 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
32 ; CHECK-NEXT: ret i1 [[CMP]]
34 %C = icmp ne i32 %B, 0
38 define i32 @test4(i32 %X, i1 %C) {
39 ; CHECK-LABEL: @test4(
40 ; CHECK-NEXT: [[SEL:%.*]] = select i1 %C, i32 0, i32 7
41 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SEL]], %X
42 %V = select i1 %C, i32 1, i32 8
47 define i32 @test5(i32 %X, i8 %B) {
48 ; CHECK-LABEL: @test5(
49 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 %B to i32
50 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 32, [[ZEXT]]
51 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], -1
52 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], %X
53 ; CHECK-NEXT: ret i32 [[AND]]
54 %shift.upgrd.1 = zext i8 %B to i32
55 %Amt = shl i32 32, %shift.upgrd.1
56 %V = urem i32 %X, %Amt
60 define i32 @test6(i32 %A) {
61 ; CHECK-LABEL: @test6(
62 ; CHECK-NEXT: ret i32 undef
63 %B = srem i32 %A, 0 ;; undef
67 define i32 @test7(i32 %A) {
68 ; CHECK-LABEL: @test7(
69 ; CHECK-NEXT: ret i32 0
75 define i32 @test8(i32 %A) {
76 ; CHECK-LABEL: @test8(
77 ; CHECK-NEXT: ret i32 0
83 define i32 @test9(i32 %A) {
84 ; CHECK-LABEL: @test9(
85 ; CHECK-NEXT: ret i32 0
91 define i32 @test10(i8 %c) {
92 ; CHECK-LABEL: @test10(
93 ; CHECK-NEXT: ret i32 0
94 %tmp.1 = zext i8 %c to i32
95 %tmp.2 = mul i32 %tmp.1, 4
96 %tmp.3 = sext i32 %tmp.2 to i64
97 %tmp.5 = urem i64 %tmp.3, 4
98 %tmp.6 = trunc i64 %tmp.5 to i32
102 define i32 @test11(i32 %i) {
103 ; CHECK-LABEL: @test11(
104 ; CHECK-NEXT: ret i32 0
105 %tmp.1 = and i32 %i, -2
106 %tmp.3 = mul i32 %tmp.1, 2
107 %tmp.5 = urem i32 %tmp.3, 4
111 define i32 @test12(i32 %i) {
112 ; CHECK-LABEL: @test12(
113 ; CHECK-NEXT: ret i32 0
114 %tmp.1 = and i32 %i, -4
115 %tmp.5 = srem i32 %tmp.1, 2
119 define i32 @test13(i32 %i) {
120 ; CHECK-LABEL: @test13(
121 ; CHECK-NEXT: ret i32 0
126 define i64 @test14(i64 %x, i32 %y) {
127 ; CHECK-LABEL: @test14(
128 ; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, %y
129 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[SHL]] to i64
130 ; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[ZEXT]], -1
131 ; CHECK-NEXT: [[AND:%.*]] = and i64 [[ADD]], %x
132 ; CHECK-NEXT: ret i64 [[AND]]
134 %zext = zext i32 %shl to i64
135 %urem = urem i64 %x, %zext
139 define i64 @test15(i32 %x, i32 %y) {
140 ; CHECK-LABEL: @test15(
141 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, %y
142 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], -1
143 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], %x
144 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[AND]] to i64
145 ; CHECK-NEXT: ret i64 [[ZEXT]]
147 %zext0 = zext i32 %shl to i64
148 %zext1 = zext i32 %x to i64
149 %urem = urem i64 %zext1, %zext0
153 define i32 @test16(i32 %x, i32 %y) {
154 ; CHECK-LABEL: @test16(
155 ; CHECK-NEXT: [[SHR:%.*]] = lshr i32 %y, 11
156 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], 4
157 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], 3
158 ; CHECK-NEXT: [[REM:%.*]] = and i32 [[OR]], %x
159 ; CHECK-NEXT: ret i32 [[REM]]
160 %shr = lshr i32 %y, 11
161 %and = and i32 %shr, 4
162 %add = add i32 %and, 4
163 %rem = urem i32 %x, %add
167 define i32 @test17(i32 %X) {
168 ; CHECK-LABEL: @test17(
169 ; CHECK-NEXT: icmp ne i32 %X, 1
170 ; CHECK-NEXT: zext i1
176 define i32 @test18(i16 %x, i32 %y) {
178 ; CHECK-NEXT: [[AND:%.*]] = and i16 %x, 4
179 ; CHECK-NEXT: [[EXT:%.*]] = zext i16 [[AND]] to i32
180 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw nsw i32 [[EXT]], 3
181 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[SHL]], 63
182 ; CHECK-NEXT: [[REM:%.*]] = and i32 [[XOR]], %y
183 ; CHECK-NEXT: ret i32 [[REM]]
185 %2 = icmp ne i16 %1, 0
186 %3 = select i1 %2, i32 32, i32 64
191 define i32 @test19(i32 %x, i32 %y) {
193 ; CHECK-NEXT: [[SHL1:%.*]] = shl i32 1, %x
194 ; CHECK-NEXT: [[SHL2:%.*]] = shl i32 1, %y
195 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL1]], [[SHL2]]
196 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[AND]], [[SHL1]]
197 ; CHECK-NEXT: [[SUB:%.*]] = add i32 [[ADD]], -1
198 ; CHECK-NEXT: [[REM:%.*]] = and i32 [[SUB]], %y
199 ; CHECK-NEXT: ret i32 [[REM]]
208 define <2 x i64> @test20(<2 x i64> %X, <2 x i1> %C) {
209 ; CHECK-LABEL: @test20(
210 ; CHECK-NEXT: select <2 x i1> %C, <2 x i64> <i64 1, i64 2>, <2 x i64> zeroinitializer
211 ; CHECK-NEXT: ret <2 x i64>
212 %V = select <2 x i1> %C, <2 x i64> <i64 1, i64 2>, <2 x i64> <i64 8, i64 9>
213 %R = urem <2 x i64> %V, <i64 2, i64 3>