1 //===------------ ARMDecoderEmitter.cpp - Decoder Generator ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the ARM Disassembler.
11 // It contains the tablegen backend that emits the decoder functions for ARM and
12 // Thumb. The disassembler core includes the auto-generated file, invokes the
13 // decoder functions, and builds up the MCInst based on the decoded Opcode.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "arm-decoder-emitter"
19 #include "ARMDecoderEmitter.h"
20 #include "CodeGenTarget.h"
22 #include "llvm/ADT/StringExtras.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/raw_ostream.h"
32 /////////////////////////////////////////////////////
34 // Enums and Utilities for ARM Instruction Format //
36 /////////////////////////////////////////////////////
39 ENTRY(ARM_FORMAT_PSEUDO, 0) \
40 ENTRY(ARM_FORMAT_MULFRM, 1) \
41 ENTRY(ARM_FORMAT_BRFRM, 2) \
42 ENTRY(ARM_FORMAT_BRMISCFRM, 3) \
43 ENTRY(ARM_FORMAT_DPFRM, 4) \
44 ENTRY(ARM_FORMAT_DPSOREGFRM, 5) \
45 ENTRY(ARM_FORMAT_LDFRM, 6) \
46 ENTRY(ARM_FORMAT_STFRM, 7) \
47 ENTRY(ARM_FORMAT_LDMISCFRM, 8) \
48 ENTRY(ARM_FORMAT_STMISCFRM, 9) \
49 ENTRY(ARM_FORMAT_LDSTMULFRM, 10) \
50 ENTRY(ARM_FORMAT_LDSTEXFRM, 11) \
51 ENTRY(ARM_FORMAT_ARITHMISCFRM, 12) \
52 ENTRY(ARM_FORMAT_EXTFRM, 13) \
53 ENTRY(ARM_FORMAT_VFPUNARYFRM, 14) \
54 ENTRY(ARM_FORMAT_VFPBINARYFRM, 15) \
55 ENTRY(ARM_FORMAT_VFPCONV1FRM, 16) \
56 ENTRY(ARM_FORMAT_VFPCONV2FRM, 17) \
57 ENTRY(ARM_FORMAT_VFPCONV3FRM, 18) \
58 ENTRY(ARM_FORMAT_VFPCONV4FRM, 19) \
59 ENTRY(ARM_FORMAT_VFPCONV5FRM, 20) \
60 ENTRY(ARM_FORMAT_VFPLDSTFRM, 21) \
61 ENTRY(ARM_FORMAT_VFPLDSTMULFRM, 22) \
62 ENTRY(ARM_FORMAT_VFPMISCFRM, 23) \
63 ENTRY(ARM_FORMAT_THUMBFRM, 24) \
64 ENTRY(ARM_FORMAT_NEONFRM, 25) \
65 ENTRY(ARM_FORMAT_NEONGETLNFRM, 26) \
66 ENTRY(ARM_FORMAT_NEONSETLNFRM, 27) \
67 ENTRY(ARM_FORMAT_NEONDUPFRM, 28) \
68 ENTRY(ARM_FORMAT_MISCFRM, 29) \
69 ENTRY(ARM_FORMAT_THUMBMISCFRM, 30) \
70 ENTRY(ARM_FORMAT_NLdSt, 31) \
71 ENTRY(ARM_FORMAT_N1RegModImm, 32) \
72 ENTRY(ARM_FORMAT_N2Reg, 33) \
73 ENTRY(ARM_FORMAT_NVCVT, 34) \
74 ENTRY(ARM_FORMAT_NVecDupLn, 35) \
75 ENTRY(ARM_FORMAT_N2RegVecShL, 36) \
76 ENTRY(ARM_FORMAT_N2RegVecShR, 37) \
77 ENTRY(ARM_FORMAT_N3Reg, 38) \
78 ENTRY(ARM_FORMAT_N3RegVecSh, 39) \
79 ENTRY(ARM_FORMAT_NVecExtract, 40) \
80 ENTRY(ARM_FORMAT_NVecMulScalar, 41) \
81 ENTRY(ARM_FORMAT_NVTBL, 42)
83 // ARM instruction format specifies the encoding used by the instruction.
84 #define ENTRY(n, v) n = v,
91 // Converts enum to const char*.
92 static const char *stringForARMFormat(ARMFormat form) {
93 #define ENTRY(n, v) case n: return #n;
110 /////////////////////////
112 // Utility functions //
114 /////////////////////////
116 /// byteFromBitsInit - Return the byte value from a BitsInit.
117 /// Called from getByteField().
118 static uint8_t byteFromBitsInit(BitsInit &init) {
119 int width = init.getNumBits();
121 assert(width <= 8 && "Field is too large for uint8_t!");
128 for (index = 0; index < width; index++) {
129 if (static_cast<BitInit*>(init.getBit(index))->getValue())
138 static uint8_t getByteField(const Record &def, const char *str) {
139 BitsInit *bits = def.getValueAsBitsInit(str);
140 return byteFromBitsInit(*bits);
143 static BitsInit &getBitsField(const Record &def, const char *str) {
144 BitsInit *bits = def.getValueAsBitsInit(str);
148 /// sameStringExceptSuffix - Return true if the two strings differ only in RHS's
149 /// suffix. ("VST4d8", "VST4d8_UPD", "_UPD") as input returns true.
151 bool sameStringExceptSuffix(const StringRef LHS, const StringRef RHS,
152 const StringRef Suffix) {
154 if (RHS.startswith(LHS) && RHS.endswith(Suffix))
155 return RHS.size() == LHS.size() + Suffix.size();
160 /// thumbInstruction - Determine whether we have a Thumb instruction.
161 /// See also ARMInstrFormats.td.
162 static bool thumbInstruction(uint8_t Form) {
163 return Form == ARM_FORMAT_THUMBFRM;
166 // The set (BIT_TRUE, BIT_FALSE, BIT_UNSET) represents a ternary logic system
169 // BIT_UNFILTERED is used as the init value for a filter position. It is used
170 // only for filter processings.
175 BIT_UNFILTERED // unfiltered
178 static bool ValueSet(bit_value_t V) {
179 return (V == BIT_TRUE || V == BIT_FALSE);
181 static bool ValueNotSet(bit_value_t V) {
182 return (V == BIT_UNSET);
184 static int Value(bit_value_t V) {
185 return ValueNotSet(V) ? -1 : (V == BIT_FALSE ? 0 : 1);
187 static bit_value_t bitFromBits(BitsInit &bits, unsigned index) {
188 if (BitInit *bit = dynamic_cast<BitInit*>(bits.getBit(index)))
189 return bit->getValue() ? BIT_TRUE : BIT_FALSE;
191 // The bit is uninitialized.
194 // Prints the bit value for each position.
195 static void dumpBits(raw_ostream &o, BitsInit &bits) {
198 for (index = bits.getNumBits(); index > 0; index--) {
199 switch (bitFromBits(bits, index - 1)) {
210 assert(0 && "unexpected return value from bitFromBits");
215 // Enums for the available target names.
221 // FIXME: Possibly auto-detected?
224 // Forward declaration.
227 // Representation of the instruction to work on.
228 typedef bit_value_t insn_t[BIT_WIDTH];
230 /// Filter - Filter works with FilterChooser to produce the decoding tree for
233 /// It is useful to think of a Filter as governing the switch stmts of the
234 /// decoding tree in a certain level. Each case stmt delegates to an inferior
235 /// FilterChooser to decide what further decoding logic to employ, or in another
236 /// words, what other remaining bits to look at. The FilterChooser eventually
237 /// chooses a best Filter to do its job.
239 /// This recursive scheme ends when the number of Opcodes assigned to the
240 /// FilterChooser becomes 1 or if there is a conflict. A conflict happens when
241 /// the Filter/FilterChooser combo does not know how to distinguish among the
242 /// Opcodes assigned.
244 /// An example of a conflcit is
247 /// 111101000.00........00010000....
248 /// 111101000.00........0001........
249 /// 1111010...00........0001........
250 /// 1111010...00....................
251 /// 1111010.........................
252 /// 1111............................
253 /// ................................
254 /// VST4q8a 111101000_00________00010000____
255 /// VST4q8b 111101000_00________00010000____
257 /// The Debug output shows the path that the decoding tree follows to reach the
258 /// the conclusion that there is a conflict. VST4q8a is a vst4 to double-spaced
259 /// even registers, while VST4q8b is a vst4 to double-spaced odd regsisters.
261 /// The encoding info in the .td files does not specify this meta information,
262 /// which could have been used by the decoder to resolve the conflict. The
263 /// decoder could try to decode the even/odd register numbering and assign to
264 /// VST4q8a or VST4q8b, but for the time being, the decoder chooses the "a"
265 /// version and return the Opcode since the two have the same Asm format string.
268 FilterChooser *Owner; // points to the FilterChooser who owns this filter
269 unsigned StartBit; // the starting bit position
270 unsigned NumBits; // number of bits to filter
271 bool Mixed; // a mixed region contains both set and unset bits
273 // Map of well-known segment value to the set of uid's with that value.
274 std::map<uint64_t, std::vector<unsigned> > FilteredInstructions;
276 // Set of uid's with non-constant segment values.
277 std::vector<unsigned> VariableInstructions;
279 // Map of well-known segment value to its delegate.
280 std::map<unsigned, FilterChooser*> FilterChooserMap;
282 // Number of instructions which fall under FilteredInstructions category.
283 unsigned NumFiltered;
285 // Keeps track of the last opcode in the filtered bucket.
286 unsigned LastOpcFiltered;
288 // Number of instructions which fall under VariableInstructions category.
289 unsigned NumVariable;
292 unsigned getNumFiltered() { return NumFiltered; }
293 unsigned getNumVariable() { return NumVariable; }
294 unsigned getSingletonOpc() {
295 assert(NumFiltered == 1);
296 return LastOpcFiltered;
298 // Return the filter chooser for the group of instructions without constant
300 FilterChooser &getVariableFC() {
301 assert(NumFiltered == 1);
302 assert(FilterChooserMap.size() == 1);
303 return *(FilterChooserMap.find((unsigned)-1)->second);
306 Filter(const Filter &f);
307 Filter(FilterChooser &owner, unsigned startBit, unsigned numBits, bool mixed);
311 // Divides the decoding task into sub tasks and delegates them to the
312 // inferior FilterChooser's.
314 // A special case arises when there's only one entry in the filtered
315 // instructions. In order to unambiguously decode the singleton, we need to
316 // match the remaining undecoded encoding bits against the singleton.
319 // Emit code to decode instructions given a segment or segments of bits.
320 void emit(raw_ostream &o, unsigned &Indentation);
322 // Returns the number of fanout produced by the filter. More fanout implies
323 // the filter distinguishes more categories of instructions.
324 unsigned usefulness() const;
325 }; // End of class Filter
327 // These are states of our finite state machines used in FilterChooser's
328 // filterProcessor() which produces the filter candidates to use.
337 /// FilterChooser - FilterChooser chooses the best filter among a set of Filters
338 /// in order to perform the decoding of instructions at the current level.
340 /// Decoding proceeds from the top down. Based on the well-known encoding bits
341 /// of instructions available, FilterChooser builds up the possible Filters that
342 /// can further the task of decoding by distinguishing among the remaining
343 /// candidate instructions.
345 /// Once a filter has been chosen, it is called upon to divide the decoding task
346 /// into sub-tasks and delegates them to its inferior FilterChoosers for further
349 /// It is useful to think of a Filter as governing the switch stmts of the
350 /// decoding tree. And each case is delegated to an inferior FilterChooser to
351 /// decide what further remaining bits to look at.
352 class FilterChooser {
353 static TARGET_NAME_t TargetName;
358 // Vector of codegen instructions to choose our filter.
359 const std::vector<const CodeGenInstruction*> &AllInstructions;
361 // Vector of uid's for this filter chooser to work on.
362 const std::vector<unsigned> Opcodes;
364 // Vector of candidate filters.
365 std::vector<Filter> Filters;
367 // Array of bit values passed down from our parent.
368 // Set to all BIT_UNFILTERED's for Parent == NULL.
369 bit_value_t FilterBitValues[BIT_WIDTH];
371 // Links to the FilterChooser above us in the decoding tree.
372 FilterChooser *Parent;
374 // Index of the best filter from Filters.
378 static void setTargetName(TARGET_NAME_t tn) { TargetName = tn; }
380 FilterChooser(const FilterChooser &FC) :
381 AllInstructions(FC.AllInstructions), Opcodes(FC.Opcodes),
382 Filters(FC.Filters), Parent(FC.Parent), BestIndex(FC.BestIndex) {
383 memcpy(FilterBitValues, FC.FilterBitValues, sizeof(FilterBitValues));
386 FilterChooser(const std::vector<const CodeGenInstruction*> &Insts,
387 const std::vector<unsigned> &IDs) :
388 AllInstructions(Insts), Opcodes(IDs), Filters(), Parent(NULL),
390 for (unsigned i = 0; i < BIT_WIDTH; ++i)
391 FilterBitValues[i] = BIT_UNFILTERED;
396 FilterChooser(const std::vector<const CodeGenInstruction*> &Insts,
397 const std::vector<unsigned> &IDs,
398 bit_value_t (&ParentFilterBitValues)[BIT_WIDTH],
399 FilterChooser &parent) :
400 AllInstructions(Insts), Opcodes(IDs), Filters(), Parent(&parent),
402 for (unsigned i = 0; i < BIT_WIDTH; ++i)
403 FilterBitValues[i] = ParentFilterBitValues[i];
408 // The top level filter chooser has NULL as its parent.
409 bool isTopLevel() { return Parent == NULL; }
411 // This provides an opportunity for target specific code emission.
412 void emitTopHook(raw_ostream &o);
414 // Emit the top level typedef and decodeInstruction() function.
415 void emitTop(raw_ostream &o, unsigned &Indentation);
417 // This provides an opportunity for target specific code emission after
419 void emitBot(raw_ostream &o, unsigned &Indentation);
422 // Populates the insn given the uid.
423 void insnWithID(insn_t &Insn, unsigned Opcode) const {
424 BitsInit &Bits = getBitsField(*AllInstructions[Opcode]->TheDef, "Inst");
426 for (unsigned i = 0; i < BIT_WIDTH; ++i)
427 Insn[i] = bitFromBits(Bits, i);
429 // Set Inst{21} to 1 (wback) when IndexModeBits == IndexModeUpd.
430 if (getByteField(*AllInstructions[Opcode]->TheDef, "IndexModeBits")
435 // Returns the record name.
436 const std::string &nameWithID(unsigned Opcode) const {
437 return AllInstructions[Opcode]->TheDef->getName();
440 // Populates the field of the insn given the start position and the number of
441 // consecutive bits to scan for.
443 // Returns false if there exists any uninitialized bit value in the range.
444 // Returns true, otherwise.
445 bool fieldFromInsn(uint64_t &Field, insn_t &Insn, unsigned StartBit,
446 unsigned NumBits) const;
448 /// dumpFilterArray - dumpFilterArray prints out debugging info for the given
449 /// filter array as a series of chars.
450 void dumpFilterArray(raw_ostream &o, bit_value_t (&filter)[BIT_WIDTH]);
452 /// dumpStack - dumpStack traverses the filter chooser chain and calls
453 /// dumpFilterArray on each filter chooser up to the top level one.
454 void dumpStack(raw_ostream &o, const char *prefix);
456 Filter &bestFilter() {
457 assert(BestIndex != -1 && "BestIndex not set");
458 return Filters[BestIndex];
461 // Called from Filter::recurse() when singleton exists. For debug purpose.
462 void SingletonExists(unsigned Opc);
464 bool PositionFiltered(unsigned i) {
465 return ValueSet(FilterBitValues[i]);
468 // Calculates the island(s) needed to decode the instruction.
469 // This returns a lit of undecoded bits of an instructions, for example,
470 // Inst{20} = 1 && Inst{3-0} == 0b1111 represents two islands of yet-to-be
471 // decoded bits in order to verify that the instruction matches the Opcode.
472 unsigned getIslands(std::vector<unsigned> &StartBits,
473 std::vector<unsigned> &EndBits, std::vector<uint64_t> &FieldVals,
476 // The purpose of this function is for the API client to detect possible
477 // Load/Store Coprocessor instructions. If the coprocessor number is of
478 // the instruction is either 10 or 11, the decoder should not report the
479 // instruction as LDC/LDC2/STC/STC2, but should match against Advanced SIMD or
481 bool LdStCopEncoding1(unsigned Opc) {
482 const std::string &Name = nameWithID(Opc);
483 if (Name == "LDC_OFFSET" || Name == "LDC_OPTION" ||
484 Name == "LDC_POST" || Name == "LDC_PRE" ||
485 Name == "LDCL_OFFSET" || Name == "LDCL_OPTION" ||
486 Name == "LDCL_POST" || Name == "LDCL_PRE" ||
487 Name == "STC_OFFSET" || Name == "STC_OPTION" ||
488 Name == "STC_POST" || Name == "STC_PRE" ||
489 Name == "STCL_OFFSET" || Name == "STCL_OPTION" ||
490 Name == "STCL_POST" || Name == "STCL_PRE")
496 // Emits code to decode the singleton. Return true if we have matched all the
498 bool emitSingletonDecoder(raw_ostream &o, unsigned &Indentation,unsigned Opc);
500 // Emits code to decode the singleton, and then to decode the rest.
501 void emitSingletonDecoder(raw_ostream &o, unsigned &Indentation,Filter &Best);
503 // Assign a single filter and run with it.
504 void runSingleFilter(FilterChooser &owner, unsigned startBit, unsigned numBit,
507 // reportRegion is a helper function for filterProcessor to mark a region as
508 // eligible for use as a filter region.
509 void reportRegion(bitAttr_t RA, unsigned StartBit, unsigned BitIndex,
512 // FilterProcessor scans the well-known encoding bits of the instructions and
513 // builds up a list of candidate filters. It chooses the best filter and
514 // recursively descends down the decoding tree.
515 bool filterProcessor(bool AllowMixed, bool Greedy = true);
517 // Decides on the best configuration of filter(s) to use in order to decode
518 // the instructions. A conflict of instructions may occur, in which case we
519 // dump the conflict set to the standard error.
522 // Emits code to decode our share of instructions. Returns true if the
523 // emitted code causes a return, which occurs if we know how to decode
524 // the instruction at this level or the instruction is not decodeable.
525 bool emit(raw_ostream &o, unsigned &Indentation);
528 ///////////////////////////
530 // Filter Implmenetation //
532 ///////////////////////////
534 Filter::Filter(const Filter &f) :
535 Owner(f.Owner), StartBit(f.StartBit), NumBits(f.NumBits), Mixed(f.Mixed),
536 FilteredInstructions(f.FilteredInstructions),
537 VariableInstructions(f.VariableInstructions),
538 FilterChooserMap(f.FilterChooserMap), NumFiltered(f.NumFiltered),
539 LastOpcFiltered(f.LastOpcFiltered), NumVariable(f.NumVariable) {
542 Filter::Filter(FilterChooser &owner, unsigned startBit, unsigned numBits,
543 bool mixed) : Owner(&owner), StartBit(startBit), NumBits(numBits),
545 assert(StartBit + NumBits - 1 < BIT_WIDTH);
551 for (unsigned i = 0, e = Owner->Opcodes.size(); i != e; ++i) {
554 // Populates the insn given the uid.
555 Owner->insnWithID(Insn, Owner->Opcodes[i]);
558 // Scans the segment for possibly well-specified encoding bits.
559 bool ok = Owner->fieldFromInsn(Field, Insn, StartBit, NumBits);
562 // The encoding bits are well-known. Lets add the uid of the
563 // instruction into the bucket keyed off the constant field value.
564 LastOpcFiltered = Owner->Opcodes[i];
565 FilteredInstructions[Field].push_back(LastOpcFiltered);
568 // Some of the encoding bit(s) are unspecfied. This contributes to
569 // one additional member of "Variable" instructions.
570 VariableInstructions.push_back(Owner->Opcodes[i]);
575 assert((FilteredInstructions.size() + VariableInstructions.size() > 0)
576 && "Filter returns no instruction categories");
580 std::map<unsigned, FilterChooser*>::iterator filterIterator;
581 for (filterIterator = FilterChooserMap.begin();
582 filterIterator != FilterChooserMap.end();
584 delete filterIterator->second;
588 // Divides the decoding task into sub tasks and delegates them to the
589 // inferior FilterChooser's.
591 // A special case arises when there's only one entry in the filtered
592 // instructions. In order to unambiguously decode the singleton, we need to
593 // match the remaining undecoded encoding bits against the singleton.
594 void Filter::recurse() {
595 std::map<uint64_t, std::vector<unsigned> >::const_iterator mapIterator;
597 bit_value_t BitValueArray[BIT_WIDTH];
598 // Starts by inheriting our parent filter chooser's filter bit values.
599 bit_value_t *BitVals = Owner->FilterBitValues;
600 for (unsigned i = 0; i < BIT_WIDTH; ++i)
601 BitValueArray[i] = BitVals[i];
602 // FIXME: memcpy() is optmized out with self-hosting llvm-gcc (-O1 and -O2).
603 //memcpy(BitValueArray, Owner->FilterBitValues, sizeof(BitValueArray));
607 if (VariableInstructions.size()) {
608 // Conservatively marks each segment position as BIT_UNSET.
609 for (bitIndex = 0; bitIndex < NumBits; bitIndex++)
610 BitValueArray[StartBit + bitIndex] = BIT_UNSET;
612 // Delegates to an inferior filter chooser for futher processing on this
613 // group of instructions whose segment values are variable.
614 FilterChooserMap.insert(std::pair<unsigned, FilterChooser*>(
616 new FilterChooser(Owner->AllInstructions,
617 VariableInstructions,
623 // No need to recurse for a singleton filtered instruction.
624 // See also Filter::emit().
625 if (getNumFiltered() == 1) {
626 //Owner->SingletonExists(LastOpcFiltered);
627 assert(FilterChooserMap.size() == 1);
631 // Otherwise, create sub choosers.
632 for (mapIterator = FilteredInstructions.begin();
633 mapIterator != FilteredInstructions.end();
636 // Marks all the segment positions with either BIT_TRUE or BIT_FALSE.
637 for (bitIndex = 0; bitIndex < NumBits; bitIndex++) {
638 if (mapIterator->first & (1 << bitIndex))
639 BitValueArray[StartBit + bitIndex] = BIT_TRUE;
641 BitValueArray[StartBit + bitIndex] = BIT_FALSE;
644 // Delegates to an inferior filter chooser for futher processing on this
645 // category of instructions.
646 FilterChooserMap.insert(std::pair<unsigned, FilterChooser*>(
648 new FilterChooser(Owner->AllInstructions,
656 // Emit code to decode instructions given a segment or segments of bits.
657 void Filter::emit(raw_ostream &o, unsigned &Indentation) {
658 o.indent(Indentation) << "// Check Inst{";
661 o << (StartBit + NumBits - 1) << '-';
663 o << StartBit << "} ...\n";
665 o.indent(Indentation) << "switch (fieldFromInstruction(insn, "
666 << StartBit << ", " << NumBits << ")) {\n";
668 std::map<unsigned, FilterChooser*>::iterator filterIterator;
670 bool DefaultCase = false;
671 for (filterIterator = FilterChooserMap.begin();
672 filterIterator != FilterChooserMap.end();
675 // Field value -1 implies a non-empty set of variable instructions.
676 // See also recurse().
677 if (filterIterator->first == (unsigned)-1) {
680 o.indent(Indentation) << "default:\n";
681 o.indent(Indentation) << " break; // fallthrough\n";
683 // Closing curly brace for the switch statement.
684 // This is unconventional because we want the default processing to be
685 // performed for the fallthrough cases as well, i.e., when the "cases"
686 // did not prove a decoded instruction.
687 o.indent(Indentation) << "}\n";
690 o.indent(Indentation) << "case " << filterIterator->first << ":\n";
692 // We arrive at a category of instructions with the same segment value.
693 // Now delegate to the sub filter chooser for further decodings.
694 // The case may fallthrough, which happens if the remaining well-known
695 // encoding bits do not match exactly.
696 if (!DefaultCase) { ++Indentation; ++Indentation; }
698 bool finished = filterIterator->second->emit(o, Indentation);
699 // For top level default case, there's no need for a break statement.
700 if (Owner->isTopLevel() && DefaultCase)
703 o.indent(Indentation) << "break;\n";
705 if (!DefaultCase) { --Indentation; --Indentation; }
708 // If there is no default case, we still need to supply a closing brace.
710 // Closing curly brace for the switch statement.
711 o.indent(Indentation) << "}\n";
715 // Returns the number of fanout produced by the filter. More fanout implies
716 // the filter distinguishes more categories of instructions.
717 unsigned Filter::usefulness() const {
718 if (VariableInstructions.size())
719 return FilteredInstructions.size();
721 return FilteredInstructions.size() + 1;
724 //////////////////////////////////
726 // Filterchooser Implementation //
728 //////////////////////////////////
730 // Define the symbol here.
731 TARGET_NAME_t FilterChooser::TargetName;
733 // This provides an opportunity for target specific code emission.
734 void FilterChooser::emitTopHook(raw_ostream &o) {
735 if (TargetName == TARGET_ARM) {
736 // Emit code that references the ARMFormat data type.
737 o << "static const ARMFormat ARMFormats[] = {\n";
738 for (unsigned i = 0, e = AllInstructions.size(); i != e; ++i) {
739 const Record &Def = *(AllInstructions[i]->TheDef);
740 const std::string &Name = Def.getName();
741 if (Def.isSubClassOf("InstARM") || Def.isSubClassOf("InstThumb"))
743 stringForARMFormat((ARMFormat)getByteField(Def, "Form"));
745 o << " ARM_FORMAT_NA";
747 o << ",\t// Inst #" << i << " = " << Name << '\n';
749 o << " ARM_FORMAT_NA\t// Unreachable.\n";
754 // Emit the top level typedef and decodeInstruction() function.
755 void FilterChooser::emitTop(raw_ostream &o, unsigned &Indentation) {
756 // Run the target specific emit hook.
761 o.indent(Indentation) << "typedef uint8_t field_t;\n";
764 o.indent(Indentation) << "typedef uint16_t field_t;\n";
767 o.indent(Indentation) << "typedef uint32_t field_t;\n";
770 o.indent(Indentation) << "typedef uint64_t field_t;\n";
773 assert(0 && "Unexpected instruction size!");
778 o.indent(Indentation) << "static field_t " <<
779 "fieldFromInstruction(field_t insn, unsigned startBit, unsigned numBits)\n";
781 o.indent(Indentation) << "{\n";
783 ++Indentation; ++Indentation;
784 o.indent(Indentation) << "assert(startBit + numBits <= " << BIT_WIDTH
785 << " && \"Instruction field out of bounds!\");\n";
787 o.indent(Indentation) << "field_t fieldMask;\n";
789 o.indent(Indentation) << "if (numBits == " << BIT_WIDTH << ")\n";
791 ++Indentation; ++Indentation;
792 o.indent(Indentation) << "fieldMask = (field_t)-1;\n";
793 --Indentation; --Indentation;
795 o.indent(Indentation) << "else\n";
797 ++Indentation; ++Indentation;
798 o.indent(Indentation) << "fieldMask = ((1 << numBits) - 1) << startBit;\n";
799 --Indentation; --Indentation;
802 o.indent(Indentation) << "return (insn & fieldMask) >> startBit;\n";
803 --Indentation; --Indentation;
805 o.indent(Indentation) << "}\n";
809 o.indent(Indentation) << "static uint16_t decodeInstruction(field_t insn) {\n";
811 ++Indentation; ++Indentation;
812 // Emits code to decode the instructions.
813 emit(o, Indentation);
816 o.indent(Indentation) << "return 0;\n";
817 --Indentation; --Indentation;
819 o.indent(Indentation) << "}\n";
824 // This provides an opportunity for target specific code emission after
826 void FilterChooser::emitBot(raw_ostream &o, unsigned &Indentation) {
827 if (TargetName != TARGET_THUMB) return;
829 // Emit code that decodes the Thumb ISA.
830 o.indent(Indentation)
831 << "static uint16_t decodeThumbInstruction(field_t insn) {\n";
833 ++Indentation; ++Indentation;
835 // Emits code to decode the instructions.
836 emit(o, Indentation);
839 o.indent(Indentation) << "return 0;\n";
841 --Indentation; --Indentation;
843 o.indent(Indentation) << "}\n";
846 // Populates the field of the insn given the start position and the number of
847 // consecutive bits to scan for.
849 // Returns false if and on the first uninitialized bit value encountered.
850 // Returns true, otherwise.
851 bool FilterChooser::fieldFromInsn(uint64_t &Field, insn_t &Insn,
852 unsigned StartBit, unsigned NumBits) const {
855 for (unsigned i = 0; i < NumBits; ++i) {
856 if (Insn[StartBit + i] == BIT_UNSET)
859 if (Insn[StartBit + i] == BIT_TRUE)
860 Field = Field | (1 << i);
866 /// dumpFilterArray - dumpFilterArray prints out debugging info for the given
867 /// filter array as a series of chars.
868 void FilterChooser::dumpFilterArray(raw_ostream &o,
869 bit_value_t (&filter)[BIT_WIDTH]) {
872 for (bitIndex = BIT_WIDTH; bitIndex > 0; bitIndex--) {
873 switch (filter[bitIndex - 1]) {
890 /// dumpStack - dumpStack traverses the filter chooser chain and calls
891 /// dumpFilterArray on each filter chooser up to the top level one.
892 void FilterChooser::dumpStack(raw_ostream &o, const char *prefix) {
893 FilterChooser *current = this;
897 dumpFilterArray(o, current->FilterBitValues);
899 current = current->Parent;
903 // Called from Filter::recurse() when singleton exists. For debug purpose.
904 void FilterChooser::SingletonExists(unsigned Opc) {
906 insnWithID(Insn0, Opc);
908 errs() << "Singleton exists: " << nameWithID(Opc)
909 << " with its decoding dominating ";
910 for (unsigned i = 0; i < Opcodes.size(); ++i) {
911 if (Opcodes[i] == Opc) continue;
912 errs() << nameWithID(Opcodes[i]) << ' ';
916 dumpStack(errs(), "\t\t");
917 for (unsigned i = 0; i < Opcodes.size(); i++) {
918 const std::string &Name = nameWithID(Opcodes[i]);
920 errs() << '\t' << Name << " ";
922 getBitsField(*AllInstructions[Opcodes[i]]->TheDef, "Inst"));
927 // Calculates the island(s) needed to decode the instruction.
928 // This returns a list of undecoded bits of an instructions, for example,
929 // Inst{20} = 1 && Inst{3-0} == 0b1111 represents two islands of yet-to-be
930 // decoded bits in order to verify that the instruction matches the Opcode.
931 unsigned FilterChooser::getIslands(std::vector<unsigned> &StartBits,
932 std::vector<unsigned> &EndBits, std::vector<uint64_t> &FieldVals,
937 uint64_t FieldVal = 0;
940 // 1: Water (the bit value does not affect decoding)
941 // 2: Island (well-known bit value needed for decoding)
945 for (unsigned i = 0; i < BIT_WIDTH; ++i) {
946 Val = Value(Insn[i]);
947 bool Filtered = PositionFiltered(i);
950 assert(0 && "Unreachable code!");
954 if (Filtered || Val == -1)
955 State = 1; // Still in Water
957 State = 2; // Into the Island
959 StartBits.push_back(i);
964 if (Filtered || Val == -1) {
965 State = 1; // Into the Water
966 EndBits.push_back(i - 1);
967 FieldVals.push_back(FieldVal);
970 State = 2; // Still in Island
972 FieldVal = FieldVal | Val << BitNo;
977 // If we are still in Island after the loop, do some housekeeping.
979 EndBits.push_back(BIT_WIDTH - 1);
980 FieldVals.push_back(FieldVal);
984 assert(StartBits.size() == Num && EndBits.size() == Num &&
985 FieldVals.size() == Num);
989 // Emits code to decode the singleton. Return true if we have matched all the
991 bool FilterChooser::emitSingletonDecoder(raw_ostream &o, unsigned &Indentation,
993 std::vector<unsigned> StartBits;
994 std::vector<unsigned> EndBits;
995 std::vector<uint64_t> FieldVals;
997 insnWithID(Insn, Opc);
999 // This provides a good opportunity to check for possible Ld/St Coprocessor
1000 // Opcode and escapes if the coproc # is either 10 or 11. It is a NEON/VFP
1001 // instruction is disguise.
1002 if (TargetName == TARGET_ARM && LdStCopEncoding1(Opc)) {
1003 o.indent(Indentation);
1004 // A8.6.51 & A8.6.188
1005 // If coproc = 0b101?, i.e, slice(insn, 11, 8) = 10 or 11, escape.
1006 o << "if (fieldFromInstruction(insn, 9, 3) == 5) break; // fallthrough\n";
1009 // Look for islands of undecoded bits of the singleton.
1010 getIslands(StartBits, EndBits, FieldVals, Insn);
1012 unsigned Size = StartBits.size();
1013 unsigned I, NumBits;
1015 // If we have matched all the well-known bits, just issue a return.
1017 o.indent(Indentation) << "return " << Opc << "; // " << nameWithID(Opc)
1022 // Otherwise, there are more decodings to be done!
1024 // Emit code to match the island(s) for the singleton.
1025 o.indent(Indentation) << "// Check ";
1027 for (I = Size; I != 0; --I) {
1028 o << "Inst{" << EndBits[I-1] << '-' << StartBits[I-1] << "} ";
1032 o << "for singleton decoding...\n";
1035 o.indent(Indentation) << "if (";
1037 for (I = Size; I != 0; --I) {
1038 NumBits = EndBits[I-1] - StartBits[I-1] + 1;
1039 o << "fieldFromInstruction(insn, " << StartBits[I-1] << ", " << NumBits
1040 << ") == " << FieldVals[I-1];
1047 o.indent(Indentation) << " return " << Opc << "; // " << nameWithID(Opc)
1053 // Emits code to decode the singleton, and then to decode the rest.
1054 void FilterChooser::emitSingletonDecoder(raw_ostream &o, unsigned &Indentation,
1057 unsigned Opc = Best.getSingletonOpc();
1059 emitSingletonDecoder(o, Indentation, Opc);
1061 // Emit code for the rest.
1062 o.indent(Indentation) << "else\n";
1065 Best.getVariableFC().emit(o, Indentation);
1069 // Assign a single filter and run with it. Top level API client can initialize
1070 // with a single filter to start the filtering process.
1071 void FilterChooser::runSingleFilter(FilterChooser &owner, unsigned startBit,
1072 unsigned numBit, bool mixed) {
1074 Filter F(*this, startBit, numBit, true);
1075 Filters.push_back(F);
1076 BestIndex = 0; // Sole Filter instance to choose from.
1077 bestFilter().recurse();
1080 // reportRegion is a helper function for filterProcessor to mark a region as
1081 // eligible for use as a filter region.
1082 void FilterChooser::reportRegion(bitAttr_t RA, unsigned StartBit,
1083 unsigned BitIndex, bool AllowMixed) {
1084 if (RA == ATTR_MIXED && AllowMixed)
1085 Filters.push_back(Filter(*this, StartBit, BitIndex - StartBit, true));
1086 else if (RA == ATTR_ALL_SET && !AllowMixed)
1087 Filters.push_back(Filter(*this, StartBit, BitIndex - StartBit, false));
1090 // FilterProcessor scans the well-known encoding bits of the instructions and
1091 // builds up a list of candidate filters. It chooses the best filter and
1092 // recursively descends down the decoding tree.
1093 bool FilterChooser::filterProcessor(bool AllowMixed, bool Greedy) {
1096 unsigned numInstructions = Opcodes.size();
1098 assert(numInstructions && "Filter created with no instructions");
1100 // No further filtering is necessary.
1101 if (numInstructions == 1)
1104 // Heuristics. See also doFilter()'s "Heuristics" comment when num of
1105 // instructions is 3.
1106 if (AllowMixed && !Greedy) {
1107 assert(numInstructions == 3);
1109 for (unsigned i = 0; i < Opcodes.size(); ++i) {
1110 std::vector<unsigned> StartBits;
1111 std::vector<unsigned> EndBits;
1112 std::vector<uint64_t> FieldVals;
1115 insnWithID(Insn, Opcodes[i]);
1117 // Look for islands of undecoded bits of any instruction.
1118 if (getIslands(StartBits, EndBits, FieldVals, Insn) > 0) {
1119 // Found an instruction with island(s). Now just assign a filter.
1120 runSingleFilter(*this, StartBits[0], EndBits[0] - StartBits[0] + 1,
1127 unsigned BitIndex, InsnIndex;
1129 // We maintain BIT_WIDTH copies of the bitAttrs automaton.
1130 // The automaton consumes the corresponding bit from each
1133 // Input symbols: 0, 1, and _ (unset).
1134 // States: NONE, FILTERED, ALL_SET, ALL_UNSET, and MIXED.
1135 // Initial state: NONE.
1137 // (NONE) ------- [01] -> (ALL_SET)
1138 // (NONE) ------- _ ----> (ALL_UNSET)
1139 // (ALL_SET) ---- [01] -> (ALL_SET)
1140 // (ALL_SET) ---- _ ----> (MIXED)
1141 // (ALL_UNSET) -- [01] -> (MIXED)
1142 // (ALL_UNSET) -- _ ----> (ALL_UNSET)
1143 // (MIXED) ------ . ----> (MIXED)
1144 // (FILTERED)---- . ----> (FILTERED)
1146 bitAttr_t bitAttrs[BIT_WIDTH];
1148 // FILTERED bit positions provide no entropy and are not worthy of pursuing.
1149 // Filter::recurse() set either BIT_TRUE or BIT_FALSE for each position.
1150 for (BitIndex = 0; BitIndex < BIT_WIDTH; ++BitIndex)
1151 if (FilterBitValues[BitIndex] == BIT_TRUE ||
1152 FilterBitValues[BitIndex] == BIT_FALSE)
1153 bitAttrs[BitIndex] = ATTR_FILTERED;
1155 bitAttrs[BitIndex] = ATTR_NONE;
1157 for (InsnIndex = 0; InsnIndex < numInstructions; ++InsnIndex) {
1160 insnWithID(insn, Opcodes[InsnIndex]);
1162 for (BitIndex = 0; BitIndex < BIT_WIDTH; ++BitIndex) {
1163 switch (bitAttrs[BitIndex]) {
1165 if (insn[BitIndex] == BIT_UNSET)
1166 bitAttrs[BitIndex] = ATTR_ALL_UNSET;
1168 bitAttrs[BitIndex] = ATTR_ALL_SET;
1171 if (insn[BitIndex] == BIT_UNSET)
1172 bitAttrs[BitIndex] = ATTR_MIXED;
1174 case ATTR_ALL_UNSET:
1175 if (insn[BitIndex] != BIT_UNSET)
1176 bitAttrs[BitIndex] = ATTR_MIXED;
1185 // The regionAttr automaton consumes the bitAttrs automatons' state,
1186 // lowest-to-highest.
1188 // Input symbols: F(iltered), (all_)S(et), (all_)U(nset), M(ixed)
1189 // States: NONE, ALL_SET, MIXED
1190 // Initial state: NONE
1192 // (NONE) ----- F --> (NONE)
1193 // (NONE) ----- S --> (ALL_SET) ; and set region start
1194 // (NONE) ----- U --> (NONE)
1195 // (NONE) ----- M --> (MIXED) ; and set region start
1196 // (ALL_SET) -- F --> (NONE) ; and report an ALL_SET region
1197 // (ALL_SET) -- S --> (ALL_SET)
1198 // (ALL_SET) -- U --> (NONE) ; and report an ALL_SET region
1199 // (ALL_SET) -- M --> (MIXED) ; and report an ALL_SET region
1200 // (MIXED) ---- F --> (NONE) ; and report a MIXED region
1201 // (MIXED) ---- S --> (ALL_SET) ; and report a MIXED region
1202 // (MIXED) ---- U --> (NONE) ; and report a MIXED region
1203 // (MIXED) ---- M --> (MIXED)
1205 bitAttr_t RA = ATTR_NONE;
1206 unsigned StartBit = 0;
1208 for (BitIndex = 0; BitIndex < BIT_WIDTH; BitIndex++) {
1209 bitAttr_t bitAttr = bitAttrs[BitIndex];
1211 assert(bitAttr != ATTR_NONE && "Bit without attributes");
1219 StartBit = BitIndex;
1222 case ATTR_ALL_UNSET:
1225 StartBit = BitIndex;
1229 assert(0 && "Unexpected bitAttr!");
1235 reportRegion(RA, StartBit, BitIndex, AllowMixed);
1240 case ATTR_ALL_UNSET:
1241 reportRegion(RA, StartBit, BitIndex, AllowMixed);
1245 reportRegion(RA, StartBit, BitIndex, AllowMixed);
1246 StartBit = BitIndex;
1250 assert(0 && "Unexpected bitAttr!");
1256 reportRegion(RA, StartBit, BitIndex, AllowMixed);
1257 StartBit = BitIndex;
1261 reportRegion(RA, StartBit, BitIndex, AllowMixed);
1262 StartBit = BitIndex;
1265 case ATTR_ALL_UNSET:
1266 reportRegion(RA, StartBit, BitIndex, AllowMixed);
1272 assert(0 && "Unexpected bitAttr!");
1275 case ATTR_ALL_UNSET:
1276 assert(0 && "regionAttr state machine has no ATTR_UNSET state");
1278 assert(0 && "regionAttr state machine has no ATTR_FILTERED state");
1282 // At the end, if we're still in ALL_SET or MIXED states, report a region
1289 reportRegion(RA, StartBit, BitIndex, AllowMixed);
1291 case ATTR_ALL_UNSET:
1294 reportRegion(RA, StartBit, BitIndex, AllowMixed);
1298 // We have finished with the filter processings. Now it's time to choose
1299 // the best performing filter.
1301 bool AllUseless = true;
1302 unsigned BestScore = 0;
1304 for (unsigned i = 0, e = Filters.size(); i != e; ++i) {
1305 unsigned Usefulness = Filters[i].usefulness();
1310 if (Usefulness > BestScore) {
1312 BestScore = Usefulness;
1317 bestFilter().recurse();
1320 } // end of FilterChooser::filterProcessor(bool)
1322 // Decides on the best configuration of filter(s) to use in order to decode
1323 // the instructions. A conflict of instructions may occur, in which case we
1324 // dump the conflict set to the standard error.
1325 void FilterChooser::doFilter() {
1326 unsigned Num = Opcodes.size();
1327 assert(Num && "FilterChooser created with no instructions");
1329 // Heuristics: Use Inst{31-28} as the top level filter for ARM ISA.
1330 if (TargetName == TARGET_ARM && Parent == NULL) {
1331 runSingleFilter(*this, 28, 4, false);
1335 // Try regions of consecutive known bit values first.
1336 if (filterProcessor(false))
1339 // Then regions of mixed bits (both known and unitialized bit values allowed).
1340 if (filterProcessor(true))
1343 // Heuristics to cope with conflict set {t2CMPrs, t2SUBSrr, t2SUBSrs} where
1344 // no single instruction for the maximum ATTR_MIXED region Inst{14-4} has a
1345 // well-known encoding pattern. In such case, we backtrack and scan for the
1346 // the very first consecutive ATTR_ALL_SET region and assign a filter to it.
1347 if (Num == 3 && filterProcessor(true, false))
1350 // If we come to here, the instruction decoding has failed.
1351 // Print out the instructions in the conflict set...
1355 errs() << "Conflict:\n";
1357 dumpStack(errs(), "\t\t");
1359 for (unsigned i = 0; i < Num; i++) {
1360 const std::string &Name = nameWithID(Opcodes[i]);
1362 errs() << '\t' << Name << " ";
1364 getBitsField(*AllInstructions[Opcodes[i]]->TheDef, "Inst"));
1370 // Emits code to decode our share of instructions. Returns true if the
1371 // emitted code causes a return, which occurs if we know how to decode
1372 // the instruction at this level or the instruction is not decodeable.
1373 bool FilterChooser::emit(raw_ostream &o, unsigned &Indentation) {
1374 if (Opcodes.size() == 1)
1375 // There is only one instruction in the set, which is great!
1376 // Call emitSingletonDecoder() to see whether there are any remaining
1378 return emitSingletonDecoder(o, Indentation, Opcodes[0]);
1380 // Choose the best filter to do the decodings!
1381 if (BestIndex != -1) {
1382 Filter &Best = bestFilter();
1383 if (Best.getNumFiltered() == 1)
1384 emitSingletonDecoder(o, Indentation, Best);
1386 bestFilter().emit(o, Indentation);
1390 // If we reach here, there is a conflict in decoding. Let's resolve the known
1392 if ((TargetName == TARGET_ARM || TargetName == TARGET_THUMB) &&
1393 Opcodes.size() == 2) {
1394 // Resolve the known conflict sets:
1396 // 1. source registers are identical => VMOVDneon; otherwise => VORRd
1397 // 2. source registers are identical => VMOVQ; otherwise => VORRq
1398 // 3. LDR, LDRcp => return LDR for now.
1399 // FIXME: How can we distinguish between LDR and LDRcp? Do we need to?
1400 // 4. tLDM, tLDM_UPD => Rn = Inst{10-8}, reglist = Inst{7-0},
1401 // wback = registers<Rn> = 0
1402 // NOTE: (tLDM, tLDM_UPD) resolution must come before Advanced SIMD
1403 // addressing mode resolution!!!
1404 // 5. VLD[234]LN*/VST[234]LN* vs. VLD[234]LN*_UPD/VST[234]LN*_UPD conflicts
1405 // are resolved returning the non-UPD versions of the instructions if the
1406 // Rm field, i.e., Inst{3-0} is 0b1111. This is specified in A7.7.1
1407 // Advanced SIMD addressing mode.
1408 const std::string &name1 = nameWithID(Opcodes[0]);
1409 const std::string &name2 = nameWithID(Opcodes[1]);
1410 if ((name1 == "VMOVDneon" && name2 == "VORRd") ||
1411 (name1 == "VMOVQ" && name2 == "VORRq")) {
1412 // Inserting the opening curly brace for this case block.
1413 --Indentation; --Indentation;
1414 o.indent(Indentation) << "{\n";
1415 ++Indentation; ++Indentation;
1417 o.indent(Indentation)
1418 << "field_t N = fieldFromInstruction(insn, 7, 1), "
1419 << "M = fieldFromInstruction(insn, 5, 1);\n";
1420 o.indent(Indentation)
1421 << "field_t Vn = fieldFromInstruction(insn, 16, 4), "
1422 << "Vm = fieldFromInstruction(insn, 0, 4);\n";
1423 o.indent(Indentation)
1424 << "return (N == M && Vn == Vm) ? "
1425 << Opcodes[0] << " /* " << name1 << " */ : "
1426 << Opcodes[1] << " /* " << name2 << " */ ;\n";
1428 // Inserting the closing curly brace for this case block.
1429 --Indentation; --Indentation;
1430 o.indent(Indentation) << "}\n";
1431 ++Indentation; ++Indentation;
1435 if (name1 == "LDR" && name2 == "LDRcp") {
1436 o.indent(Indentation)
1437 << "return " << Opcodes[0]
1438 << "; // Returning LDR for {LDR, LDRcp}\n";
1441 if (name1 == "tLDM" && name2 == "tLDM_UPD") {
1442 // Inserting the opening curly brace for this case block.
1443 --Indentation; --Indentation;
1444 o.indent(Indentation) << "{\n";
1445 ++Indentation; ++Indentation;
1447 o.indent(Indentation)
1448 << "unsigned Rn = fieldFromInstruction(insn, 8, 3), "
1449 << "list = fieldFromInstruction(insn, 0, 8);\n";
1450 o.indent(Indentation)
1451 << "return ((list >> Rn) & 1) == 0 ? "
1452 << Opcodes[1] << " /* " << name2 << " */ : "
1453 << Opcodes[0] << " /* " << name1 << " */ ;\n";
1455 // Inserting the closing curly brace for this case block.
1456 --Indentation; --Indentation;
1457 o.indent(Indentation) << "}\n";
1458 ++Indentation; ++Indentation;
1462 if (sameStringExceptSuffix(name1, name2, "_UPD")) {
1463 o.indent(Indentation)
1464 << "return fieldFromInstruction(insn, 0, 4) == 15 ? " << Opcodes[0]
1465 << " /* " << name1 << " */ : " << Opcodes[1] << "/* " << name2
1466 << " */ ; // Advanced SIMD addressing mode\n";
1470 // Otherwise, it does not belong to the known conflict sets.
1472 // We don't know how to decode these instructions! Dump the conflict set!
1473 o.indent(Indentation) << "return 0;" << " // Conflict set: ";
1474 for (int i = 0, N = Opcodes.size(); i < N; ++i) {
1475 o << nameWithID(Opcodes[i]);
1485 ////////////////////////////////////////////
1488 // (Helper class for ARMDecoderEmitter) //
1490 ////////////////////////////////////////////
1492 class ARMDecoderEmitter::ARMDEBackend {
1494 ARMDEBackend(ARMDecoderEmitter &frontend) :
1495 NumberedInstructions(),
1501 if (Target.getName() == "ARM")
1502 TargetName = TARGET_ARM;
1504 errs() << "Target name " << Target.getName() << " not recognized\n";
1505 assert(0 && "Unknown target");
1508 // Populate the instructions for our TargetName.
1509 populateInstructions();
1519 void getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
1520 &NumberedInstructions) {
1521 // We must emit the PHI opcode first...
1522 std::string Namespace = Target.getInstNamespace();
1523 assert(!Namespace.empty() && "No instructions defined.");
1525 NumberedInstructions = Target.getInstructionsByEnumValue();
1528 bool populateInstruction(const CodeGenInstruction &CGI, TARGET_NAME_t TN);
1530 void populateInstructions();
1532 // Emits disassembler code for instruction decoding. This delegates to the
1533 // FilterChooser instance to do the heavy lifting.
1534 void emit(raw_ostream &o);
1537 std::vector<const CodeGenInstruction*> NumberedInstructions;
1538 std::vector<unsigned> Opcodes;
1539 // Special case for the ARM chip, which supports ARM and Thumb ISAs.
1540 // Opcodes2 will be populated with the Thumb opcodes.
1541 std::vector<unsigned> Opcodes2;
1542 ARMDecoderEmitter &Frontend;
1543 CodeGenTarget Target;
1546 TARGET_NAME_t TargetName;
1549 bool ARMDecoderEmitter::ARMDEBackend::populateInstruction(
1550 const CodeGenInstruction &CGI, TARGET_NAME_t TN) {
1551 const Record &Def = *CGI.TheDef;
1552 const StringRef Name = Def.getName();
1553 uint8_t Form = getByteField(Def, "Form");
1555 if (TN == TARGET_ARM) {
1556 // FIXME: what about Int_MemBarrierV6 and Int_SyncBarrierV6?
1557 if ((Name != "Int_MemBarrierV7" && Name != "Int_SyncBarrierV7") &&
1558 Form == ARM_FORMAT_PSEUDO)
1560 if (thumbInstruction(Form))
1562 if (Name.find("CMPz") != std::string::npos /* ||
1563 Name.find("CMNz") != std::string::npos */)
1566 // Ignore pseudo instructions.
1567 if (Name == "BXr9" || Name == "BMOVPCRX" || Name == "BMOVPCRXr9")
1570 // VLDMQ/VSTMQ can be hanlded with the more generic VLDMD/VSTMD.
1571 if (Name == "VLDMQ" || Name == "VLDMQ_UPD" ||
1572 Name == "VSTMQ" || Name == "VSTMQ_UPD")
1576 // The following special cases are for conflict resolutions.
1579 // NEON NLdStFrm conflict resolutions:
1581 // 1. Ignore suffix "odd" and "odd_UPD", prefer the "even" register-
1582 // numbered ones which have the same Asm format string.
1583 // 2. Ignore VST2d64_UPD, which conflicts with VST1q64_UPD.
1584 // 3. Ignore VLD2d64_UPD, which conflicts with VLD1q64_UPD.
1585 // 4. Ignore VLD1q[_UPD], which conflicts with VLD1q64[_UPD].
1586 // 5. Ignore VST1q[_UPD], which conflicts with VST1q64[_UPD].
1587 if (Name.endswith("odd") || Name.endswith("odd_UPD") ||
1588 Name == "VST2d64_UPD" || Name == "VLD2d64_UPD" ||
1589 Name == "VLD1q" || Name == "VLD1q_UPD" ||
1590 Name == "VST1q" || Name == "VST1q_UPD")
1593 // RSCSri and RSCSrs set the 's' bit, but are not predicated. We are
1594 // better off using the generic RSCri and RSCrs instructions.
1595 if (Name == "RSCSri" || Name == "RSCSrs") return false;
1597 // MOVCCr, MOVCCs, MOVCCi, FCYPScc, FCYPDcc, FNEGScc, and FNEGDcc are used
1598 // in the compiler to implement conditional moves. We can ignore them in
1599 // favor of their more generic versions of instructions.
1600 // See also SDNode *ARMDAGToDAGISel::Select(SDValue Op).
1601 if (Name == "MOVCCr" || Name == "MOVCCs" || Name == "MOVCCi" ||
1602 Name == "FCPYScc" || Name == "FCPYDcc" ||
1603 Name == "FNEGScc" || Name == "FNEGDcc")
1606 // Ditto for VMOVDcc, VMOVScc, VNEGDcc, and VNEGScc.
1607 if (Name == "VMOVDcc" || Name == "VMOVScc" || Name == "VNEGDcc" ||
1611 // Ignore the *_sfp instructions when decoding. They are used by the
1612 // compiler to implement scalar floating point operations using vector
1613 // operations in order to work around some performance issues.
1614 if (Name.find("_sfp") != std::string::npos) return false;
1616 // LDM_RET is a special case of LDM (Load Multiple) where the registers
1617 // loaded include the PC, causing a branch to a loaded address. Ignore
1618 // the LDM_RET instruction when decoding.
1619 if (Name == "LDM_RET") return false;
1621 // Bcc is in a more generic form than B. Ignore B when decoding.
1622 if (Name == "B") return false;
1624 // Ignore the non-Darwin BL instructions and the TPsoft (TLS) instruction.
1625 if (Name == "BL" || Name == "BL_pred" || Name == "BLX" || Name == "BX" ||
1629 // Ignore VDUPf[d|q] instructions known to conflict with VDUP32[d-q] for
1630 // decoding. The instruction duplicates an element from an ARM core
1631 // register into every element of the destination vector. There is no
1632 // distinction between data types.
1633 if (Name == "VDUPfd" || Name == "VDUPfq") return false;
1636 // Vector Extract extracts elements from the bottom end of the second
1637 // operand vector and the top end of the first, concatenates them and
1638 // places the result in the destination vector. The elements of the
1639 // vectors are treated as being 8-bit bitfields. There is no distinction
1640 // between data types. The size of the operation can be specified in
1641 // assembler as vext.size. If the value is 16, 32, or 64, the syntax is
1642 // a pseudo-instruction for a VEXT instruction specifying the equivalent
1645 // Variants VEXTd16, VEXTd32, VEXTd8, and VEXTdf are reduced to VEXTd8;
1646 // variants VEXTq16, VEXTq32, VEXTq8, and VEXTqf are reduced to VEXTq8.
1647 if (Name == "VEXTd16" || Name == "VEXTd32" || Name == "VEXTdf" ||
1648 Name == "VEXTq16" || Name == "VEXTq32" || Name == "VEXTqf")
1651 // Vector Reverse is similar to Vector Extract. There is no distinction
1652 // between data types, other than size.
1654 // VREV64df is equivalent to VREV64d32.
1655 // VREV64qf is equivalent to VREV64q32.
1656 if (Name == "VREV64df" || Name == "VREV64qf") return false;
1658 // VDUPLNfd is equivalent to VDUPLN32d; VDUPfdf is specialized VDUPLN32d.
1659 // VDUPLNfq is equivalent to VDUPLN32q; VDUPfqf is specialized VDUPLN32q.
1660 // VLD1df is equivalent to VLD1d32.
1661 // VLD1qf is equivalent to VLD1q32.
1662 // VLD2d64 is equivalent to VLD1q64.
1663 // VST1df is equivalent to VST1d32.
1664 // VST1qf is equivalent to VST1q32.
1665 // VST2d64 is equivalent to VST1q64.
1666 if (Name == "VDUPLNfd" || Name == "VDUPfdf" ||
1667 Name == "VDUPLNfq" || Name == "VDUPfqf" ||
1668 Name == "VLD1df" || Name == "VLD1qf" || Name == "VLD2d64" ||
1669 Name == "VST1df" || Name == "VST1qf" || Name == "VST2d64")
1671 } else if (TN == TARGET_THUMB) {
1672 if (!thumbInstruction(Form))
1675 // Ignore pseudo instructions.
1676 if (Name == "tInt_eh_sjlj_setjmp" || Name == "t2Int_eh_sjlj_setjmp" ||
1677 Name == "t2MOVi32imm" || Name == "tBX" || Name == "tBXr9")
1680 // On Darwin R9 is call-clobbered. Ignore the non-Darwin counterparts.
1681 if (Name == "tBL" || Name == "tBLXi" || Name == "tBLXr")
1684 // Ignore the TPsoft (TLS) instructions, which conflict with tBLr9.
1685 if (Name == "tTPsoft" || Name == "t2TPsoft")
1688 // Ignore tLEApcrel and tLEApcrelJT, prefer tADDrPCi.
1689 if (Name == "tLEApcrel" || Name == "tLEApcrelJT")
1692 // Ignore t2LEApcrel, prefer the generic t2ADD* for disassembly printing.
1693 if (Name == "t2LEApcrel")
1696 // Ignore tADDrSP, tADDspr, and tPICADD, prefer the generic tADDhirr.
1697 // Ignore t2SUBrSPs, prefer the t2SUB[S]r[r|s].
1698 // Ignore t2ADDrSPs, prefer the t2ADD[S]r[r|s].
1699 if (Name == "tADDrSP" || Name == "tADDspr" || Name == "tPICADD" ||
1700 Name == "t2SUBrSPs" || Name == "t2ADDrSPs")
1703 // Ignore t2LDRDpci, prefer the generic t2LDRDi8, t2LDRD_PRE, t2LDRD_POST.
1704 if (Name == "t2LDRDpci")
1707 // Ignore t2TBB, t2TBH and prefer the generic t2TBBgen, t2TBHgen.
1708 if (Name == "t2TBB" || Name == "t2TBH")
1711 // Resolve conflicts:
1713 // tBfar conflicts with tBLr9
1714 // tCMNz conflicts with tCMN (with assembly format strings being equal)
1715 // tPOP_RET/t2LDM_RET conflict with tPOP/t2LDM (ditto)
1716 // tMOVCCi conflicts with tMOVi8
1717 // tMOVCCr conflicts with tMOVgpr2gpr
1718 // tBR_JTr conflicts with tBRIND
1719 // tSpill conflicts with tSTRspi
1720 // tLDRcp conflicts with tLDRspi
1721 // tRestore conflicts with tLDRspi
1722 // t2LEApcrelJT conflicts with t2LEApcrel
1723 // t2ADDrSPi/t2SUBrSPi have more generic couterparts
1724 if (Name == "tBfar" ||
1725 /* Name == "tCMNz" || */ Name == "tCMPzi8" || Name == "tCMPzr" ||
1726 Name == "tCMPzhir" || /* Name == "t2CMNzrr" || Name == "t2CMNzrs" ||
1727 Name == "t2CMNzri" || */ Name == "t2CMPzrr" || Name == "t2CMPzrs" ||
1728 Name == "t2CMPzri" || Name == "tPOP_RET" || Name == "t2LDM_RET" ||
1729 Name == "tMOVCCi" || Name == "tMOVCCr" || Name == "tBR_JTr" ||
1730 Name == "tSpill" || Name == "tLDRcp" || Name == "tRestore" ||
1731 Name == "t2LEApcrelJT" || Name == "t2ADDrSPi" || Name == "t2SUBrSPi")
1735 // Dumps the instruction encoding format.
1736 switch (TargetName) {
1739 DEBUG(errs() << Name << " " << stringForARMFormat((ARMFormat)Form));
1744 BitsInit &Bits = getBitsField(Def, "Inst");
1748 // Dumps the instruction encoding bits.
1749 dumpBits(errs(), Bits);
1753 // Dumps the list of operand info.
1754 for (unsigned i = 0, e = CGI.OperandList.size(); i != e; ++i) {
1755 CodeGenInstruction::OperandInfo Info = CGI.OperandList[i];
1756 const std::string &OperandName = Info.Name;
1757 const Record &OperandDef = *Info.Rec;
1759 errs() << "\t" << OperandName << " (" << OperandDef.getName() << ")\n";
1766 void ARMDecoderEmitter::ARMDEBackend::populateInstructions() {
1767 getInstructionsByEnumValue(NumberedInstructions);
1769 uint16_t numUIDs = NumberedInstructions.size();
1772 const char *instClass = NULL;
1774 switch (TargetName) {
1776 instClass = "InstARM";
1779 assert(0 && "Unreachable code!");
1782 for (uid = 0; uid < numUIDs; uid++) {
1783 // filter out intrinsics
1784 if (!NumberedInstructions[uid]->TheDef->isSubClassOf(instClass))
1787 if (populateInstruction(*NumberedInstructions[uid], TargetName))
1788 Opcodes.push_back(uid);
1791 // Special handling for the ARM chip, which supports two modes of execution.
1792 // This branch handles the Thumb opcodes.
1793 if (TargetName == TARGET_ARM) {
1794 for (uid = 0; uid < numUIDs; uid++) {
1795 // filter out intrinsics
1796 if (!NumberedInstructions[uid]->TheDef->isSubClassOf("InstARM")
1797 && !NumberedInstructions[uid]->TheDef->isSubClassOf("InstThumb"))
1800 if (populateInstruction(*NumberedInstructions[uid], TARGET_THUMB))
1801 Opcodes2.push_back(uid);
1806 // Emits disassembler code for instruction decoding. This delegates to the
1807 // FilterChooser instance to do the heavy lifting.
1808 void ARMDecoderEmitter::ARMDEBackend::emit(raw_ostream &o) {
1809 switch (TargetName) {
1811 Frontend.EmitSourceFileHeader("ARM/Thumb Decoders", o);
1814 assert(0 && "Unreachable code!");
1817 o << "#include \"llvm/System/DataTypes.h\"\n";
1818 o << "#include <assert.h>\n";
1820 o << "namespace llvm {\n\n";
1822 FilterChooser::setTargetName(TargetName);
1824 switch (TargetName) {
1826 // Emit common utility and ARM ISA decoder.
1827 FC = new FilterChooser(NumberedInstructions, Opcodes);
1828 // Reset indentation level.
1829 unsigned Indentation = 0;
1830 FC->emitTop(o, Indentation);
1833 // Emit Thumb ISA decoder as well.
1834 FilterChooser::setTargetName(TARGET_THUMB);
1835 FC = new FilterChooser(NumberedInstructions, Opcodes2);
1836 // Reset indentation level.
1838 FC->emitBot(o, Indentation);
1842 assert(0 && "Unreachable code!");
1845 o << "\n} // End llvm namespace \n";
1848 /////////////////////////
1849 // Backend interface //
1850 /////////////////////////
1852 void ARMDecoderEmitter::initBackend()
1854 Backend = new ARMDEBackend(*this);
1857 void ARMDecoderEmitter::run(raw_ostream &o)
1862 void ARMDecoderEmitter::shutdownBackend()