1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "llvm/ADT/PointerUnion.h"
101 #include "llvm/ADT/STLExtras.h"
102 #include "llvm/ADT/SmallPtrSet.h"
103 #include "llvm/ADT/SmallVector.h"
104 #include "llvm/ADT/StringExtras.h"
105 #include "llvm/Support/CommandLine.h"
106 #include "llvm/Support/Debug.h"
107 #include "llvm/Support/ErrorHandling.h"
108 #include "llvm/TableGen/Error.h"
109 #include "llvm/TableGen/Record.h"
110 #include "llvm/TableGen/StringMatcher.h"
111 #include "llvm/TableGen/StringToOffsetTable.h"
112 #include "llvm/TableGen/TableGenBackend.h"
118 #include <forward_list>
119 using namespace llvm;
121 #define DEBUG_TYPE "asm-matcher-emitter"
123 static cl::opt<std::string>
124 MatchPrefix("match-prefix", cl::init(""),
125 cl::desc("Only match instructions with the given prefix"));
128 class AsmMatcherInfo;
129 struct SubtargetFeatureInfo;
131 // Register sets are used as keys in some second-order sets TableGen creates
132 // when generating its data structures. This means that the order of two
133 // RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
134 // can even affect compiler output (at least seen in diagnostics produced when
135 // all matches fail). So we use a type that sorts them consistently.
136 typedef std::set<Record*, LessRecordByID> RegisterSet;
138 class AsmMatcherEmitter {
139 RecordKeeper &Records;
141 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
143 void run(raw_ostream &o);
146 /// ClassInfo - Helper class for storing the information about a particular
147 /// class of operands which can be matched.
150 /// Invalid kind, for use as a sentinel value.
153 /// The class for a particular token.
156 /// The (first) register class, subsequent register classes are
157 /// RegisterClass0+1, and so on.
160 /// The (first) user defined class, subsequent user defined classes are
161 /// UserClass0+1, and so on.
165 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
166 /// N) for the Nth user defined class.
169 /// SuperClasses - The super classes of this class. Note that for simplicities
170 /// sake user operands only record their immediate super class, while register
171 /// operands include all superclasses.
172 std::vector<ClassInfo*> SuperClasses;
174 /// Name - The full class name, suitable for use in an enum.
177 /// ClassName - The unadorned generic name for this class (e.g., Token).
178 std::string ClassName;
180 /// ValueName - The name of the value this class represents; for a token this
181 /// is the literal token string, for an operand it is the TableGen class (or
182 /// empty if this is a derived class).
183 std::string ValueName;
185 /// PredicateMethod - The name of the operand method to test whether the
186 /// operand matches this class; this is not valid for Token or register kinds.
187 std::string PredicateMethod;
189 /// RenderMethod - The name of the operand method to add this operand to an
190 /// MCInst; this is not valid for Token or register kinds.
191 std::string RenderMethod;
193 /// ParserMethod - The name of the operand method to do a target specific
194 /// parsing on the operand.
195 std::string ParserMethod;
197 /// For register classes: the records for all the registers in this class.
198 RegisterSet Registers;
200 /// For custom match classes: the diagnostic kind for when the predicate fails.
201 std::string DiagnosticType;
203 /// isRegisterClass() - Check if this is a register class.
204 bool isRegisterClass() const {
205 return Kind >= RegisterClass0 && Kind < UserClass0;
208 /// isUserClass() - Check if this is a user defined class.
209 bool isUserClass() const {
210 return Kind >= UserClass0;
213 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
214 /// are related if they are in the same class hierarchy.
215 bool isRelatedTo(const ClassInfo &RHS) const {
216 // Tokens are only related to tokens.
217 if (Kind == Token || RHS.Kind == Token)
218 return Kind == Token && RHS.Kind == Token;
220 // Registers classes are only related to registers classes, and only if
221 // their intersection is non-empty.
222 if (isRegisterClass() || RHS.isRegisterClass()) {
223 if (!isRegisterClass() || !RHS.isRegisterClass())
227 std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin());
228 std::set_intersection(Registers.begin(), Registers.end(),
229 RHS.Registers.begin(), RHS.Registers.end(),
230 II, LessRecordByID());
235 // Otherwise we have two users operands; they are related if they are in the
236 // same class hierarchy.
238 // FIXME: This is an oversimplification, they should only be related if they
239 // intersect, however we don't have that information.
240 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
241 const ClassInfo *Root = this;
242 while (!Root->SuperClasses.empty())
243 Root = Root->SuperClasses.front();
245 const ClassInfo *RHSRoot = &RHS;
246 while (!RHSRoot->SuperClasses.empty())
247 RHSRoot = RHSRoot->SuperClasses.front();
249 return Root == RHSRoot;
252 /// isSubsetOf - Test whether this class is a subset of \p RHS.
253 bool isSubsetOf(const ClassInfo &RHS) const {
254 // This is a subset of RHS if it is the same class...
258 // ... or if any of its super classes are a subset of RHS.
259 for (const ClassInfo *CI : SuperClasses)
260 if (CI->isSubsetOf(RHS))
266 /// operator< - Compare two classes.
267 // FIXME: This ordering seems to be broken. For example:
268 // u64 < i64, i64 < s8, s8 < u64, forming a cycle
269 // u64 is a subset of i64
270 // i64 and s8 are not subsets of each other, so are ordered by name
271 // s8 and u64 are not subsets of each other, so are ordered by name
272 bool operator<(const ClassInfo &RHS) const {
276 // Unrelated classes can be ordered by kind.
277 if (!isRelatedTo(RHS))
278 return Kind < RHS.Kind;
282 llvm_unreachable("Invalid kind!");
285 // This class precedes the RHS if it is a proper subset of the RHS.
288 if (RHS.isSubsetOf(*this))
291 // Otherwise, order by name to ensure we have a total ordering.
292 return ValueName < RHS.ValueName;
297 /// MatchableInfo - Helper class for storing the necessary information for an
298 /// instruction or alias which is capable of being matched.
299 struct MatchableInfo {
301 /// Token - This is the token that the operand came from.
304 /// The unique class instance this operand should match.
307 /// The operand name this is, if anything.
310 /// The suboperand index within SrcOpName, or -1 for the entire operand.
313 /// Whether the token is "isolated", i.e., it is preceded and followed
315 bool IsIsolatedToken;
317 /// Register record if this token is singleton register.
318 Record *SingletonReg;
320 explicit AsmOperand(bool IsIsolatedToken, StringRef T)
321 : Token(T), Class(nullptr), SubOpIdx(-1),
322 IsIsolatedToken(IsIsolatedToken), SingletonReg(nullptr) {}
325 /// ResOperand - This represents a single operand in the result instruction
326 /// generated by the match. In cases (like addressing modes) where a single
327 /// assembler operand expands to multiple MCOperands, this represents the
328 /// single assembler operand, not the MCOperand.
331 /// RenderAsmOperand - This represents an operand result that is
332 /// generated by calling the render method on the assembly operand. The
333 /// corresponding AsmOperand is specified by AsmOperandNum.
336 /// TiedOperand - This represents a result operand that is a duplicate of
337 /// a previous result operand.
340 /// ImmOperand - This represents an immediate value that is dumped into
344 /// RegOperand - This represents a fixed register that is dumped in.
349 /// This is the operand # in the AsmOperands list that this should be
351 unsigned AsmOperandNum;
353 /// TiedOperandNum - This is the (earlier) result operand that should be
355 unsigned TiedOperandNum;
357 /// ImmVal - This is the immediate value added to the instruction.
360 /// Register - This is the register record.
364 /// MINumOperands - The number of MCInst operands populated by this
366 unsigned MINumOperands;
368 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
370 X.Kind = RenderAsmOperand;
371 X.AsmOperandNum = AsmOpNum;
372 X.MINumOperands = NumOperands;
376 static ResOperand getTiedOp(unsigned TiedOperandNum) {
378 X.Kind = TiedOperand;
379 X.TiedOperandNum = TiedOperandNum;
384 static ResOperand getImmOp(int64_t Val) {
392 static ResOperand getRegOp(Record *Reg) {
401 /// AsmVariantID - Target's assembly syntax variant no.
404 /// AsmString - The assembly string for this instruction (with variants
405 /// removed), e.g. "movsx $src, $dst".
406 std::string AsmString;
408 /// TheDef - This is the definition of the instruction or InstAlias that this
409 /// matchable came from.
410 Record *const TheDef;
412 /// DefRec - This is the definition that it came from.
413 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
415 const CodeGenInstruction *getResultInst() const {
416 if (DefRec.is<const CodeGenInstruction*>())
417 return DefRec.get<const CodeGenInstruction*>();
418 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
421 /// ResOperands - This is the operand list that should be built for the result
423 SmallVector<ResOperand, 8> ResOperands;
425 /// Mnemonic - This is the first token of the matched instruction, its
429 /// AsmOperands - The textual operands that this instruction matches,
430 /// annotated with a class and where in the OperandList they were defined.
431 /// This directly corresponds to the tokenized AsmString after the mnemonic is
433 SmallVector<AsmOperand, 8> AsmOperands;
435 /// Predicates - The required subtarget features to match this instruction.
436 SmallVector<const SubtargetFeatureInfo *, 4> RequiredFeatures;
438 /// ConversionFnKind - The enum value which is passed to the generated
439 /// convertToMCInst to convert parsed operands into an MCInst for this
441 std::string ConversionFnKind;
443 /// If this instruction is deprecated in some form.
446 /// If this is an alias, this is use to determine whether or not to using
447 /// the conversion function defined by the instruction's AsmMatchConverter
448 /// or to use the function generated by the alias.
449 bool UseInstAsmMatchConverter;
451 MatchableInfo(const CodeGenInstruction &CGI)
452 : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef), DefRec(&CGI),
453 UseInstAsmMatchConverter(true) {
456 MatchableInfo(std::unique_ptr<const CodeGenInstAlias> Alias)
457 : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef),
458 DefRec(Alias.release()),
459 UseInstAsmMatchConverter(
460 TheDef->getValueAsBit("UseInstAsmMatchConverter")) {
464 delete DefRec.dyn_cast<const CodeGenInstAlias*>();
467 // Two-operand aliases clone from the main matchable, but mark the second
468 // operand as a tied operand of the first for purposes of the assembler.
469 void formTwoOperandAlias(StringRef Constraint);
471 void initialize(const AsmMatcherInfo &Info,
472 SmallPtrSetImpl<Record*> &SingletonRegisters,
473 int AsmVariantNo, std::string &RegisterPrefix);
475 /// validate - Return true if this matchable is a valid thing to match against
476 /// and perform a bunch of validity checking.
477 bool validate(StringRef CommentDelimiter, bool Hack) const;
479 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
480 /// if present, from specified token.
482 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info,
483 std::string &RegisterPrefix);
485 /// findAsmOperand - Find the AsmOperand with the specified name and
486 /// suboperand index.
487 int findAsmOperand(StringRef N, int SubOpIdx) const {
488 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
489 if (N == AsmOperands[i].SrcOpName &&
490 SubOpIdx == AsmOperands[i].SubOpIdx)
495 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
496 /// This does not check the suboperand index.
497 int findAsmOperandNamed(StringRef N) const {
498 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
499 if (N == AsmOperands[i].SrcOpName)
504 void buildInstructionResultOperands();
505 void buildAliasResultOperands();
507 /// operator< - Compare two matchables.
508 bool operator<(const MatchableInfo &RHS) const {
509 // The primary comparator is the instruction mnemonic.
510 if (Mnemonic != RHS.Mnemonic)
511 return Mnemonic < RHS.Mnemonic;
513 if (AsmOperands.size() != RHS.AsmOperands.size())
514 return AsmOperands.size() < RHS.AsmOperands.size();
516 // Compare lexicographically by operand. The matcher validates that other
517 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
518 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
519 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
521 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
525 // Give matches that require more features higher precedence. This is useful
526 // because we cannot define AssemblerPredicates with the negation of
527 // processor features. For example, ARM v6 "nop" may be either a HINT or
528 // MOV. With v6, we want to match HINT. The assembler has no way to
529 // predicate MOV under "NoV6", but HINT will always match first because it
530 // requires V6 while MOV does not.
531 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
532 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
537 /// couldMatchAmbiguouslyWith - Check whether this matchable could
538 /// ambiguously match the same set of operands as \p RHS (without being a
539 /// strictly superior match).
540 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) const {
541 // The primary comparator is the instruction mnemonic.
542 if (Mnemonic != RHS.Mnemonic)
545 // The number of operands is unambiguous.
546 if (AsmOperands.size() != RHS.AsmOperands.size())
549 // Otherwise, make sure the ordering of the two instructions is unambiguous
550 // by checking that either (a) a token or operand kind discriminates them,
551 // or (b) the ordering among equivalent kinds is consistent.
553 // Tokens and operand kinds are unambiguous (assuming a correct target
555 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
556 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
557 AsmOperands[i].Class->Kind == ClassInfo::Token)
558 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
559 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
562 // Otherwise, this operand could commute if all operands are equivalent, or
563 // there is a pair of operands that compare less than and a pair that
564 // compare greater than.
565 bool HasLT = false, HasGT = false;
566 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
567 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
569 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
573 return !(HasLT ^ HasGT);
579 void tokenizeAsmString(const AsmMatcherInfo &Info);
580 void addAsmOperand(size_t Start, size_t End);
583 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
584 /// feature which participates in instruction matching.
585 struct SubtargetFeatureInfo {
586 /// \brief The predicate record for this feature.
589 /// \brief An unique index assigned to represent this feature.
592 SubtargetFeatureInfo(Record *D, uint64_t Idx) : TheDef(D), Index(Idx) {}
594 /// \brief The name of the enumerated constant identifying this feature.
595 std::string getEnumName() const {
596 return "Feature_" + TheDef->getName();
600 errs() << getEnumName() << " " << Index << "\n";
605 struct OperandMatchEntry {
606 unsigned OperandMask;
607 const MatchableInfo* MI;
610 static OperandMatchEntry create(const MatchableInfo *mi, ClassInfo *ci,
613 X.OperandMask = opMask;
621 class AsmMatcherInfo {
624 RecordKeeper &Records;
626 /// The tablegen AsmParser record.
629 /// Target - The target information.
630 CodeGenTarget &Target;
632 /// The classes which are needed for matching.
633 std::forward_list<ClassInfo> Classes;
635 /// The information on the matchables to match.
636 std::vector<std::unique_ptr<MatchableInfo>> Matchables;
638 /// Info for custom matching operands by user defined methods.
639 std::vector<OperandMatchEntry> OperandMatchInfo;
641 /// Map of Register records to their class information.
642 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
643 RegisterClassesTy RegisterClasses;
645 /// Map of Predicate records to their subtarget information.
646 std::map<Record *, SubtargetFeatureInfo, LessRecordByID> SubtargetFeatures;
648 /// Map of AsmOperandClass records to their class information.
649 std::map<Record*, ClassInfo*> AsmOperandClasses;
652 /// Map of token to class information which has already been constructed.
653 std::map<std::string, ClassInfo*> TokenClasses;
655 /// Map of RegisterClass records to their class information.
656 std::map<Record*, ClassInfo*> RegisterClassClasses;
659 /// getTokenClass - Lookup or create the class for the given token.
660 ClassInfo *getTokenClass(StringRef Token);
662 /// getOperandClass - Lookup or create the class for the given operand.
663 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
665 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
667 /// buildRegisterClasses - Build the ClassInfo* instances for register
669 void buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters);
671 /// buildOperandClasses - Build the ClassInfo* instances for user defined
673 void buildOperandClasses();
675 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
677 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
678 MatchableInfo::AsmOperand &Op);
681 AsmMatcherInfo(Record *AsmParser,
682 CodeGenTarget &Target,
683 RecordKeeper &Records);
685 /// buildInfo - Construct the various tables used during matching.
688 /// buildOperandMatchInfo - Build the necessary information to handle user
689 /// defined operand parsing methods.
690 void buildOperandMatchInfo();
692 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
694 const SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
695 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
696 const auto &I = SubtargetFeatures.find(Def);
697 return I == SubtargetFeatures.end() ? nullptr : &I->second;
700 RecordKeeper &getRecords() const {
705 } // End anonymous namespace
707 void MatchableInfo::dump() const {
708 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
710 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
711 const AsmOperand &Op = AsmOperands[i];
712 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
713 errs() << '\"' << Op.Token << "\"\n";
717 static std::pair<StringRef, StringRef>
718 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
719 // Split via the '='.
720 std::pair<StringRef, StringRef> Ops = S.split('=');
721 if (Ops.second == "")
722 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
723 // Trim whitespace and the leading '$' on the operand names.
724 size_t start = Ops.first.find_first_of('$');
725 if (start == std::string::npos)
726 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
727 Ops.first = Ops.first.slice(start + 1, std::string::npos);
728 size_t end = Ops.first.find_last_of(" \t");
729 Ops.first = Ops.first.slice(0, end);
730 // Now the second operand.
731 start = Ops.second.find_first_of('$');
732 if (start == std::string::npos)
733 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
734 Ops.second = Ops.second.slice(start + 1, std::string::npos);
735 end = Ops.second.find_last_of(" \t");
736 Ops.first = Ops.first.slice(0, end);
740 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
741 // Figure out which operands are aliased and mark them as tied.
742 std::pair<StringRef, StringRef> Ops =
743 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
745 // Find the AsmOperands that refer to the operands we're aliasing.
746 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
747 int DstAsmOperand = findAsmOperandNamed(Ops.second);
748 if (SrcAsmOperand == -1)
749 PrintFatalError(TheDef->getLoc(),
750 "unknown source two-operand alias operand '" + Ops.first +
752 if (DstAsmOperand == -1)
753 PrintFatalError(TheDef->getLoc(),
754 "unknown destination two-operand alias operand '" +
757 // Find the ResOperand that refers to the operand we're aliasing away
758 // and update it to refer to the combined operand instead.
759 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
760 ResOperand &Op = ResOperands[i];
761 if (Op.Kind == ResOperand::RenderAsmOperand &&
762 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
763 Op.AsmOperandNum = DstAsmOperand;
767 // Remove the AsmOperand for the alias operand.
768 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
769 // Adjust the ResOperand references to any AsmOperands that followed
770 // the one we just deleted.
771 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
772 ResOperand &Op = ResOperands[i];
775 // Nothing to do for operands that don't reference AsmOperands.
777 case ResOperand::RenderAsmOperand:
778 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
781 case ResOperand::TiedOperand:
782 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
789 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
790 SmallPtrSetImpl<Record*> &SingletonRegisters,
791 int AsmVariantNo, std::string &RegisterPrefix) {
792 AsmVariantID = AsmVariantNo;
794 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
796 tokenizeAsmString(Info);
798 // Compute the require features.
799 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
800 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
801 if (const SubtargetFeatureInfo *Feature =
802 Info.getSubtargetFeature(Predicates[i]))
803 RequiredFeatures.push_back(Feature);
805 // Collect singleton registers, if used.
806 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
807 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix);
808 if (Record *Reg = AsmOperands[i].SingletonReg)
809 SingletonRegisters.insert(Reg);
812 const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask");
814 DepMask = TheDef->getValue("ComplexDeprecationPredicate");
817 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
820 /// Append an AsmOperand for the given substring of AsmString.
821 void MatchableInfo::addAsmOperand(size_t Start, size_t End) {
822 StringRef String = AsmString;
823 StringRef Separators = "[]*! \t,";
824 // Look for separators before and after to figure out is this token is
825 // isolated. Accept '$$' as that's how we escape '$'.
826 bool IsIsolatedToken =
827 (!Start || Separators.find(String[Start - 1]) != StringRef::npos ||
828 String.substr(Start - 1, 2) == "$$") &&
829 (End >= String.size() || Separators.find(String[End]) != StringRef::npos);
830 AsmOperands.push_back(AsmOperand(IsIsolatedToken, String.slice(Start, End)));
833 /// tokenizeAsmString - Tokenize a simplified assembly string.
834 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
835 StringRef String = AsmString;
838 for (unsigned i = 0, e = String.size(); i != e; ++i) {
848 addAsmOperand(Prev, i);
851 if (!isspace(String[i]) && String[i] != ',')
852 addAsmOperand(i, i + 1);
858 addAsmOperand(Prev, i);
862 assert(i != String.size() && "Invalid quoted character");
863 addAsmOperand(i, i + 1);
869 addAsmOperand(Prev, i);
873 // If this isn't "${", treat like a normal token.
874 if (i + 1 == String.size() || String[i + 1] != '{') {
879 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
880 assert(End != String.end() && "Missing brace in operand reference!");
881 size_t EndPos = End - String.begin();
882 addAsmOperand(i, EndPos+1);
889 if (!Info.AsmParser->getValueAsBit("MnemonicContainsDot")) {
891 addAsmOperand(Prev, i);
901 if (InTok && Prev != String.size())
902 addAsmOperand(Prev, StringRef::npos);
904 // The first token of the instruction is the mnemonic, which must be a
905 // simple string, not a $foo variable or a singleton register.
906 if (AsmOperands.empty())
907 PrintFatalError(TheDef->getLoc(),
908 "Instruction '" + TheDef->getName() + "' has no tokens");
909 Mnemonic = AsmOperands[0].Token;
910 if (Mnemonic.empty())
911 PrintFatalError(TheDef->getLoc(),
912 "Missing instruction mnemonic");
913 // FIXME : Check and raise an error if it is a register.
914 if (Mnemonic[0] == '$')
915 PrintFatalError(TheDef->getLoc(),
916 "Invalid instruction mnemonic '" + Mnemonic + "'!");
918 // Remove the first operand, it is tracked in the mnemonic field.
919 AsmOperands.erase(AsmOperands.begin());
922 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
923 // Reject matchables with no .s string.
924 if (AsmString.empty())
925 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
927 // Reject any matchables with a newline in them, they should be marked
928 // isCodeGenOnly if they are pseudo instructions.
929 if (AsmString.find('\n') != std::string::npos)
930 PrintFatalError(TheDef->getLoc(),
931 "multiline instruction is not valid for the asmparser, "
932 "mark it isCodeGenOnly");
934 // Remove comments from the asm string. We know that the asmstring only
936 if (!CommentDelimiter.empty() &&
937 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
938 PrintFatalError(TheDef->getLoc(),
939 "asmstring for instruction has comment character in it, "
940 "mark it isCodeGenOnly");
942 // Reject matchables with operand modifiers, these aren't something we can
943 // handle, the target should be refactored to use operands instead of
946 // Also, check for instructions which reference the operand multiple times;
947 // this implies a constraint we would not honor.
948 std::set<std::string> OperandNames;
949 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
950 StringRef Tok = AsmOperands[i].Token;
951 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
952 PrintFatalError(TheDef->getLoc(),
953 "matchable with operand modifier '" + Tok +
954 "' not supported by asm matcher. Mark isCodeGenOnly!");
956 // Verify that any operand is only mentioned once.
957 // We reject aliases and ignore instructions for now.
958 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
960 PrintFatalError(TheDef->getLoc(),
961 "ERROR: matchable with tied operand '" + Tok +
962 "' can never be matched!");
963 // FIXME: Should reject these. The ARM backend hits this with $lane in a
964 // bunch of instructions. It is unclear what the right answer is.
966 errs() << "warning: '" << TheDef->getName() << "': "
967 << "ignoring instruction with tied operand '"
977 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
978 /// if present, from specified token.
980 extractSingletonRegisterForAsmOperand(unsigned OperandNo,
981 const AsmMatcherInfo &Info,
982 std::string &RegisterPrefix) {
983 StringRef Tok = AsmOperands[OperandNo].Token;
985 // If this token is not an isolated token, i.e., it isn't separated from
986 // other tokens (e.g. with whitespace), don't interpret it as a register name.
987 if (!AsmOperands[OperandNo].IsIsolatedToken)
990 if (RegisterPrefix.empty()) {
991 std::string LoweredTok = Tok.lower();
992 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
993 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
997 if (!Tok.startswith(RegisterPrefix))
1000 StringRef RegName = Tok.substr(RegisterPrefix.size());
1001 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
1002 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
1004 // If there is no register prefix (i.e. "%" in "%eax"), then this may
1005 // be some random non-register token, just ignore it.
1009 static std::string getEnumNameForToken(StringRef Str) {
1012 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
1014 case '*': Res += "_STAR_"; break;
1015 case '%': Res += "_PCT_"; break;
1016 case ':': Res += "_COLON_"; break;
1017 case '!': Res += "_EXCLAIM_"; break;
1018 case '.': Res += "_DOT_"; break;
1019 case '<': Res += "_LT_"; break;
1020 case '>': Res += "_GT_"; break;
1021 case '-': Res += "_MINUS_"; break;
1023 if ((*it >= 'A' && *it <= 'Z') ||
1024 (*it >= 'a' && *it <= 'z') ||
1025 (*it >= '0' && *it <= '9'))
1028 Res += "_" + utostr((unsigned) *it) + "_";
1035 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
1036 ClassInfo *&Entry = TokenClasses[Token];
1039 Classes.emplace_front();
1040 Entry = &Classes.front();
1041 Entry->Kind = ClassInfo::Token;
1042 Entry->ClassName = "Token";
1043 Entry->Name = "MCK_" + getEnumNameForToken(Token);
1044 Entry->ValueName = Token;
1045 Entry->PredicateMethod = "<invalid>";
1046 Entry->RenderMethod = "<invalid>";
1047 Entry->ParserMethod = "";
1048 Entry->DiagnosticType = "";
1055 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1057 Record *Rec = OI.Rec;
1059 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1060 return getOperandClass(Rec, SubOpIdx);
1064 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1065 if (Rec->isSubClassOf("RegisterOperand")) {
1066 // RegisterOperand may have an associated ParserMatchClass. If it does,
1067 // use it, else just fall back to the underlying register class.
1068 const RecordVal *R = Rec->getValue("ParserMatchClass");
1069 if (!R || !R->getValue())
1070 PrintFatalError("Record `" + Rec->getName() +
1071 "' does not have a ParserMatchClass!\n");
1073 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1074 Record *MatchClass = DI->getDef();
1075 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1079 // No custom match class. Just use the register class.
1080 Record *ClassRec = Rec->getValueAsDef("RegClass");
1082 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1083 "' has no associated register class!\n");
1084 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1086 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1090 if (Rec->isSubClassOf("RegisterClass")) {
1091 if (ClassInfo *CI = RegisterClassClasses[Rec])
1093 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1096 if (!Rec->isSubClassOf("Operand"))
1097 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1098 "' does not derive from class Operand!\n");
1099 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1100 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1103 PrintFatalError(Rec->getLoc(), "operand has no match class!");
1106 struct LessRegisterSet {
1107 bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const {
1108 // std::set<T> defines its own compariso "operator<", but it
1109 // performs a lexicographical comparison by T's innate comparison
1110 // for some reason. We don't want non-deterministic pointer
1111 // comparisons so use this instead.
1112 return std::lexicographical_compare(LHS.begin(), LHS.end(),
1113 RHS.begin(), RHS.end(),
1118 void AsmMatcherInfo::
1119 buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
1120 const auto &Registers = Target.getRegBank().getRegisters();
1121 auto &RegClassList = Target.getRegBank().getRegClasses();
1123 typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet;
1125 // The register sets used for matching.
1126 RegisterSetSet RegisterSets;
1128 // Gather the defined sets.
1129 for (const CodeGenRegisterClass &RC : RegClassList)
1130 RegisterSets.insert(
1131 RegisterSet(RC.getOrder().begin(), RC.getOrder().end()));
1133 // Add any required singleton sets.
1134 for (Record *Rec : SingletonRegisters) {
1135 RegisterSets.insert(RegisterSet(&Rec, &Rec + 1));
1138 // Introduce derived sets where necessary (when a register does not determine
1139 // a unique register set class), and build the mapping of registers to the set
1140 // they should classify to.
1141 std::map<Record*, RegisterSet> RegisterMap;
1142 for (const CodeGenRegister &CGR : Registers) {
1143 // Compute the intersection of all sets containing this register.
1144 RegisterSet ContainingSet;
1146 for (const RegisterSet &RS : RegisterSets) {
1147 if (!RS.count(CGR.TheDef))
1150 if (ContainingSet.empty()) {
1156 std::swap(Tmp, ContainingSet);
1157 std::insert_iterator<RegisterSet> II(ContainingSet,
1158 ContainingSet.begin());
1159 std::set_intersection(Tmp.begin(), Tmp.end(), RS.begin(), RS.end(), II,
1163 if (!ContainingSet.empty()) {
1164 RegisterSets.insert(ContainingSet);
1165 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1169 // Construct the register classes.
1170 std::map<RegisterSet, ClassInfo*, LessRegisterSet> RegisterSetClasses;
1172 for (const RegisterSet &RS : RegisterSets) {
1173 Classes.emplace_front();
1174 ClassInfo *CI = &Classes.front();
1175 CI->Kind = ClassInfo::RegisterClass0 + Index;
1176 CI->ClassName = "Reg" + utostr(Index);
1177 CI->Name = "MCK_Reg" + utostr(Index);
1179 CI->PredicateMethod = ""; // unused
1180 CI->RenderMethod = "addRegOperands";
1182 // FIXME: diagnostic type.
1183 CI->DiagnosticType = "";
1184 RegisterSetClasses.insert(std::make_pair(RS, CI));
1188 // Find the superclasses; we could compute only the subgroup lattice edges,
1189 // but there isn't really a point.
1190 for (const RegisterSet &RS : RegisterSets) {
1191 ClassInfo *CI = RegisterSetClasses[RS];
1192 for (const RegisterSet &RS2 : RegisterSets)
1194 std::includes(RS2.begin(), RS2.end(), RS.begin(), RS.end(),
1196 CI->SuperClasses.push_back(RegisterSetClasses[RS2]);
1199 // Name the register classes which correspond to a user defined RegisterClass.
1200 for (const CodeGenRegisterClass &RC : RegClassList) {
1201 // Def will be NULL for non-user defined register classes.
1202 Record *Def = RC.getDef();
1205 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(),
1206 RC.getOrder().end())];
1207 if (CI->ValueName.empty()) {
1208 CI->ClassName = RC.getName();
1209 CI->Name = "MCK_" + RC.getName();
1210 CI->ValueName = RC.getName();
1212 CI->ValueName = CI->ValueName + "," + RC.getName();
1214 RegisterClassClasses.insert(std::make_pair(Def, CI));
1217 // Populate the map for individual registers.
1218 for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(),
1219 ie = RegisterMap.end(); it != ie; ++it)
1220 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1222 // Name the register classes which correspond to singleton registers.
1223 for (Record *Rec : SingletonRegisters) {
1224 ClassInfo *CI = RegisterClasses[Rec];
1225 assert(CI && "Missing singleton register class info!");
1227 if (CI->ValueName.empty()) {
1228 CI->ClassName = Rec->getName();
1229 CI->Name = "MCK_" + Rec->getName();
1230 CI->ValueName = Rec->getName();
1232 CI->ValueName = CI->ValueName + "," + Rec->getName();
1236 void AsmMatcherInfo::buildOperandClasses() {
1237 std::vector<Record*> AsmOperands =
1238 Records.getAllDerivedDefinitions("AsmOperandClass");
1240 // Pre-populate AsmOperandClasses map.
1241 for (Record *Rec : AsmOperands) {
1242 Classes.emplace_front();
1243 AsmOperandClasses[Rec] = &Classes.front();
1247 for (Record *Rec : AsmOperands) {
1248 ClassInfo *CI = AsmOperandClasses[Rec];
1249 CI->Kind = ClassInfo::UserClass0 + Index;
1251 ListInit *Supers = Rec->getValueAsListInit("SuperClasses");
1252 for (Init *I : Supers->getValues()) {
1253 DefInit *DI = dyn_cast<DefInit>(I);
1255 PrintError(Rec->getLoc(), "Invalid super class reference!");
1259 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1261 PrintError(Rec->getLoc(), "Invalid super class reference!");
1263 CI->SuperClasses.push_back(SC);
1265 CI->ClassName = Rec->getValueAsString("Name");
1266 CI->Name = "MCK_" + CI->ClassName;
1267 CI->ValueName = Rec->getName();
1269 // Get or construct the predicate method name.
1270 Init *PMName = Rec->getValueInit("PredicateMethod");
1271 if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1272 CI->PredicateMethod = SI->getValue();
1274 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1275 CI->PredicateMethod = "is" + CI->ClassName;
1278 // Get or construct the render method name.
1279 Init *RMName = Rec->getValueInit("RenderMethod");
1280 if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1281 CI->RenderMethod = SI->getValue();
1283 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1284 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1287 // Get the parse method name or leave it as empty.
1288 Init *PRMName = Rec->getValueInit("ParserMethod");
1289 if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1290 CI->ParserMethod = SI->getValue();
1292 // Get the diagnostic type or leave it as empty.
1293 // Get the parse method name or leave it as empty.
1294 Init *DiagnosticType = Rec->getValueInit("DiagnosticType");
1295 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1296 CI->DiagnosticType = SI->getValue();
1302 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1303 CodeGenTarget &target,
1304 RecordKeeper &records)
1305 : Records(records), AsmParser(asmParser), Target(target) {
1308 /// buildOperandMatchInfo - Build the necessary information to handle user
1309 /// defined operand parsing methods.
1310 void AsmMatcherInfo::buildOperandMatchInfo() {
1312 /// Map containing a mask with all operands indices that can be found for
1313 /// that class inside a instruction.
1314 typedef std::map<ClassInfo *, unsigned, less_ptr<ClassInfo>> OpClassMaskTy;
1315 OpClassMaskTy OpClassMask;
1317 for (const auto &MI : Matchables) {
1318 OpClassMask.clear();
1320 // Keep track of all operands of this instructions which belong to the
1322 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
1323 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
1324 if (Op.Class->ParserMethod.empty())
1326 unsigned &OperandMask = OpClassMask[Op.Class];
1327 OperandMask |= (1 << i);
1330 // Generate operand match info for each mnemonic/operand class pair.
1331 for (const auto &OCM : OpClassMask) {
1332 unsigned OpMask = OCM.second;
1333 ClassInfo *CI = OCM.first;
1334 OperandMatchInfo.push_back(OperandMatchEntry::create(MI.get(), CI,
1340 void AsmMatcherInfo::buildInfo() {
1341 // Build information about all of the AssemblerPredicates.
1342 std::vector<Record*> AllPredicates =
1343 Records.getAllDerivedDefinitions("Predicate");
1344 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1345 Record *Pred = AllPredicates[i];
1346 // Ignore predicates that are not intended for the assembler.
1347 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1350 if (Pred->getName().empty())
1351 PrintFatalError(Pred->getLoc(), "Predicate has no name!");
1353 SubtargetFeatures.insert(std::make_pair(
1354 Pred, SubtargetFeatureInfo(Pred, SubtargetFeatures.size())));
1355 DEBUG(SubtargetFeatures.find(Pred)->second.dump());
1356 assert(SubtargetFeatures.size() <= 64 && "Too many subtarget features!");
1359 // Parse the instructions; we need to do this first so that we can gather the
1360 // singleton register classes.
1361 SmallPtrSet<Record*, 16> SingletonRegisters;
1362 unsigned VariantCount = Target.getAsmParserVariantCount();
1363 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1364 Record *AsmVariant = Target.getAsmParserVariant(VC);
1365 std::string CommentDelimiter =
1366 AsmVariant->getValueAsString("CommentDelimiter");
1367 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1368 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1370 for (const CodeGenInstruction *CGI : Target.instructions()) {
1372 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1373 // filter the set of instructions we consider.
1374 if (!StringRef(CGI->TheDef->getName()).startswith(MatchPrefix))
1377 // Ignore "codegen only" instructions.
1378 if (CGI->TheDef->getValueAsBit("isCodeGenOnly"))
1381 std::unique_ptr<MatchableInfo> II(new MatchableInfo(*CGI));
1383 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1385 // Ignore instructions which shouldn't be matched and diagnose invalid
1386 // instruction definitions with an error.
1387 if (!II->validate(CommentDelimiter, true))
1390 Matchables.push_back(std::move(II));
1393 // Parse all of the InstAlias definitions and stick them in the list of
1395 std::vector<Record*> AllInstAliases =
1396 Records.getAllDerivedDefinitions("InstAlias");
1397 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1398 auto Alias = llvm::make_unique<CodeGenInstAlias>(AllInstAliases[i],
1399 AsmVariantNo, Target);
1401 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1402 // filter the set of instruction aliases we consider, based on the target
1404 if (!StringRef(Alias->ResultInst->TheDef->getName())
1405 .startswith( MatchPrefix))
1408 std::unique_ptr<MatchableInfo> II(new MatchableInfo(std::move(Alias)));
1410 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1412 // Validate the alias definitions.
1413 II->validate(CommentDelimiter, false);
1415 Matchables.push_back(std::move(II));
1419 // Build info for the register classes.
1420 buildRegisterClasses(SingletonRegisters);
1422 // Build info for the user defined assembly operand classes.
1423 buildOperandClasses();
1425 // Build the information about matchables, now that we have fully formed
1427 std::vector<std::unique_ptr<MatchableInfo>> NewMatchables;
1428 for (auto &II : Matchables) {
1429 // Parse the tokens after the mnemonic.
1430 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1431 // don't precompute the loop bound.
1432 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1433 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1434 StringRef Token = Op.Token;
1436 // Check for singleton registers.
1437 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1438 Op.Class = RegisterClasses[RegRecord];
1439 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1440 "Unexpected class for singleton register");
1444 // Check for simple tokens.
1445 if (Token[0] != '$') {
1446 Op.Class = getTokenClass(Token);
1450 if (Token.size() > 1 && isdigit(Token[1])) {
1451 Op.Class = getTokenClass(Token);
1455 // Otherwise this is an operand reference.
1456 StringRef OperandName;
1457 if (Token[1] == '{')
1458 OperandName = Token.substr(2, Token.size() - 3);
1460 OperandName = Token.substr(1);
1462 if (II->DefRec.is<const CodeGenInstruction*>())
1463 buildInstructionOperandReference(II.get(), OperandName, i);
1465 buildAliasOperandReference(II.get(), OperandName, Op);
1468 if (II->DefRec.is<const CodeGenInstruction*>()) {
1469 II->buildInstructionResultOperands();
1470 // If the instruction has a two-operand alias, build up the
1471 // matchable here. We'll add them in bulk at the end to avoid
1472 // confusing this loop.
1473 std::string Constraint =
1474 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1475 if (Constraint != "") {
1476 // Start by making a copy of the original matchable.
1477 std::unique_ptr<MatchableInfo> AliasII(new MatchableInfo(*II));
1479 // Adjust it to be a two-operand alias.
1480 AliasII->formTwoOperandAlias(Constraint);
1482 // Add the alias to the matchables list.
1483 NewMatchables.push_back(std::move(AliasII));
1486 II->buildAliasResultOperands();
1488 if (!NewMatchables.empty())
1489 Matchables.insert(Matchables.end(),
1490 std::make_move_iterator(NewMatchables.begin()),
1491 std::make_move_iterator(NewMatchables.end()));
1493 // Process token alias definitions and set up the associated superclass
1495 std::vector<Record*> AllTokenAliases =
1496 Records.getAllDerivedDefinitions("TokenAlias");
1497 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1498 Record *Rec = AllTokenAliases[i];
1499 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1500 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1501 if (FromClass == ToClass)
1502 PrintFatalError(Rec->getLoc(),
1503 "error: Destination value identical to source value.");
1504 FromClass->SuperClasses.push_back(ToClass);
1507 // Reorder classes so that classes precede super classes.
1511 /// buildInstructionOperandReference - The specified operand is a reference to a
1512 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1513 void AsmMatcherInfo::
1514 buildInstructionOperandReference(MatchableInfo *II,
1515 StringRef OperandName,
1516 unsigned AsmOpIdx) {
1517 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1518 const CGIOperandList &Operands = CGI.Operands;
1519 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1521 // Map this token to an operand.
1523 if (!Operands.hasOperandNamed(OperandName, Idx))
1524 PrintFatalError(II->TheDef->getLoc(),
1525 "error: unable to find operand: '" + OperandName + "'");
1527 // If the instruction operand has multiple suboperands, but the parser
1528 // match class for the asm operand is still the default "ImmAsmOperand",
1529 // then handle each suboperand separately.
1530 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1531 Record *Rec = Operands[Idx].Rec;
1532 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1533 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1534 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1535 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1536 StringRef Token = Op->Token; // save this in case Op gets moved
1537 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1538 MatchableInfo::AsmOperand NewAsmOp(/*IsIsolatedToken=*/true, Token);
1539 NewAsmOp.SubOpIdx = SI;
1540 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1542 // Replace Op with first suboperand.
1543 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1548 // Set up the operand class.
1549 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1551 // If the named operand is tied, canonicalize it to the untied operand.
1552 // For example, something like:
1553 // (outs GPR:$dst), (ins GPR:$src)
1554 // with an asmstring of
1556 // we want to canonicalize to:
1558 // so that we know how to provide the $dst operand when filling in the result.
1560 if (Operands[Idx].MINumOperands == 1)
1561 OITied = Operands[Idx].getTiedRegister();
1563 // The tied operand index is an MIOperand index, find the operand that
1565 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1566 OperandName = Operands[Idx.first].Name;
1567 Op->SubOpIdx = Idx.second;
1570 Op->SrcOpName = OperandName;
1573 /// buildAliasOperandReference - When parsing an operand reference out of the
1574 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1575 /// operand reference is by looking it up in the result pattern definition.
1576 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1577 StringRef OperandName,
1578 MatchableInfo::AsmOperand &Op) {
1579 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1581 // Set up the operand class.
1582 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1583 if (CGA.ResultOperands[i].isRecord() &&
1584 CGA.ResultOperands[i].getName() == OperandName) {
1585 // It's safe to go with the first one we find, because CodeGenInstAlias
1586 // validates that all operands with the same name have the same record.
1587 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1588 // Use the match class from the Alias definition, not the
1589 // destination instruction, as we may have an immediate that's
1590 // being munged by the match class.
1591 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1593 Op.SrcOpName = OperandName;
1597 PrintFatalError(II->TheDef->getLoc(),
1598 "error: unable to find operand: '" + OperandName + "'");
1601 void MatchableInfo::buildInstructionResultOperands() {
1602 const CodeGenInstruction *ResultInst = getResultInst();
1604 // Loop over all operands of the result instruction, determining how to
1606 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1607 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1609 // If this is a tied operand, just copy from the previously handled operand.
1611 if (OpInfo.MINumOperands == 1)
1612 TiedOp = OpInfo.getTiedRegister();
1614 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1618 // Find out what operand from the asmparser this MCInst operand comes from.
1619 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1620 if (OpInfo.Name.empty() || SrcOperand == -1) {
1621 // This may happen for operands that are tied to a suboperand of a
1622 // complex operand. Simply use a dummy value here; nobody should
1623 // use this operand slot.
1624 // FIXME: The long term goal is for the MCOperand list to not contain
1625 // tied operands at all.
1626 ResOperands.push_back(ResOperand::getImmOp(0));
1630 // Check if the one AsmOperand populates the entire operand.
1631 unsigned NumOperands = OpInfo.MINumOperands;
1632 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1633 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1637 // Add a separate ResOperand for each suboperand.
1638 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1639 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1640 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1641 "unexpected AsmOperands for suboperands");
1642 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1647 void MatchableInfo::buildAliasResultOperands() {
1648 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1649 const CodeGenInstruction *ResultInst = getResultInst();
1651 // Loop over all operands of the result instruction, determining how to
1653 unsigned AliasOpNo = 0;
1654 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1655 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1656 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1658 // If this is a tied operand, just copy from the previously handled operand.
1660 if (OpInfo->MINumOperands == 1)
1661 TiedOp = OpInfo->getTiedRegister();
1663 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1667 // Handle all the suboperands for this operand.
1668 const std::string &OpName = OpInfo->Name;
1669 for ( ; AliasOpNo < LastOpNo &&
1670 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1671 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1673 // Find out what operand from the asmparser that this MCInst operand
1675 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1676 case CodeGenInstAlias::ResultOperand::K_Record: {
1677 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1678 int SrcOperand = findAsmOperand(Name, SubIdx);
1679 if (SrcOperand == -1)
1680 PrintFatalError(TheDef->getLoc(), "Instruction '" +
1681 TheDef->getName() + "' has operand '" + OpName +
1682 "' that doesn't appear in asm string!");
1683 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1684 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1688 case CodeGenInstAlias::ResultOperand::K_Imm: {
1689 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1690 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1693 case CodeGenInstAlias::ResultOperand::K_Reg: {
1694 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1695 ResOperands.push_back(ResOperand::getRegOp(Reg));
1703 static unsigned getConverterOperandID(const std::string &Name,
1704 SetVector<std::string> &Table,
1706 IsNew = Table.insert(Name);
1708 unsigned ID = IsNew ? Table.size() - 1 :
1709 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1711 assert(ID < Table.size());
1717 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1718 std::vector<std::unique_ptr<MatchableInfo>> &Infos,
1720 SetVector<std::string> OperandConversionKinds;
1721 SetVector<std::string> InstructionConversionKinds;
1722 std::vector<std::vector<uint8_t> > ConversionTable;
1723 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1725 // TargetOperandClass - This is the target's operand class, like X86Operand.
1726 std::string TargetOperandClass = Target.getName() + "Operand";
1728 // Write the convert function to a separate stream, so we can drop it after
1729 // the enum. We'll build up the conversion handlers for the individual
1730 // operand types opportunistically as we encounter them.
1731 std::string ConvertFnBody;
1732 raw_string_ostream CvtOS(ConvertFnBody);
1733 // Start the unified conversion function.
1734 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1735 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1736 << "unsigned Opcode,\n"
1737 << " const OperandVector"
1738 << " &Operands) {\n"
1739 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1740 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1741 << " Inst.setOpcode(Opcode);\n"
1742 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1743 << " switch (*p) {\n"
1744 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1745 << " case CVT_Reg:\n"
1746 << " static_cast<" << TargetOperandClass
1747 << "&>(*Operands[*(p + 1)]).addRegOperands(Inst, 1);\n"
1749 << " case CVT_Tied:\n"
1750 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1753 std::string OperandFnBody;
1754 raw_string_ostream OpOS(OperandFnBody);
1755 // Start the operand number lookup function.
1756 OpOS << "void " << Target.getName() << ClassName << "::\n"
1757 << "convertToMapAndConstraints(unsigned Kind,\n";
1759 OpOS << "const OperandVector &Operands) {\n"
1760 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1761 << " unsigned NumMCOperands = 0;\n"
1762 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1763 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1764 << " switch (*p) {\n"
1765 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1766 << " case CVT_Reg:\n"
1767 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1768 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
1769 << " ++NumMCOperands;\n"
1771 << " case CVT_Tied:\n"
1772 << " ++NumMCOperands;\n"
1775 // Pre-populate the operand conversion kinds with the standard always
1776 // available entries.
1777 OperandConversionKinds.insert("CVT_Done");
1778 OperandConversionKinds.insert("CVT_Reg");
1779 OperandConversionKinds.insert("CVT_Tied");
1780 enum { CVT_Done, CVT_Reg, CVT_Tied };
1782 for (auto &II : Infos) {
1783 // Check if we have a custom match function.
1784 std::string AsmMatchConverter =
1785 II->getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1786 if (!AsmMatchConverter.empty() && II->UseInstAsmMatchConverter) {
1787 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1788 II->ConversionFnKind = Signature;
1790 // Check if we have already generated this signature.
1791 if (!InstructionConversionKinds.insert(Signature))
1794 // Remember this converter for the kind enum.
1795 unsigned KindID = OperandConversionKinds.size();
1796 OperandConversionKinds.insert("CVT_" +
1797 getEnumNameForToken(AsmMatchConverter));
1799 // Add the converter row for this instruction.
1800 ConversionTable.emplace_back();
1801 ConversionTable.back().push_back(KindID);
1802 ConversionTable.back().push_back(CVT_Done);
1804 // Add the handler to the conversion driver function.
1805 CvtOS << " case CVT_"
1806 << getEnumNameForToken(AsmMatchConverter) << ":\n"
1807 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1810 // FIXME: Handle the operand number lookup for custom match functions.
1814 // Build the conversion function signature.
1815 std::string Signature = "Convert";
1817 std::vector<uint8_t> ConversionRow;
1819 // Compute the convert enum and the case body.
1820 MaxRowLength = std::max(MaxRowLength, II->ResOperands.size()*2 + 1 );
1822 for (unsigned i = 0, e = II->ResOperands.size(); i != e; ++i) {
1823 const MatchableInfo::ResOperand &OpInfo = II->ResOperands[i];
1825 // Generate code to populate each result operand.
1826 switch (OpInfo.Kind) {
1827 case MatchableInfo::ResOperand::RenderAsmOperand: {
1828 // This comes from something we parsed.
1829 const MatchableInfo::AsmOperand &Op =
1830 II->AsmOperands[OpInfo.AsmOperandNum];
1832 // Registers are always converted the same, don't duplicate the
1833 // conversion function based on them.
1836 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1838 Signature += utostr(OpInfo.MINumOperands);
1839 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1841 // Add the conversion kind, if necessary, and get the associated ID
1842 // the index of its entry in the vector).
1843 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1844 Op.Class->RenderMethod);
1845 Name = getEnumNameForToken(Name);
1847 bool IsNewConverter = false;
1848 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1851 // Add the operand entry to the instruction kind conversion row.
1852 ConversionRow.push_back(ID);
1853 ConversionRow.push_back(OpInfo.AsmOperandNum + 1);
1855 if (!IsNewConverter)
1858 // This is a new operand kind. Add a handler for it to the
1859 // converter driver.
1860 CvtOS << " case " << Name << ":\n"
1861 << " static_cast<" << TargetOperandClass
1862 << "&>(*Operands[*(p + 1)])." << Op.Class->RenderMethod
1863 << "(Inst, " << OpInfo.MINumOperands << ");\n"
1866 // Add a handler for the operand number lookup.
1867 OpOS << " case " << Name << ":\n"
1868 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
1870 if (Op.Class->isRegisterClass())
1871 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
1873 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
1874 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
1878 case MatchableInfo::ResOperand::TiedOperand: {
1879 // If this operand is tied to a previous one, just copy the MCInst
1880 // operand from the earlier one.We can only tie single MCOperand values.
1881 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1882 unsigned TiedOp = OpInfo.TiedOperandNum;
1883 assert(i > TiedOp && "Tied operand precedes its target!");
1884 Signature += "__Tie" + utostr(TiedOp);
1885 ConversionRow.push_back(CVT_Tied);
1886 ConversionRow.push_back(TiedOp);
1889 case MatchableInfo::ResOperand::ImmOperand: {
1890 int64_t Val = OpInfo.ImmVal;
1891 std::string Ty = "imm_" + itostr(Val);
1892 Ty = getEnumNameForToken(Ty);
1893 Signature += "__" + Ty;
1895 std::string Name = "CVT_" + Ty;
1896 bool IsNewConverter = false;
1897 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1899 // Add the operand entry to the instruction kind conversion row.
1900 ConversionRow.push_back(ID);
1901 ConversionRow.push_back(0);
1903 if (!IsNewConverter)
1906 CvtOS << " case " << Name << ":\n"
1907 << " Inst.addOperand(MCOperand::createImm(" << Val << "));\n"
1910 OpOS << " case " << Name << ":\n"
1911 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1912 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
1913 << " ++NumMCOperands;\n"
1917 case MatchableInfo::ResOperand::RegOperand: {
1918 std::string Reg, Name;
1919 if (!OpInfo.Register) {
1923 Reg = getQualifiedName(OpInfo.Register);
1924 Name = "reg" + OpInfo.Register->getName();
1926 Signature += "__" + Name;
1927 Name = "CVT_" + Name;
1928 bool IsNewConverter = false;
1929 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1931 // Add the operand entry to the instruction kind conversion row.
1932 ConversionRow.push_back(ID);
1933 ConversionRow.push_back(0);
1935 if (!IsNewConverter)
1937 CvtOS << " case " << Name << ":\n"
1938 << " Inst.addOperand(MCOperand::createReg(" << Reg << "));\n"
1941 OpOS << " case " << Name << ":\n"
1942 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1943 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
1944 << " ++NumMCOperands;\n"
1950 // If there were no operands, add to the signature to that effect
1951 if (Signature == "Convert")
1952 Signature += "_NoOperands";
1954 II->ConversionFnKind = Signature;
1956 // Save the signature. If we already have it, don't add a new row
1958 if (!InstructionConversionKinds.insert(Signature))
1961 // Add the row to the table.
1962 ConversionTable.push_back(ConversionRow);
1965 // Finish up the converter driver function.
1966 CvtOS << " }\n }\n}\n\n";
1968 // Finish up the operand number lookup function.
1969 OpOS << " }\n }\n}\n\n";
1971 OS << "namespace {\n";
1973 // Output the operand conversion kind enum.
1974 OS << "enum OperatorConversionKind {\n";
1975 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i)
1976 OS << " " << OperandConversionKinds[i] << ",\n";
1977 OS << " CVT_NUM_CONVERTERS\n";
1980 // Output the instruction conversion kind enum.
1981 OS << "enum InstructionConversionKind {\n";
1982 for (SetVector<std::string>::const_iterator
1983 i = InstructionConversionKinds.begin(),
1984 e = InstructionConversionKinds.end(); i != e; ++i)
1985 OS << " " << *i << ",\n";
1986 OS << " CVT_NUM_SIGNATURES\n";
1990 OS << "} // end anonymous namespace\n\n";
1992 // Output the conversion table.
1993 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
1994 << MaxRowLength << "] = {\n";
1996 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
1997 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
1998 OS << " // " << InstructionConversionKinds[Row] << "\n";
2000 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
2001 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
2002 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
2003 OS << "CVT_Done },\n";
2008 // Spit out the conversion driver function.
2011 // Spit out the operand number lookup function.
2015 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
2016 static void emitMatchClassEnumeration(CodeGenTarget &Target,
2017 std::forward_list<ClassInfo> &Infos,
2019 OS << "namespace {\n\n";
2021 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
2022 << "/// instruction matching.\n";
2023 OS << "enum MatchClassKind {\n";
2024 OS << " InvalidMatchClass = 0,\n";
2025 for (const auto &CI : Infos) {
2026 OS << " " << CI.Name << ", // ";
2027 if (CI.Kind == ClassInfo::Token) {
2028 OS << "'" << CI.ValueName << "'\n";
2029 } else if (CI.isRegisterClass()) {
2030 if (!CI.ValueName.empty())
2031 OS << "register class '" << CI.ValueName << "'\n";
2033 OS << "derived register class\n";
2035 OS << "user defined class '" << CI.ValueName << "'\n";
2038 OS << " NumMatchClassKinds\n";
2044 /// emitValidateOperandClass - Emit the function to validate an operand class.
2045 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2047 OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, "
2048 << "MatchClassKind Kind) {\n";
2049 OS << " " << Info.Target.getName() << "Operand &Operand = ("
2050 << Info.Target.getName() << "Operand&)GOp;\n";
2052 // The InvalidMatchClass is not to match any operand.
2053 OS << " if (Kind == InvalidMatchClass)\n";
2054 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2056 // Check for Token operands first.
2057 // FIXME: Use a more specific diagnostic type.
2058 OS << " if (Operand.isToken())\n";
2059 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2060 << " MCTargetAsmParser::Match_Success :\n"
2061 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2063 // Check the user classes. We don't care what order since we're only
2064 // actually matching against one of them.
2065 for (const auto &CI : Info.Classes) {
2066 if (!CI.isUserClass())
2069 OS << " // '" << CI.ClassName << "' class\n";
2070 OS << " if (Kind == " << CI.Name << ") {\n";
2071 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2072 OS << " return MCTargetAsmParser::Match_Success;\n";
2073 if (!CI.DiagnosticType.empty())
2074 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2075 << CI.DiagnosticType << ";\n";
2079 // Check for register operands, including sub-classes.
2080 OS << " if (Operand.isReg()) {\n";
2081 OS << " MatchClassKind OpKind;\n";
2082 OS << " switch (Operand.getReg()) {\n";
2083 OS << " default: OpKind = InvalidMatchClass; break;\n";
2084 for (const auto &RC : Info.RegisterClasses)
2085 OS << " case " << Info.Target.getName() << "::"
2086 << RC.first->getName() << ": OpKind = " << RC.second->Name
2089 OS << " return isSubclass(OpKind, Kind) ? "
2090 << "MCTargetAsmParser::Match_Success :\n "
2091 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2093 // Generic fallthrough match failure case for operands that don't have
2094 // specialized diagnostic types.
2095 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2099 /// emitIsSubclass - Emit the subclass predicate function.
2100 static void emitIsSubclass(CodeGenTarget &Target,
2101 std::forward_list<ClassInfo> &Infos,
2103 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2104 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2105 OS << " if (A == B)\n";
2106 OS << " return true;\n\n";
2109 raw_string_ostream SS(OStr);
2111 SS << " switch (A) {\n";
2112 SS << " default:\n";
2113 SS << " return false;\n";
2114 for (const auto &A : Infos) {
2115 std::vector<StringRef> SuperClasses;
2116 for (const auto &B : Infos) {
2117 if (&A != &B && A.isSubsetOf(B))
2118 SuperClasses.push_back(B.Name);
2121 if (SuperClasses.empty())
2125 SS << "\n case " << A.Name << ":\n";
2127 if (SuperClasses.size() == 1) {
2128 SS << " return B == " << SuperClasses.back().str() << ";\n";
2132 if (!SuperClasses.empty()) {
2133 SS << " switch (B) {\n";
2134 SS << " default: return false;\n";
2135 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
2136 SS << " case " << SuperClasses[i].str() << ": return true;\n";
2139 // No case statement to emit
2140 SS << " return false;\n";
2145 // If there were case statements emitted into the string stream, write them
2146 // to the output stream, otherwise write the default.
2150 OS << " return false;\n";
2155 /// emitMatchTokenString - Emit the function to match a token string to the
2156 /// appropriate match class value.
2157 static void emitMatchTokenString(CodeGenTarget &Target,
2158 std::forward_list<ClassInfo> &Infos,
2160 // Construct the match list.
2161 std::vector<StringMatcher::StringPair> Matches;
2162 for (const auto &CI : Infos) {
2163 if (CI.Kind == ClassInfo::Token)
2164 Matches.emplace_back(CI.ValueName, "return " + CI.Name + ";");
2167 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2169 StringMatcher("Name", Matches, OS).Emit();
2171 OS << " return InvalidMatchClass;\n";
2175 /// emitMatchRegisterName - Emit the function to match a string to the target
2176 /// specific register enum.
2177 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2179 // Construct the match list.
2180 std::vector<StringMatcher::StringPair> Matches;
2181 const auto &Regs = Target.getRegBank().getRegisters();
2182 for (const CodeGenRegister &Reg : Regs) {
2183 if (Reg.TheDef->getValueAsString("AsmName").empty())
2186 Matches.emplace_back(Reg.TheDef->getValueAsString("AsmName"),
2187 "return " + utostr(Reg.EnumValue) + ";");
2190 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2192 StringMatcher("Name", Matches, OS).Emit();
2194 OS << " return 0;\n";
2198 static const char *getMinimalTypeForRange(uint64_t Range) {
2199 assert(Range <= 0xFFFFFFFFFFFFFFFFULL && "Enum too large");
2200 if (Range > 0xFFFFFFFFULL)
2209 static const char *getMinimalRequiredFeaturesType(const AsmMatcherInfo &Info) {
2210 uint64_t MaxIndex = Info.SubtargetFeatures.size();
2213 return getMinimalTypeForRange(1ULL << MaxIndex);
2216 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2218 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2220 OS << "// Flags for subtarget features that participate in "
2221 << "instruction matching.\n";
2222 OS << "enum SubtargetFeatureFlag : " << getMinimalRequiredFeaturesType(Info)
2224 for (const auto &SF : Info.SubtargetFeatures) {
2225 const SubtargetFeatureInfo &SFI = SF.second;
2226 OS << " " << SFI.getEnumName() << " = (1ULL << " << SFI.Index << "),\n";
2228 OS << " Feature_None = 0\n";
2232 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2233 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2234 // Get the set of diagnostic types from all of the operand classes.
2235 std::set<StringRef> Types;
2236 for (std::map<Record*, ClassInfo*>::const_iterator
2237 I = Info.AsmOperandClasses.begin(),
2238 E = Info.AsmOperandClasses.end(); I != E; ++I) {
2239 if (!I->second->DiagnosticType.empty())
2240 Types.insert(I->second->DiagnosticType);
2243 if (Types.empty()) return;
2245 // Now emit the enum entries.
2246 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end();
2248 OS << " Match_" << *I << ",\n";
2249 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2252 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2253 /// user-level name for a subtarget feature.
2254 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2255 OS << "// User-level names for subtarget features that participate in\n"
2256 << "// instruction matching.\n"
2257 << "static const char *getSubtargetFeatureName(uint64_t Val) {\n";
2258 if (!Info.SubtargetFeatures.empty()) {
2259 OS << " switch(Val) {\n";
2260 for (const auto &SF : Info.SubtargetFeatures) {
2261 const SubtargetFeatureInfo &SFI = SF.second;
2262 // FIXME: Totally just a placeholder name to get the algorithm working.
2263 OS << " case " << SFI.getEnumName() << ": return \""
2264 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2266 OS << " default: return \"(unknown)\";\n";
2269 // Nothing to emit, so skip the switch
2270 OS << " return \"(unknown)\";\n";
2275 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2276 /// available features given a subtarget.
2277 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2279 std::string ClassName =
2280 Info.AsmParser->getValueAsString("AsmParserClassName");
2282 OS << "uint64_t " << Info.Target.getName() << ClassName << "::\n"
2283 << "ComputeAvailableFeatures(const FeatureBitset& FB) const {\n";
2284 OS << " uint64_t Features = 0;\n";
2285 for (const auto &SF : Info.SubtargetFeatures) {
2286 const SubtargetFeatureInfo &SFI = SF.second;
2289 std::string CondStorage =
2290 SFI.TheDef->getValueAsString("AssemblerCondString");
2291 StringRef Conds = CondStorage;
2292 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2299 StringRef Cond = Comma.first;
2300 if (Cond[0] == '!') {
2302 Cond = Cond.substr(1);
2308 OS << "FB[" << Info.Target.getName() << "::" << Cond << "])";
2310 if (Comma.second.empty())
2314 Comma = Comma.second.split(',');
2318 OS << " Features |= " << SFI.getEnumName() << ";\n";
2320 OS << " return Features;\n";
2324 static std::string GetAliasRequiredFeatures(Record *R,
2325 const AsmMatcherInfo &Info) {
2326 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2328 unsigned NumFeatures = 0;
2329 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2330 const SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2333 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2334 "' is not marked as an AssemblerPredicate!");
2339 Result += F->getEnumName();
2343 if (NumFeatures > 1)
2344 Result = '(' + Result + ')';
2348 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2349 std::vector<Record*> &Aliases,
2350 unsigned Indent = 0,
2351 StringRef AsmParserVariantName = StringRef()){
2352 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2353 // iteration order of the map is stable.
2354 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2356 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2357 Record *R = Aliases[i];
2358 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2359 std::string AsmVariantName = R->getValueAsString("AsmVariantName");
2360 if (AsmVariantName != AsmParserVariantName)
2362 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2364 if (AliasesFromMnemonic.empty())
2367 // Process each alias a "from" mnemonic at a time, building the code executed
2368 // by the string remapper.
2369 std::vector<StringMatcher::StringPair> Cases;
2370 for (std::map<std::string, std::vector<Record*> >::iterator
2371 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2373 const std::vector<Record*> &ToVec = I->second;
2375 // Loop through each alias and emit code that handles each case. If there
2376 // are two instructions without predicates, emit an error. If there is one,
2378 std::string MatchCode;
2379 int AliasWithNoPredicate = -1;
2381 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2382 Record *R = ToVec[i];
2383 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2385 // If this unconditionally matches, remember it for later and diagnose
2387 if (FeatureMask.empty()) {
2388 if (AliasWithNoPredicate != -1) {
2389 // We can't have two aliases from the same mnemonic with no predicate.
2390 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2391 "two MnemonicAliases with the same 'from' mnemonic!");
2392 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2395 AliasWithNoPredicate = i;
2398 if (R->getValueAsString("ToMnemonic") == I->first)
2399 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2401 if (!MatchCode.empty())
2402 MatchCode += "else ";
2403 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2404 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2407 if (AliasWithNoPredicate != -1) {
2408 Record *R = ToVec[AliasWithNoPredicate];
2409 if (!MatchCode.empty())
2410 MatchCode += "else\n ";
2411 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2414 MatchCode += "return;";
2416 Cases.push_back(std::make_pair(I->first, MatchCode));
2418 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2421 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2422 /// emit a function for them and return true, otherwise return false.
2423 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2424 CodeGenTarget &Target) {
2425 // Ignore aliases when match-prefix is set.
2426 if (!MatchPrefix.empty())
2429 std::vector<Record*> Aliases =
2430 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2431 if (Aliases.empty()) return false;
2433 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2434 "uint64_t Features, unsigned VariantID) {\n";
2435 OS << " switch (VariantID) {\n";
2436 unsigned VariantCount = Target.getAsmParserVariantCount();
2437 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2438 Record *AsmVariant = Target.getAsmParserVariant(VC);
2439 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2440 std::string AsmParserVariantName = AsmVariant->getValueAsString("Name");
2441 OS << " case " << AsmParserVariantNo << ":\n";
2442 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2443 AsmParserVariantName);
2448 // Emit aliases that apply to all variants.
2449 emitMnemonicAliasVariant(OS, Info, Aliases);
2456 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2457 const AsmMatcherInfo &Info, StringRef ClassName,
2458 StringToOffsetTable &StringTable,
2459 unsigned MaxMnemonicIndex) {
2460 unsigned MaxMask = 0;
2461 for (std::vector<OperandMatchEntry>::const_iterator it =
2462 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2464 MaxMask |= it->OperandMask;
2467 // Emit the static custom operand parsing table;
2468 OS << "namespace {\n";
2469 OS << " struct OperandMatchEntry {\n";
2470 OS << " " << getMinimalRequiredFeaturesType(Info)
2471 << " RequiredFeatures;\n";
2472 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2474 OS << " " << getMinimalTypeForRange(std::distance(
2475 Info.Classes.begin(), Info.Classes.end())) << " Class;\n";
2476 OS << " " << getMinimalTypeForRange(MaxMask)
2477 << " OperandMask;\n\n";
2478 OS << " StringRef getMnemonic() const {\n";
2479 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2480 OS << " MnemonicTable[Mnemonic]);\n";
2484 OS << " // Predicate for searching for an opcode.\n";
2485 OS << " struct LessOpcodeOperand {\n";
2486 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2487 OS << " return LHS.getMnemonic() < RHS;\n";
2489 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2490 OS << " return LHS < RHS.getMnemonic();\n";
2492 OS << " bool operator()(const OperandMatchEntry &LHS,";
2493 OS << " const OperandMatchEntry &RHS) {\n";
2494 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2498 OS << "} // end anonymous namespace.\n\n";
2500 OS << "static const OperandMatchEntry OperandMatchTable["
2501 << Info.OperandMatchInfo.size() << "] = {\n";
2503 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2504 for (std::vector<OperandMatchEntry>::const_iterator it =
2505 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2507 const OperandMatchEntry &OMI = *it;
2508 const MatchableInfo &II = *OMI.MI;
2512 // Write the required features mask.
2513 if (!II.RequiredFeatures.empty()) {
2514 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2516 OS << II.RequiredFeatures[i]->getEnumName();
2521 // Store a pascal-style length byte in the mnemonic.
2522 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2523 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2524 << " /* " << II.Mnemonic << " */, ";
2528 OS << ", " << OMI.OperandMask;
2530 bool printComma = false;
2531 for (int i = 0, e = 31; i !=e; ++i)
2532 if (OMI.OperandMask & (1 << i)) {
2544 // Emit the operand class switch to call the correct custom parser for
2545 // the found operand class.
2546 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2547 << Target.getName() << ClassName << "::\n"
2548 << "tryCustomParseOperand(OperandVector"
2549 << " &Operands,\n unsigned MCK) {\n\n"
2550 << " switch(MCK) {\n";
2552 for (const auto &CI : Info.Classes) {
2553 if (CI.ParserMethod.empty())
2555 OS << " case " << CI.Name << ":\n"
2556 << " return " << CI.ParserMethod << "(Operands);\n";
2559 OS << " default:\n";
2560 OS << " return MatchOperand_NoMatch;\n";
2562 OS << " return MatchOperand_NoMatch;\n";
2565 // Emit the static custom operand parser. This code is very similar with
2566 // the other matcher. Also use MatchResultTy here just in case we go for
2567 // a better error handling.
2568 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2569 << Target.getName() << ClassName << "::\n"
2570 << "MatchOperandParserImpl(OperandVector"
2571 << " &Operands,\n StringRef Mnemonic) {\n";
2573 // Emit code to get the available features.
2574 OS << " // Get the current feature set.\n";
2575 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2577 OS << " // Get the next operand index.\n";
2578 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2580 // Emit code to search the table.
2581 OS << " // Search the table.\n";
2582 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2583 OS << " MnemonicRange =\n";
2584 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2585 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2586 << " LessOpcodeOperand());\n\n";
2588 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2589 OS << " return MatchOperand_NoMatch;\n\n";
2591 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2592 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2594 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2595 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2597 // Emit check that the required features are available.
2598 OS << " // check if the available features match\n";
2599 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2600 << "!= it->RequiredFeatures) {\n";
2601 OS << " continue;\n";
2604 // Emit check to ensure the operand number matches.
2605 OS << " // check if the operand in question has a custom parser.\n";
2606 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2607 OS << " continue;\n\n";
2609 // Emit call to the custom parser method
2610 OS << " // call custom parse method to handle the operand\n";
2611 OS << " OperandMatchResultTy Result = ";
2612 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2613 OS << " if (Result != MatchOperand_NoMatch)\n";
2614 OS << " return Result;\n";
2617 OS << " // Okay, we had no match.\n";
2618 OS << " return MatchOperand_NoMatch;\n";
2622 void AsmMatcherEmitter::run(raw_ostream &OS) {
2623 CodeGenTarget Target(Records);
2624 Record *AsmParser = Target.getAsmParser();
2625 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2627 // Compute the information on the instructions to match.
2628 AsmMatcherInfo Info(AsmParser, Target, Records);
2631 // Sort the instruction table using the partial order on classes. We use
2632 // stable_sort to ensure that ambiguous instructions are still
2633 // deterministically ordered.
2634 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2635 [](const std::unique_ptr<MatchableInfo> &a,
2636 const std::unique_ptr<MatchableInfo> &b){
2639 DEBUG_WITH_TYPE("instruction_info", {
2640 for (const auto &MI : Info.Matchables)
2644 // Check for ambiguous matchables.
2645 DEBUG_WITH_TYPE("ambiguous_instrs", {
2646 unsigned NumAmbiguous = 0;
2647 for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
2649 for (auto J = std::next(I); J != E; ++J) {
2650 const MatchableInfo &A = **I;
2651 const MatchableInfo &B = **J;
2653 if (A.couldMatchAmbiguouslyWith(B)) {
2654 errs() << "warning: ambiguous matchables:\n";
2656 errs() << "\nis incomparable with:\n";
2664 errs() << "warning: " << NumAmbiguous
2665 << " ambiguous matchables!\n";
2668 // Compute the information on the custom operand parsing.
2669 Info.buildOperandMatchInfo();
2671 // Write the output.
2673 // Information for the class declaration.
2674 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2675 OS << "#undef GET_ASSEMBLER_HEADER\n";
2676 OS << " // This should be included into the middle of the declaration of\n";
2677 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2678 OS << " uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;\n";
2679 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2680 << "unsigned Opcode,\n"
2681 << " const OperandVector "
2683 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2684 OS << " const OperandVector &Operands) override;\n";
2685 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) override;\n";
2686 OS << " unsigned MatchInstructionImpl(const OperandVector &Operands,\n"
2687 << " MCInst &Inst,\n"
2688 << " uint64_t &ErrorInfo,"
2689 << " bool matchingInlineAsm,\n"
2690 << " unsigned VariantID = 0);\n";
2692 if (!Info.OperandMatchInfo.empty()) {
2693 OS << "\n enum OperandMatchResultTy {\n";
2694 OS << " MatchOperand_Success, // operand matched successfully\n";
2695 OS << " MatchOperand_NoMatch, // operand did not match\n";
2696 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2698 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2699 OS << " OperandVector &Operands,\n";
2700 OS << " StringRef Mnemonic);\n";
2702 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2703 OS << " OperandVector &Operands,\n";
2704 OS << " unsigned MCK);\n\n";
2707 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2709 // Emit the operand match diagnostic enum names.
2710 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2711 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2712 emitOperandDiagnosticTypes(Info, OS);
2713 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2716 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2717 OS << "#undef GET_REGISTER_MATCHER\n\n";
2719 // Emit the subtarget feature enumeration.
2720 emitSubtargetFeatureFlagEnumeration(Info, OS);
2722 // Emit the function to match a register name to number.
2723 // This should be omitted for Mips target
2724 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2725 emitMatchRegisterName(Target, AsmParser, OS);
2727 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2729 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2730 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2732 // Generate the helper function to get the names for subtarget features.
2733 emitGetSubtargetFeatureName(Info, OS);
2735 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2737 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2738 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2740 // Generate the function that remaps for mnemonic aliases.
2741 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
2743 // Generate the convertToMCInst function to convert operands into an MCInst.
2744 // Also, generate the convertToMapAndConstraints function for MS-style inline
2745 // assembly. The latter doesn't actually generate a MCInst.
2746 emitConvertFuncs(Target, ClassName, Info.Matchables, OS);
2748 // Emit the enumeration for classes which participate in matching.
2749 emitMatchClassEnumeration(Target, Info.Classes, OS);
2751 // Emit the routine to match token strings to their match class.
2752 emitMatchTokenString(Target, Info.Classes, OS);
2754 // Emit the subclass predicate routine.
2755 emitIsSubclass(Target, Info.Classes, OS);
2757 // Emit the routine to validate an operand against a match class.
2758 emitValidateOperandClass(Info, OS);
2760 // Emit the available features compute function.
2761 emitComputeAvailableFeatures(Info, OS);
2764 StringToOffsetTable StringTable;
2766 size_t MaxNumOperands = 0;
2767 unsigned MaxMnemonicIndex = 0;
2768 bool HasDeprecation = false;
2769 for (const auto &MI : Info.Matchables) {
2770 MaxNumOperands = std::max(MaxNumOperands, MI->AsmOperands.size());
2771 HasDeprecation |= MI->HasDeprecation;
2773 // Store a pascal-style length byte in the mnemonic.
2774 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2775 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2776 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2779 OS << "static const char *const MnemonicTable =\n";
2780 StringTable.EmitString(OS);
2783 // Emit the static match table; unused classes get initalized to 0 which is
2784 // guaranteed to be InvalidMatchClass.
2786 // FIXME: We can reduce the size of this table very easily. First, we change
2787 // it so that store the kinds in separate bit-fields for each index, which
2788 // only needs to be the max width used for classes at that index (we also need
2789 // to reject based on this during classification). If we then make sure to
2790 // order the match kinds appropriately (putting mnemonics last), then we
2791 // should only end up using a few bits for each class, especially the ones
2792 // following the mnemonic.
2793 OS << "namespace {\n";
2794 OS << " struct MatchEntry {\n";
2795 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2797 OS << " uint16_t Opcode;\n";
2798 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2800 OS << " " << getMinimalRequiredFeaturesType(Info)
2801 << " RequiredFeatures;\n";
2802 OS << " " << getMinimalTypeForRange(
2803 std::distance(Info.Classes.begin(), Info.Classes.end()))
2804 << " Classes[" << MaxNumOperands << "];\n";
2805 OS << " StringRef getMnemonic() const {\n";
2806 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2807 OS << " MnemonicTable[Mnemonic]);\n";
2811 OS << " // Predicate for searching for an opcode.\n";
2812 OS << " struct LessOpcode {\n";
2813 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2814 OS << " return LHS.getMnemonic() < RHS;\n";
2816 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2817 OS << " return LHS < RHS.getMnemonic();\n";
2819 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2820 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2824 OS << "} // end anonymous namespace.\n\n";
2826 unsigned VariantCount = Target.getAsmParserVariantCount();
2827 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2828 Record *AsmVariant = Target.getAsmParserVariant(VC);
2829 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2831 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
2833 for (const auto &MI : Info.Matchables) {
2834 if (MI->AsmVariantID != AsmVariantNo)
2837 // Store a pascal-style length byte in the mnemonic.
2838 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2839 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2840 << " /* " << MI->Mnemonic << " */, "
2841 << Target.getName() << "::"
2842 << MI->getResultInst()->TheDef->getName() << ", "
2843 << MI->ConversionFnKind << ", ";
2845 // Write the required features mask.
2846 if (!MI->RequiredFeatures.empty()) {
2847 for (unsigned i = 0, e = MI->RequiredFeatures.size(); i != e; ++i) {
2849 OS << MI->RequiredFeatures[i]->getEnumName();
2855 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
2856 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
2859 OS << Op.Class->Name;
2867 // A method to determine if a mnemonic is in the list.
2868 OS << "bool " << Target.getName() << ClassName << "::\n"
2869 << "mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {\n";
2870 OS << " // Find the appropriate table for this asm variant.\n";
2871 OS << " const MatchEntry *Start, *End;\n";
2872 OS << " switch (VariantID) {\n";
2873 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
2874 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2875 Record *AsmVariant = Target.getAsmParserVariant(VC);
2876 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2877 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2878 << "); End = std::end(MatchTable" << VC << "); break;\n";
2881 OS << " // Search the table.\n";
2882 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2883 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n";
2884 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2887 // Finally, build the match function.
2888 OS << "unsigned " << Target.getName() << ClassName << "::\n"
2889 << "MatchInstructionImpl(const OperandVector &Operands,\n";
2890 OS << " MCInst &Inst, uint64_t &ErrorInfo,\n"
2891 << " bool matchingInlineAsm, unsigned VariantID) {\n";
2893 OS << " // Eliminate obvious mismatches.\n";
2894 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2895 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2896 OS << " return Match_InvalidOperand;\n";
2899 // Emit code to get the available features.
2900 OS << " // Get the current feature set.\n";
2901 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2903 OS << " // Get the instruction mnemonic, which is the first token.\n";
2904 OS << " StringRef Mnemonic = ((" << Target.getName()
2905 << "Operand&)*Operands[0]).getToken();\n\n";
2907 if (HasMnemonicAliases) {
2908 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2909 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
2912 // Emit code to compute the class list for this operand vector.
2913 OS << " // Some state to try to produce better error messages.\n";
2914 OS << " bool HadMatchOtherThanFeatures = false;\n";
2915 OS << " bool HadMatchOtherThanPredicate = false;\n";
2916 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2917 OS << " uint64_t MissingFeatures = ~0ULL;\n";
2918 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2919 OS << " // wrong for all instances of the instruction.\n";
2920 OS << " ErrorInfo = ~0ULL;\n";
2922 // Emit code to search the table.
2923 OS << " // Find the appropriate table for this asm variant.\n";
2924 OS << " const MatchEntry *Start, *End;\n";
2925 OS << " switch (VariantID) {\n";
2926 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
2927 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2928 Record *AsmVariant = Target.getAsmParserVariant(VC);
2929 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2930 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2931 << "); End = std::end(MatchTable" << VC << "); break;\n";
2934 OS << " // Search the table.\n";
2935 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2936 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
2938 OS << " // Return a more specific error code if no mnemonics match.\n";
2939 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2940 OS << " return Match_MnemonicFail;\n\n";
2942 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2943 << "*ie = MnemonicRange.second;\n";
2944 OS << " it != ie; ++it) {\n";
2946 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2947 OS << " assert(Mnemonic == it->getMnemonic());\n";
2949 // Emit check that the subclasses match.
2950 OS << " bool OperandsValid = true;\n";
2951 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2952 OS << " if (i + 1 >= Operands.size()) {\n";
2953 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2954 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n";
2957 OS << " unsigned Diag = validateOperandClass(*Operands[i+1],\n";
2959 OS << "(MatchClassKind)it->Classes[i]);\n";
2960 OS << " if (Diag == Match_Success)\n";
2961 OS << " continue;\n";
2962 OS << " // If the generic handler indicates an invalid operand\n";
2963 OS << " // failure, check for a special case.\n";
2964 OS << " if (Diag == Match_InvalidOperand) {\n";
2965 OS << " Diag = validateTargetOperandClass(*Operands[i+1],\n";
2967 OS << "(MatchClassKind)it->Classes[i]);\n";
2968 OS << " if (Diag == Match_Success)\n";
2969 OS << " continue;\n";
2971 OS << " // If this operand is broken for all of the instances of this\n";
2972 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2973 OS << " // If we already had a match that only failed due to a\n";
2974 OS << " // target predicate, that diagnostic is preferred.\n";
2975 OS << " if (!HadMatchOtherThanPredicate &&\n";
2976 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n";
2977 OS << " ErrorInfo = i+1;\n";
2978 OS << " // InvalidOperand is the default. Prefer specificity.\n";
2979 OS << " if (Diag != Match_InvalidOperand)\n";
2980 OS << " RetCode = Diag;\n";
2982 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2983 OS << " OperandsValid = false;\n";
2987 OS << " if (!OperandsValid) continue;\n";
2989 // Emit check that the required features are available.
2990 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2991 << "!= it->RequiredFeatures) {\n";
2992 OS << " HadMatchOtherThanFeatures = true;\n";
2993 OS << " uint64_t NewMissingFeatures = it->RequiredFeatures & "
2994 "~AvailableFeatures;\n";
2995 OS << " if (countPopulation(NewMissingFeatures) <=\n"
2996 " countPopulation(MissingFeatures))\n";
2997 OS << " MissingFeatures = NewMissingFeatures;\n";
2998 OS << " continue;\n";
3001 OS << " Inst.clear();\n\n";
3002 OS << " if (matchingInlineAsm) {\n";
3003 OS << " Inst.setOpcode(it->Opcode);\n";
3004 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
3005 OS << " return Match_Success;\n";
3007 OS << " // We have selected a definite instruction, convert the parsed\n"
3008 << " // operands into the appropriate MCInst.\n";
3009 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
3012 // Verify the instruction with the target-specific match predicate function.
3013 OS << " // We have a potential match. Check the target predicate to\n"
3014 << " // handle any context sensitive constraints.\n"
3015 << " unsigned MatchResult;\n"
3016 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
3017 << " Match_Success) {\n"
3018 << " Inst.clear();\n"
3019 << " RetCode = MatchResult;\n"
3020 << " HadMatchOtherThanPredicate = true;\n"
3024 // Call the post-processing function, if used.
3025 std::string InsnCleanupFn =
3026 AsmParser->getValueAsString("AsmParserInstCleanup");
3027 if (!InsnCleanupFn.empty())
3028 OS << " " << InsnCleanupFn << "(Inst);\n";
3030 if (HasDeprecation) {
3031 OS << " std::string Info;\n";
3032 OS << " if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, STI, Info)) {\n";
3033 OS << " SMLoc Loc = ((" << Target.getName()
3034 << "Operand&)*Operands[0]).getStartLoc();\n";
3035 OS << " getParser().Warning(Loc, Info, None);\n";
3039 OS << " return Match_Success;\n";
3042 OS << " // Okay, we had no match. Try to return a useful error code.\n";
3043 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
3044 OS << " return RetCode;\n\n";
3045 OS << " // Missing feature matches return which features were missing\n";
3046 OS << " ErrorInfo = MissingFeatures;\n";
3047 OS << " return Match_MissingFeature;\n";
3050 if (!Info.OperandMatchInfo.empty())
3051 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
3054 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
3059 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
3060 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
3061 AsmMatcherEmitter(RK).run(OS);
3064 } // End llvm namespace