1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "StringToOffsetTable.h"
101 #include "llvm/ADT/OwningPtr.h"
102 #include "llvm/ADT/PointerUnion.h"
103 #include "llvm/ADT/STLExtras.h"
104 #include "llvm/ADT/SmallPtrSet.h"
105 #include "llvm/ADT/SmallVector.h"
106 #include "llvm/ADT/StringExtras.h"
107 #include "llvm/Support/CommandLine.h"
108 #include "llvm/Support/Debug.h"
109 #include "llvm/Support/ErrorHandling.h"
110 #include "llvm/TableGen/Error.h"
111 #include "llvm/TableGen/Record.h"
112 #include "llvm/TableGen/StringMatcher.h"
113 #include "llvm/TableGen/TableGenBackend.h"
117 using namespace llvm;
119 static cl::opt<std::string>
120 MatchPrefix("match-prefix", cl::init(""),
121 cl::desc("Only match instructions with the given prefix"));
124 class AsmMatcherInfo;
125 struct SubtargetFeatureInfo;
127 class AsmMatcherEmitter {
128 RecordKeeper &Records;
130 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
132 void run(raw_ostream &o);
135 /// ClassInfo - Helper class for storing the information about a particular
136 /// class of operands which can be matched.
139 /// Invalid kind, for use as a sentinel value.
142 /// The class for a particular token.
145 /// The (first) register class, subsequent register classes are
146 /// RegisterClass0+1, and so on.
149 /// The (first) user defined class, subsequent user defined classes are
150 /// UserClass0+1, and so on.
154 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
155 /// N) for the Nth user defined class.
158 /// SuperClasses - The super classes of this class. Note that for simplicities
159 /// sake user operands only record their immediate super class, while register
160 /// operands include all superclasses.
161 std::vector<ClassInfo*> SuperClasses;
163 /// Name - The full class name, suitable for use in an enum.
166 /// ClassName - The unadorned generic name for this class (e.g., Token).
167 std::string ClassName;
169 /// ValueName - The name of the value this class represents; for a token this
170 /// is the literal token string, for an operand it is the TableGen class (or
171 /// empty if this is a derived class).
172 std::string ValueName;
174 /// PredicateMethod - The name of the operand method to test whether the
175 /// operand matches this class; this is not valid for Token or register kinds.
176 std::string PredicateMethod;
178 /// RenderMethod - The name of the operand method to add this operand to an
179 /// MCInst; this is not valid for Token or register kinds.
180 std::string RenderMethod;
182 /// ParserMethod - The name of the operand method to do a target specific
183 /// parsing on the operand.
184 std::string ParserMethod;
186 /// For register classes, the records for all the registers in this class.
187 std::set<Record*> Registers;
189 /// For custom match classes, he diagnostic kind for when the predicate fails.
190 std::string DiagnosticType;
192 /// isRegisterClass() - Check if this is a register class.
193 bool isRegisterClass() const {
194 return Kind >= RegisterClass0 && Kind < UserClass0;
197 /// isUserClass() - Check if this is a user defined class.
198 bool isUserClass() const {
199 return Kind >= UserClass0;
202 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
203 /// are related if they are in the same class hierarchy.
204 bool isRelatedTo(const ClassInfo &RHS) const {
205 // Tokens are only related to tokens.
206 if (Kind == Token || RHS.Kind == Token)
207 return Kind == Token && RHS.Kind == Token;
209 // Registers classes are only related to registers classes, and only if
210 // their intersection is non-empty.
211 if (isRegisterClass() || RHS.isRegisterClass()) {
212 if (!isRegisterClass() || !RHS.isRegisterClass())
215 std::set<Record*> Tmp;
216 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
217 std::set_intersection(Registers.begin(), Registers.end(),
218 RHS.Registers.begin(), RHS.Registers.end(),
224 // Otherwise we have two users operands; they are related if they are in the
225 // same class hierarchy.
227 // FIXME: This is an oversimplification, they should only be related if they
228 // intersect, however we don't have that information.
229 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
230 const ClassInfo *Root = this;
231 while (!Root->SuperClasses.empty())
232 Root = Root->SuperClasses.front();
234 const ClassInfo *RHSRoot = &RHS;
235 while (!RHSRoot->SuperClasses.empty())
236 RHSRoot = RHSRoot->SuperClasses.front();
238 return Root == RHSRoot;
241 /// isSubsetOf - Test whether this class is a subset of \p RHS.
242 bool isSubsetOf(const ClassInfo &RHS) const {
243 // This is a subset of RHS if it is the same class...
247 // ... or if any of its super classes are a subset of RHS.
248 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
249 ie = SuperClasses.end(); it != ie; ++it)
250 if ((*it)->isSubsetOf(RHS))
256 /// operator< - Compare two classes.
257 bool operator<(const ClassInfo &RHS) const {
261 // Unrelated classes can be ordered by kind.
262 if (!isRelatedTo(RHS))
263 return Kind < RHS.Kind;
267 llvm_unreachable("Invalid kind!");
270 // This class precedes the RHS if it is a proper subset of the RHS.
273 if (RHS.isSubsetOf(*this))
276 // Otherwise, order by name to ensure we have a total ordering.
277 return ValueName < RHS.ValueName;
283 /// Sort ClassInfo pointers independently of pointer value.
284 struct LessClassInfoPtr {
285 bool operator()(const ClassInfo *LHS, const ClassInfo *RHS) const {
291 /// MatchableInfo - Helper class for storing the necessary information for an
292 /// instruction or alias which is capable of being matched.
293 struct MatchableInfo {
295 /// Token - This is the token that the operand came from.
298 /// The unique class instance this operand should match.
301 /// The operand name this is, if anything.
304 /// The suboperand index within SrcOpName, or -1 for the entire operand.
307 /// Register record if this token is singleton register.
308 Record *SingletonReg;
310 explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1),
314 /// ResOperand - This represents a single operand in the result instruction
315 /// generated by the match. In cases (like addressing modes) where a single
316 /// assembler operand expands to multiple MCOperands, this represents the
317 /// single assembler operand, not the MCOperand.
320 /// RenderAsmOperand - This represents an operand result that is
321 /// generated by calling the render method on the assembly operand. The
322 /// corresponding AsmOperand is specified by AsmOperandNum.
325 /// TiedOperand - This represents a result operand that is a duplicate of
326 /// a previous result operand.
329 /// ImmOperand - This represents an immediate value that is dumped into
333 /// RegOperand - This represents a fixed register that is dumped in.
338 /// This is the operand # in the AsmOperands list that this should be
340 unsigned AsmOperandNum;
342 /// TiedOperandNum - This is the (earlier) result operand that should be
344 unsigned TiedOperandNum;
346 /// ImmVal - This is the immediate value added to the instruction.
349 /// Register - This is the register record.
353 /// MINumOperands - The number of MCInst operands populated by this
355 unsigned MINumOperands;
357 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
359 X.Kind = RenderAsmOperand;
360 X.AsmOperandNum = AsmOpNum;
361 X.MINumOperands = NumOperands;
365 static ResOperand getTiedOp(unsigned TiedOperandNum) {
367 X.Kind = TiedOperand;
368 X.TiedOperandNum = TiedOperandNum;
373 static ResOperand getImmOp(int64_t Val) {
381 static ResOperand getRegOp(Record *Reg) {
390 /// AsmVariantID - Target's assembly syntax variant no.
393 /// TheDef - This is the definition of the instruction or InstAlias that this
394 /// matchable came from.
395 Record *const TheDef;
397 /// DefRec - This is the definition that it came from.
398 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
400 const CodeGenInstruction *getResultInst() const {
401 if (DefRec.is<const CodeGenInstruction*>())
402 return DefRec.get<const CodeGenInstruction*>();
403 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
406 /// ResOperands - This is the operand list that should be built for the result
408 SmallVector<ResOperand, 8> ResOperands;
410 /// AsmString - The assembly string for this instruction (with variants
411 /// removed), e.g. "movsx $src, $dst".
412 std::string AsmString;
414 /// Mnemonic - This is the first token of the matched instruction, its
418 /// AsmOperands - The textual operands that this instruction matches,
419 /// annotated with a class and where in the OperandList they were defined.
420 /// This directly corresponds to the tokenized AsmString after the mnemonic is
422 SmallVector<AsmOperand, 8> AsmOperands;
424 /// Predicates - The required subtarget features to match this instruction.
425 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
427 /// ConversionFnKind - The enum value which is passed to the generated
428 /// convertToMCInst to convert parsed operands into an MCInst for this
430 std::string ConversionFnKind;
432 MatchableInfo(const CodeGenInstruction &CGI)
433 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI),
434 AsmString(CGI.AsmString) {
437 MatchableInfo(const CodeGenInstAlias *Alias)
438 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias),
439 AsmString(Alias->AsmString) {
442 // Two-operand aliases clone from the main matchable, but mark the second
443 // operand as a tied operand of the first for purposes of the assembler.
444 void formTwoOperandAlias(StringRef Constraint);
446 void initialize(const AsmMatcherInfo &Info,
447 SmallPtrSet<Record*, 16> &SingletonRegisters,
448 int AsmVariantNo, std::string &RegisterPrefix);
450 /// validate - Return true if this matchable is a valid thing to match against
451 /// and perform a bunch of validity checking.
452 bool validate(StringRef CommentDelimiter, bool Hack) const;
454 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
455 /// if present, from specified token.
457 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info,
458 std::string &RegisterPrefix);
460 /// findAsmOperand - Find the AsmOperand with the specified name and
461 /// suboperand index.
462 int findAsmOperand(StringRef N, int SubOpIdx) const {
463 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
464 if (N == AsmOperands[i].SrcOpName &&
465 SubOpIdx == AsmOperands[i].SubOpIdx)
470 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
471 /// This does not check the suboperand index.
472 int findAsmOperandNamed(StringRef N) const {
473 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
474 if (N == AsmOperands[i].SrcOpName)
479 void buildInstructionResultOperands();
480 void buildAliasResultOperands();
482 /// operator< - Compare two matchables.
483 bool operator<(const MatchableInfo &RHS) const {
484 // The primary comparator is the instruction mnemonic.
485 if (Mnemonic != RHS.Mnemonic)
486 return Mnemonic < RHS.Mnemonic;
488 if (AsmOperands.size() != RHS.AsmOperands.size())
489 return AsmOperands.size() < RHS.AsmOperands.size();
491 // Compare lexicographically by operand. The matcher validates that other
492 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
493 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
494 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
496 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
500 // Give matches that require more features higher precedence. This is useful
501 // because we cannot define AssemblerPredicates with the negation of
502 // processor features. For example, ARM v6 "nop" may be either a HINT or
503 // MOV. With v6, we want to match HINT. The assembler has no way to
504 // predicate MOV under "NoV6", but HINT will always match first because it
505 // requires V6 while MOV does not.
506 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
507 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
512 /// couldMatchAmbiguouslyWith - Check whether this matchable could
513 /// ambiguously match the same set of operands as \p RHS (without being a
514 /// strictly superior match).
515 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) {
516 // The primary comparator is the instruction mnemonic.
517 if (Mnemonic != RHS.Mnemonic)
520 // The number of operands is unambiguous.
521 if (AsmOperands.size() != RHS.AsmOperands.size())
524 // Otherwise, make sure the ordering of the two instructions is unambiguous
525 // by checking that either (a) a token or operand kind discriminates them,
526 // or (b) the ordering among equivalent kinds is consistent.
528 // Tokens and operand kinds are unambiguous (assuming a correct target
530 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
531 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
532 AsmOperands[i].Class->Kind == ClassInfo::Token)
533 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
534 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
537 // Otherwise, this operand could commute if all operands are equivalent, or
538 // there is a pair of operands that compare less than and a pair that
539 // compare greater than.
540 bool HasLT = false, HasGT = false;
541 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
542 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
544 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
548 return !(HasLT ^ HasGT);
554 void tokenizeAsmString(const AsmMatcherInfo &Info);
557 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
558 /// feature which participates in instruction matching.
559 struct SubtargetFeatureInfo {
560 /// \brief The predicate record for this feature.
563 /// \brief An unique index assigned to represent this feature.
566 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
568 /// \brief The name of the enumerated constant identifying this feature.
569 std::string getEnumName() const {
570 return "Feature_" + TheDef->getName();
574 struct OperandMatchEntry {
575 unsigned OperandMask;
579 static OperandMatchEntry create(MatchableInfo* mi, ClassInfo *ci,
582 X.OperandMask = opMask;
590 class AsmMatcherInfo {
593 RecordKeeper &Records;
595 /// The tablegen AsmParser record.
598 /// Target - The target information.
599 CodeGenTarget &Target;
601 /// The classes which are needed for matching.
602 std::vector<ClassInfo*> Classes;
604 /// The information on the matchables to match.
605 std::vector<MatchableInfo*> Matchables;
607 /// Info for custom matching operands by user defined methods.
608 std::vector<OperandMatchEntry> OperandMatchInfo;
610 /// Map of Register records to their class information.
611 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
612 RegisterClassesTy RegisterClasses;
614 /// Map of Predicate records to their subtarget information.
615 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
617 /// Map of AsmOperandClass records to their class information.
618 std::map<Record*, ClassInfo*> AsmOperandClasses;
621 /// Map of token to class information which has already been constructed.
622 std::map<std::string, ClassInfo*> TokenClasses;
624 /// Map of RegisterClass records to their class information.
625 std::map<Record*, ClassInfo*> RegisterClassClasses;
628 /// getTokenClass - Lookup or create the class for the given token.
629 ClassInfo *getTokenClass(StringRef Token);
631 /// getOperandClass - Lookup or create the class for the given operand.
632 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
634 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
636 /// buildRegisterClasses - Build the ClassInfo* instances for register
638 void buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
640 /// buildOperandClasses - Build the ClassInfo* instances for user defined
642 void buildOperandClasses();
644 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
646 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
647 MatchableInfo::AsmOperand &Op);
650 AsmMatcherInfo(Record *AsmParser,
651 CodeGenTarget &Target,
652 RecordKeeper &Records);
654 /// buildInfo - Construct the various tables used during matching.
657 /// buildOperandMatchInfo - Build the necessary information to handle user
658 /// defined operand parsing methods.
659 void buildOperandMatchInfo();
661 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
663 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
664 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
665 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
666 SubtargetFeatures.find(Def);
667 return I == SubtargetFeatures.end() ? 0 : I->second;
670 RecordKeeper &getRecords() const {
675 } // End anonymous namespace
677 void MatchableInfo::dump() {
678 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
680 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
681 AsmOperand &Op = AsmOperands[i];
682 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
683 errs() << '\"' << Op.Token << "\"\n";
687 static std::pair<StringRef, StringRef>
688 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
689 // Split via the '='.
690 std::pair<StringRef, StringRef> Ops = S.split('=');
691 if (Ops.second == "")
692 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
693 // Trim whitespace and the leading '$' on the operand names.
694 size_t start = Ops.first.find_first_of('$');
695 if (start == std::string::npos)
696 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
697 Ops.first = Ops.first.slice(start + 1, std::string::npos);
698 size_t end = Ops.first.find_last_of(" \t");
699 Ops.first = Ops.first.slice(0, end);
700 // Now the second operand.
701 start = Ops.second.find_first_of('$');
702 if (start == std::string::npos)
703 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
704 Ops.second = Ops.second.slice(start + 1, std::string::npos);
705 end = Ops.second.find_last_of(" \t");
706 Ops.first = Ops.first.slice(0, end);
710 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
711 // Figure out which operands are aliased and mark them as tied.
712 std::pair<StringRef, StringRef> Ops =
713 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
715 // Find the AsmOperands that refer to the operands we're aliasing.
716 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
717 int DstAsmOperand = findAsmOperandNamed(Ops.second);
718 if (SrcAsmOperand == -1)
719 PrintFatalError(TheDef->getLoc(),
720 "unknown source two-operand alias operand '" +
721 Ops.first.str() + "'.");
722 if (DstAsmOperand == -1)
723 PrintFatalError(TheDef->getLoc(),
724 "unknown destination two-operand alias operand '" +
725 Ops.second.str() + "'.");
727 // Find the ResOperand that refers to the operand we're aliasing away
728 // and update it to refer to the combined operand instead.
729 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
730 ResOperand &Op = ResOperands[i];
731 if (Op.Kind == ResOperand::RenderAsmOperand &&
732 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
733 Op.AsmOperandNum = DstAsmOperand;
737 // Remove the AsmOperand for the alias operand.
738 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
739 // Adjust the ResOperand references to any AsmOperands that followed
740 // the one we just deleted.
741 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
742 ResOperand &Op = ResOperands[i];
745 // Nothing to do for operands that don't reference AsmOperands.
747 case ResOperand::RenderAsmOperand:
748 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
751 case ResOperand::TiedOperand:
752 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
759 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
760 SmallPtrSet<Record*, 16> &SingletonRegisters,
761 int AsmVariantNo, std::string &RegisterPrefix) {
762 AsmVariantID = AsmVariantNo;
764 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
766 tokenizeAsmString(Info);
768 // Compute the require features.
769 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
770 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
771 if (SubtargetFeatureInfo *Feature =
772 Info.getSubtargetFeature(Predicates[i]))
773 RequiredFeatures.push_back(Feature);
775 // Collect singleton registers, if used.
776 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
777 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix);
778 if (Record *Reg = AsmOperands[i].SingletonReg)
779 SingletonRegisters.insert(Reg);
783 /// tokenizeAsmString - Tokenize a simplified assembly string.
784 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
785 StringRef String = AsmString;
788 for (unsigned i = 0, e = String.size(); i != e; ++i) {
798 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
801 if (!isspace(String[i]) && String[i] != ',')
802 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
808 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
812 assert(i != String.size() && "Invalid quoted character");
813 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
819 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
823 // If this isn't "${", treat like a normal token.
824 if (i + 1 == String.size() || String[i + 1] != '{') {
829 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
830 assert(End != String.end() && "Missing brace in operand reference!");
831 size_t EndPos = End - String.begin();
832 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
840 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
849 if (InTok && Prev != String.size())
850 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
852 // The first token of the instruction is the mnemonic, which must be a
853 // simple string, not a $foo variable or a singleton register.
854 if (AsmOperands.empty())
855 PrintFatalError(TheDef->getLoc(),
856 "Instruction '" + TheDef->getName() + "' has no tokens");
857 Mnemonic = AsmOperands[0].Token;
858 if (Mnemonic.empty())
859 PrintFatalError(TheDef->getLoc(),
860 "Missing instruction mnemonic");
861 // FIXME : Check and raise an error if it is a register.
862 if (Mnemonic[0] == '$')
863 PrintFatalError(TheDef->getLoc(),
864 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
866 // Remove the first operand, it is tracked in the mnemonic field.
867 AsmOperands.erase(AsmOperands.begin());
870 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
871 // Reject matchables with no .s string.
872 if (AsmString.empty())
873 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
875 // Reject any matchables with a newline in them, they should be marked
876 // isCodeGenOnly if they are pseudo instructions.
877 if (AsmString.find('\n') != std::string::npos)
878 PrintFatalError(TheDef->getLoc(),
879 "multiline instruction is not valid for the asmparser, "
880 "mark it isCodeGenOnly");
882 // Remove comments from the asm string. We know that the asmstring only
884 if (!CommentDelimiter.empty() &&
885 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
886 PrintFatalError(TheDef->getLoc(),
887 "asmstring for instruction has comment character in it, "
888 "mark it isCodeGenOnly");
890 // Reject matchables with operand modifiers, these aren't something we can
891 // handle, the target should be refactored to use operands instead of
894 // Also, check for instructions which reference the operand multiple times;
895 // this implies a constraint we would not honor.
896 std::set<std::string> OperandNames;
897 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
898 StringRef Tok = AsmOperands[i].Token;
899 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
900 PrintFatalError(TheDef->getLoc(),
901 "matchable with operand modifier '" + Tok.str() +
902 "' not supported by asm matcher. Mark isCodeGenOnly!");
904 // Verify that any operand is only mentioned once.
905 // We reject aliases and ignore instructions for now.
906 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
908 PrintFatalError(TheDef->getLoc(),
909 "ERROR: matchable with tied operand '" + Tok.str() +
910 "' can never be matched!");
911 // FIXME: Should reject these. The ARM backend hits this with $lane in a
912 // bunch of instructions. It is unclear what the right answer is.
914 errs() << "warning: '" << TheDef->getName() << "': "
915 << "ignoring instruction with tied operand '"
916 << Tok.str() << "'\n";
925 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
926 /// if present, from specified token.
928 extractSingletonRegisterForAsmOperand(unsigned OperandNo,
929 const AsmMatcherInfo &Info,
930 std::string &RegisterPrefix) {
931 StringRef Tok = AsmOperands[OperandNo].Token;
932 if (RegisterPrefix.empty()) {
933 std::string LoweredTok = Tok.lower();
934 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
935 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
939 if (!Tok.startswith(RegisterPrefix))
942 StringRef RegName = Tok.substr(RegisterPrefix.size());
943 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
944 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
946 // If there is no register prefix (i.e. "%" in "%eax"), then this may
947 // be some random non-register token, just ignore it.
951 static std::string getEnumNameForToken(StringRef Str) {
954 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
956 case '*': Res += "_STAR_"; break;
957 case '%': Res += "_PCT_"; break;
958 case ':': Res += "_COLON_"; break;
959 case '!': Res += "_EXCLAIM_"; break;
960 case '.': Res += "_DOT_"; break;
961 case '<': Res += "_LT_"; break;
962 case '>': Res += "_GT_"; break;
964 if ((*it >= 'A' && *it <= 'Z') ||
965 (*it >= 'a' && *it <= 'z') ||
966 (*it >= '0' && *it <= '9'))
969 Res += "_" + utostr((unsigned) *it) + "_";
976 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
977 ClassInfo *&Entry = TokenClasses[Token];
980 Entry = new ClassInfo();
981 Entry->Kind = ClassInfo::Token;
982 Entry->ClassName = "Token";
983 Entry->Name = "MCK_" + getEnumNameForToken(Token);
984 Entry->ValueName = Token;
985 Entry->PredicateMethod = "<invalid>";
986 Entry->RenderMethod = "<invalid>";
987 Entry->ParserMethod = "";
988 Entry->DiagnosticType = "";
989 Classes.push_back(Entry);
996 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
998 Record *Rec = OI.Rec;
1000 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1001 return getOperandClass(Rec, SubOpIdx);
1005 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1006 if (Rec->isSubClassOf("RegisterOperand")) {
1007 // RegisterOperand may have an associated ParserMatchClass. If it does,
1008 // use it, else just fall back to the underlying register class.
1009 const RecordVal *R = Rec->getValue("ParserMatchClass");
1010 if (R == 0 || R->getValue() == 0)
1011 PrintFatalError("Record `" + Rec->getName() +
1012 "' does not have a ParserMatchClass!\n");
1014 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1015 Record *MatchClass = DI->getDef();
1016 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1020 // No custom match class. Just use the register class.
1021 Record *ClassRec = Rec->getValueAsDef("RegClass");
1023 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1024 "' has no associated register class!\n");
1025 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1027 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1031 if (Rec->isSubClassOf("RegisterClass")) {
1032 if (ClassInfo *CI = RegisterClassClasses[Rec])
1034 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1037 if (!Rec->isSubClassOf("Operand"))
1038 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1039 "' does not derive from class Operand!\n");
1040 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1041 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1044 PrintFatalError(Rec->getLoc(), "operand has no match class!");
1047 void AsmMatcherInfo::
1048 buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
1049 const std::vector<CodeGenRegister*> &Registers =
1050 Target.getRegBank().getRegisters();
1051 ArrayRef<CodeGenRegisterClass*> RegClassList =
1052 Target.getRegBank().getRegClasses();
1054 // The register sets used for matching.
1055 std::set< std::set<Record*> > RegisterSets;
1057 // Gather the defined sets.
1058 for (ArrayRef<CodeGenRegisterClass*>::const_iterator it =
1059 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
1060 RegisterSets.insert(std::set<Record*>(
1061 (*it)->getOrder().begin(), (*it)->getOrder().end()));
1063 // Add any required singleton sets.
1064 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1065 ie = SingletonRegisters.end(); it != ie; ++it) {
1067 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
1070 // Introduce derived sets where necessary (when a register does not determine
1071 // a unique register set class), and build the mapping of registers to the set
1072 // they should classify to.
1073 std::map<Record*, std::set<Record*> > RegisterMap;
1074 for (std::vector<CodeGenRegister*>::const_iterator it = Registers.begin(),
1075 ie = Registers.end(); it != ie; ++it) {
1076 const CodeGenRegister &CGR = **it;
1077 // Compute the intersection of all sets containing this register.
1078 std::set<Record*> ContainingSet;
1080 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1081 ie = RegisterSets.end(); it != ie; ++it) {
1082 if (!it->count(CGR.TheDef))
1085 if (ContainingSet.empty()) {
1086 ContainingSet = *it;
1090 std::set<Record*> Tmp;
1091 std::swap(Tmp, ContainingSet);
1092 std::insert_iterator< std::set<Record*> > II(ContainingSet,
1093 ContainingSet.begin());
1094 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
1097 if (!ContainingSet.empty()) {
1098 RegisterSets.insert(ContainingSet);
1099 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1103 // Construct the register classes.
1104 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
1106 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1107 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
1108 ClassInfo *CI = new ClassInfo();
1109 CI->Kind = ClassInfo::RegisterClass0 + Index;
1110 CI->ClassName = "Reg" + utostr(Index);
1111 CI->Name = "MCK_Reg" + utostr(Index);
1113 CI->PredicateMethod = ""; // unused
1114 CI->RenderMethod = "addRegOperands";
1115 CI->Registers = *it;
1116 // FIXME: diagnostic type.
1117 CI->DiagnosticType = "";
1118 Classes.push_back(CI);
1119 RegisterSetClasses.insert(std::make_pair(*it, CI));
1122 // Find the superclasses; we could compute only the subgroup lattice edges,
1123 // but there isn't really a point.
1124 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1125 ie = RegisterSets.end(); it != ie; ++it) {
1126 ClassInfo *CI = RegisterSetClasses[*it];
1127 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
1128 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
1130 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
1131 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
1134 // Name the register classes which correspond to a user defined RegisterClass.
1135 for (ArrayRef<CodeGenRegisterClass*>::const_iterator
1136 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
1137 const CodeGenRegisterClass &RC = **it;
1138 // Def will be NULL for non-user defined register classes.
1139 Record *Def = RC.getDef();
1142 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(RC.getOrder().begin(),
1143 RC.getOrder().end())];
1144 if (CI->ValueName.empty()) {
1145 CI->ClassName = RC.getName();
1146 CI->Name = "MCK_" + RC.getName();
1147 CI->ValueName = RC.getName();
1149 CI->ValueName = CI->ValueName + "," + RC.getName();
1151 RegisterClassClasses.insert(std::make_pair(Def, CI));
1154 // Populate the map for individual registers.
1155 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
1156 ie = RegisterMap.end(); it != ie; ++it)
1157 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1159 // Name the register classes which correspond to singleton registers.
1160 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1161 ie = SingletonRegisters.end(); it != ie; ++it) {
1163 ClassInfo *CI = RegisterClasses[Rec];
1164 assert(CI && "Missing singleton register class info!");
1166 if (CI->ValueName.empty()) {
1167 CI->ClassName = Rec->getName();
1168 CI->Name = "MCK_" + Rec->getName();
1169 CI->ValueName = Rec->getName();
1171 CI->ValueName = CI->ValueName + "," + Rec->getName();
1175 void AsmMatcherInfo::buildOperandClasses() {
1176 std::vector<Record*> AsmOperands =
1177 Records.getAllDerivedDefinitions("AsmOperandClass");
1179 // Pre-populate AsmOperandClasses map.
1180 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1181 ie = AsmOperands.end(); it != ie; ++it)
1182 AsmOperandClasses[*it] = new ClassInfo();
1185 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1186 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
1187 ClassInfo *CI = AsmOperandClasses[*it];
1188 CI->Kind = ClassInfo::UserClass0 + Index;
1190 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
1191 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
1192 DefInit *DI = dyn_cast<DefInit>(Supers->getElement(i));
1194 PrintError((*it)->getLoc(), "Invalid super class reference!");
1198 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1200 PrintError((*it)->getLoc(), "Invalid super class reference!");
1202 CI->SuperClasses.push_back(SC);
1204 CI->ClassName = (*it)->getValueAsString("Name");
1205 CI->Name = "MCK_" + CI->ClassName;
1206 CI->ValueName = (*it)->getName();
1208 // Get or construct the predicate method name.
1209 Init *PMName = (*it)->getValueInit("PredicateMethod");
1210 if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1211 CI->PredicateMethod = SI->getValue();
1213 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1214 CI->PredicateMethod = "is" + CI->ClassName;
1217 // Get or construct the render method name.
1218 Init *RMName = (*it)->getValueInit("RenderMethod");
1219 if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1220 CI->RenderMethod = SI->getValue();
1222 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1223 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1226 // Get the parse method name or leave it as empty.
1227 Init *PRMName = (*it)->getValueInit("ParserMethod");
1228 if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1229 CI->ParserMethod = SI->getValue();
1231 // Get the diagnostic type or leave it as empty.
1232 // Get the parse method name or leave it as empty.
1233 Init *DiagnosticType = (*it)->getValueInit("DiagnosticType");
1234 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1235 CI->DiagnosticType = SI->getValue();
1237 AsmOperandClasses[*it] = CI;
1238 Classes.push_back(CI);
1242 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1243 CodeGenTarget &target,
1244 RecordKeeper &records)
1245 : Records(records), AsmParser(asmParser), Target(target) {
1248 /// buildOperandMatchInfo - Build the necessary information to handle user
1249 /// defined operand parsing methods.
1250 void AsmMatcherInfo::buildOperandMatchInfo() {
1252 /// Map containing a mask with all operands indices that can be found for
1253 /// that class inside a instruction.
1254 typedef std::map<ClassInfo*, unsigned, LessClassInfoPtr> OpClassMaskTy;
1255 OpClassMaskTy OpClassMask;
1257 for (std::vector<MatchableInfo*>::const_iterator it =
1258 Matchables.begin(), ie = Matchables.end();
1260 MatchableInfo &II = **it;
1261 OpClassMask.clear();
1263 // Keep track of all operands of this instructions which belong to the
1265 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1266 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1267 if (Op.Class->ParserMethod.empty())
1269 unsigned &OperandMask = OpClassMask[Op.Class];
1270 OperandMask |= (1 << i);
1273 // Generate operand match info for each mnemonic/operand class pair.
1274 for (OpClassMaskTy::iterator iit = OpClassMask.begin(),
1275 iie = OpClassMask.end(); iit != iie; ++iit) {
1276 unsigned OpMask = iit->second;
1277 ClassInfo *CI = iit->first;
1278 OperandMatchInfo.push_back(OperandMatchEntry::create(&II, CI, OpMask));
1283 void AsmMatcherInfo::buildInfo() {
1284 // Build information about all of the AssemblerPredicates.
1285 std::vector<Record*> AllPredicates =
1286 Records.getAllDerivedDefinitions("Predicate");
1287 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1288 Record *Pred = AllPredicates[i];
1289 // Ignore predicates that are not intended for the assembler.
1290 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1293 if (Pred->getName().empty())
1294 PrintFatalError(Pred->getLoc(), "Predicate has no name!");
1296 unsigned FeatureNo = SubtargetFeatures.size();
1297 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1298 assert(FeatureNo < 32 && "Too many subtarget features!");
1301 // Parse the instructions; we need to do this first so that we can gather the
1302 // singleton register classes.
1303 SmallPtrSet<Record*, 16> SingletonRegisters;
1304 unsigned VariantCount = Target.getAsmParserVariantCount();
1305 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1306 Record *AsmVariant = Target.getAsmParserVariant(VC);
1307 std::string CommentDelimiter =
1308 AsmVariant->getValueAsString("CommentDelimiter");
1309 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1310 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1312 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1313 E = Target.inst_end(); I != E; ++I) {
1314 const CodeGenInstruction &CGI = **I;
1316 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1317 // filter the set of instructions we consider.
1318 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1321 // Ignore "codegen only" instructions.
1322 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1325 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1327 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1329 // Ignore instructions which shouldn't be matched and diagnose invalid
1330 // instruction definitions with an error.
1331 if (!II->validate(CommentDelimiter, true))
1334 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1336 // FIXME: This is a total hack.
1337 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1338 StringRef(II->TheDef->getName()).endswith("_Int"))
1341 Matchables.push_back(II.take());
1344 // Parse all of the InstAlias definitions and stick them in the list of
1346 std::vector<Record*> AllInstAliases =
1347 Records.getAllDerivedDefinitions("InstAlias");
1348 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1349 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1351 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1352 // filter the set of instruction aliases we consider, based on the target
1354 if (!StringRef(Alias->ResultInst->TheDef->getName())
1355 .startswith( MatchPrefix))
1358 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1360 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1362 // Validate the alias definitions.
1363 II->validate(CommentDelimiter, false);
1365 Matchables.push_back(II.take());
1369 // Build info for the register classes.
1370 buildRegisterClasses(SingletonRegisters);
1372 // Build info for the user defined assembly operand classes.
1373 buildOperandClasses();
1375 // Build the information about matchables, now that we have fully formed
1377 std::vector<MatchableInfo*> NewMatchables;
1378 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1379 ie = Matchables.end(); it != ie; ++it) {
1380 MatchableInfo *II = *it;
1382 // Parse the tokens after the mnemonic.
1383 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1384 // don't precompute the loop bound.
1385 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1386 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1387 StringRef Token = Op.Token;
1389 // Check for singleton registers.
1390 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1391 Op.Class = RegisterClasses[RegRecord];
1392 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1393 "Unexpected class for singleton register");
1397 // Check for simple tokens.
1398 if (Token[0] != '$') {
1399 Op.Class = getTokenClass(Token);
1403 if (Token.size() > 1 && isdigit(Token[1])) {
1404 Op.Class = getTokenClass(Token);
1408 // Otherwise this is an operand reference.
1409 StringRef OperandName;
1410 if (Token[1] == '{')
1411 OperandName = Token.substr(2, Token.size() - 3);
1413 OperandName = Token.substr(1);
1415 if (II->DefRec.is<const CodeGenInstruction*>())
1416 buildInstructionOperandReference(II, OperandName, i);
1418 buildAliasOperandReference(II, OperandName, Op);
1421 if (II->DefRec.is<const CodeGenInstruction*>()) {
1422 II->buildInstructionResultOperands();
1423 // If the instruction has a two-operand alias, build up the
1424 // matchable here. We'll add them in bulk at the end to avoid
1425 // confusing this loop.
1426 std::string Constraint =
1427 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1428 if (Constraint != "") {
1429 // Start by making a copy of the original matchable.
1430 OwningPtr<MatchableInfo> AliasII(new MatchableInfo(*II));
1432 // Adjust it to be a two-operand alias.
1433 AliasII->formTwoOperandAlias(Constraint);
1435 // Add the alias to the matchables list.
1436 NewMatchables.push_back(AliasII.take());
1439 II->buildAliasResultOperands();
1441 if (!NewMatchables.empty())
1442 Matchables.insert(Matchables.end(), NewMatchables.begin(),
1443 NewMatchables.end());
1445 // Process token alias definitions and set up the associated superclass
1447 std::vector<Record*> AllTokenAliases =
1448 Records.getAllDerivedDefinitions("TokenAlias");
1449 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1450 Record *Rec = AllTokenAliases[i];
1451 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1452 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1453 if (FromClass == ToClass)
1454 PrintFatalError(Rec->getLoc(),
1455 "error: Destination value identical to source value.");
1456 FromClass->SuperClasses.push_back(ToClass);
1459 // Reorder classes so that classes precede super classes.
1460 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1463 /// buildInstructionOperandReference - The specified operand is a reference to a
1464 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1465 void AsmMatcherInfo::
1466 buildInstructionOperandReference(MatchableInfo *II,
1467 StringRef OperandName,
1468 unsigned AsmOpIdx) {
1469 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1470 const CGIOperandList &Operands = CGI.Operands;
1471 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1473 // Map this token to an operand.
1475 if (!Operands.hasOperandNamed(OperandName, Idx))
1476 PrintFatalError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1477 OperandName.str() + "'");
1479 // If the instruction operand has multiple suboperands, but the parser
1480 // match class for the asm operand is still the default "ImmAsmOperand",
1481 // then handle each suboperand separately.
1482 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1483 Record *Rec = Operands[Idx].Rec;
1484 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1485 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1486 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1487 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1488 StringRef Token = Op->Token; // save this in case Op gets moved
1489 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1490 MatchableInfo::AsmOperand NewAsmOp(Token);
1491 NewAsmOp.SubOpIdx = SI;
1492 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1494 // Replace Op with first suboperand.
1495 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1500 // Set up the operand class.
1501 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1503 // If the named operand is tied, canonicalize it to the untied operand.
1504 // For example, something like:
1505 // (outs GPR:$dst), (ins GPR:$src)
1506 // with an asmstring of
1508 // we want to canonicalize to:
1510 // so that we know how to provide the $dst operand when filling in the result.
1512 if (Operands[Idx].MINumOperands == 1)
1513 OITied = Operands[Idx].getTiedRegister();
1515 // The tied operand index is an MIOperand index, find the operand that
1517 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1518 OperandName = Operands[Idx.first].Name;
1519 Op->SubOpIdx = Idx.second;
1522 Op->SrcOpName = OperandName;
1525 /// buildAliasOperandReference - When parsing an operand reference out of the
1526 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1527 /// operand reference is by looking it up in the result pattern definition.
1528 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1529 StringRef OperandName,
1530 MatchableInfo::AsmOperand &Op) {
1531 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1533 // Set up the operand class.
1534 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1535 if (CGA.ResultOperands[i].isRecord() &&
1536 CGA.ResultOperands[i].getName() == OperandName) {
1537 // It's safe to go with the first one we find, because CodeGenInstAlias
1538 // validates that all operands with the same name have the same record.
1539 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1540 // Use the match class from the Alias definition, not the
1541 // destination instruction, as we may have an immediate that's
1542 // being munged by the match class.
1543 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1545 Op.SrcOpName = OperandName;
1549 PrintFatalError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1550 OperandName.str() + "'");
1553 void MatchableInfo::buildInstructionResultOperands() {
1554 const CodeGenInstruction *ResultInst = getResultInst();
1556 // Loop over all operands of the result instruction, determining how to
1558 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1559 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1561 // If this is a tied operand, just copy from the previously handled operand.
1563 if (OpInfo.MINumOperands == 1)
1564 TiedOp = OpInfo.getTiedRegister();
1566 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1570 // Find out what operand from the asmparser this MCInst operand comes from.
1571 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1572 if (OpInfo.Name.empty() || SrcOperand == -1) {
1573 // This may happen for operands that are tied to a suboperand of a
1574 // complex operand. Simply use a dummy value here; nobody should
1575 // use this operand slot.
1576 // FIXME: The long term goal is for the MCOperand list to not contain
1577 // tied operands at all.
1578 ResOperands.push_back(ResOperand::getImmOp(0));
1582 // Check if the one AsmOperand populates the entire operand.
1583 unsigned NumOperands = OpInfo.MINumOperands;
1584 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1585 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1589 // Add a separate ResOperand for each suboperand.
1590 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1591 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1592 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1593 "unexpected AsmOperands for suboperands");
1594 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1599 void MatchableInfo::buildAliasResultOperands() {
1600 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1601 const CodeGenInstruction *ResultInst = getResultInst();
1603 // Loop over all operands of the result instruction, determining how to
1605 unsigned AliasOpNo = 0;
1606 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1607 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1608 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1610 // If this is a tied operand, just copy from the previously handled operand.
1612 if (OpInfo->MINumOperands == 1)
1613 TiedOp = OpInfo->getTiedRegister();
1615 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1619 // Handle all the suboperands for this operand.
1620 const std::string &OpName = OpInfo->Name;
1621 for ( ; AliasOpNo < LastOpNo &&
1622 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1623 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1625 // Find out what operand from the asmparser that this MCInst operand
1627 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1628 case CodeGenInstAlias::ResultOperand::K_Record: {
1629 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1630 int SrcOperand = findAsmOperand(Name, SubIdx);
1631 if (SrcOperand == -1)
1632 PrintFatalError(TheDef->getLoc(), "Instruction '" +
1633 TheDef->getName() + "' has operand '" + OpName +
1634 "' that doesn't appear in asm string!");
1635 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1636 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1640 case CodeGenInstAlias::ResultOperand::K_Imm: {
1641 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1642 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1645 case CodeGenInstAlias::ResultOperand::K_Reg: {
1646 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1647 ResOperands.push_back(ResOperand::getRegOp(Reg));
1655 static unsigned getConverterOperandID(const std::string &Name,
1656 SetVector<std::string> &Table,
1658 IsNew = Table.insert(Name);
1660 unsigned ID = IsNew ? Table.size() - 1 :
1661 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1663 assert(ID < Table.size());
1669 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1670 std::vector<MatchableInfo*> &Infos,
1672 SetVector<std::string> OperandConversionKinds;
1673 SetVector<std::string> InstructionConversionKinds;
1674 std::vector<std::vector<uint8_t> > ConversionTable;
1675 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1677 // TargetOperandClass - This is the target's operand class, like X86Operand.
1678 std::string TargetOperandClass = Target.getName() + "Operand";
1680 // Write the convert function to a separate stream, so we can drop it after
1681 // the enum. We'll build up the conversion handlers for the individual
1682 // operand types opportunistically as we encounter them.
1683 std::string ConvertFnBody;
1684 raw_string_ostream CvtOS(ConvertFnBody);
1685 // Start the unified conversion function.
1686 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1687 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1688 << "unsigned Opcode,\n"
1689 << " const SmallVectorImpl<MCParsedAsmOperand*"
1690 << "> &Operands) {\n"
1691 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1692 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1693 << " Inst.setOpcode(Opcode);\n"
1694 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1695 << " switch (*p) {\n"
1696 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1697 << " case CVT_Reg:\n"
1698 << " static_cast<" << TargetOperandClass
1699 << "*>(Operands[*(p + 1)])->addRegOperands(Inst, 1);\n"
1701 << " case CVT_Tied:\n"
1702 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1705 std::string OperandFnBody;
1706 raw_string_ostream OpOS(OperandFnBody);
1707 // Start the operand number lookup function.
1708 OpOS << "void " << Target.getName() << ClassName << "::\n"
1709 << "convertToMapAndConstraints(unsigned Kind,\n";
1711 OpOS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {\n"
1712 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1713 << " unsigned NumMCOperands = 0;\n"
1714 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1715 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1716 << " switch (*p) {\n"
1717 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1718 << " case CVT_Reg:\n"
1719 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1720 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
1721 << " ++NumMCOperands;\n"
1723 << " case CVT_Tied:\n"
1724 << " ++NumMCOperands;\n"
1727 // Pre-populate the operand conversion kinds with the standard always
1728 // available entries.
1729 OperandConversionKinds.insert("CVT_Done");
1730 OperandConversionKinds.insert("CVT_Reg");
1731 OperandConversionKinds.insert("CVT_Tied");
1732 enum { CVT_Done, CVT_Reg, CVT_Tied };
1734 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1735 ie = Infos.end(); it != ie; ++it) {
1736 MatchableInfo &II = **it;
1738 // Check if we have a custom match function.
1739 std::string AsmMatchConverter =
1740 II.getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1741 if (!AsmMatchConverter.empty()) {
1742 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1743 II.ConversionFnKind = Signature;
1745 // Check if we have already generated this signature.
1746 if (!InstructionConversionKinds.insert(Signature))
1749 // Remember this converter for the kind enum.
1750 unsigned KindID = OperandConversionKinds.size();
1751 OperandConversionKinds.insert("CVT_" +
1752 getEnumNameForToken(AsmMatchConverter));
1754 // Add the converter row for this instruction.
1755 ConversionTable.push_back(std::vector<uint8_t>());
1756 ConversionTable.back().push_back(KindID);
1757 ConversionTable.back().push_back(CVT_Done);
1759 // Add the handler to the conversion driver function.
1760 CvtOS << " case CVT_"
1761 << getEnumNameForToken(AsmMatchConverter) << ":\n"
1762 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1765 // FIXME: Handle the operand number lookup for custom match functions.
1769 // Build the conversion function signature.
1770 std::string Signature = "Convert";
1772 std::vector<uint8_t> ConversionRow;
1774 // Compute the convert enum and the case body.
1775 MaxRowLength = std::max(MaxRowLength, II.ResOperands.size()*2 + 1 );
1777 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1778 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1780 // Generate code to populate each result operand.
1781 switch (OpInfo.Kind) {
1782 case MatchableInfo::ResOperand::RenderAsmOperand: {
1783 // This comes from something we parsed.
1784 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1786 // Registers are always converted the same, don't duplicate the
1787 // conversion function based on them.
1790 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1792 Signature += utostr(OpInfo.MINumOperands);
1793 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1795 // Add the conversion kind, if necessary, and get the associated ID
1796 // the index of its entry in the vector).
1797 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1798 Op.Class->RenderMethod);
1799 Name = getEnumNameForToken(Name);
1801 bool IsNewConverter = false;
1802 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1805 // Add the operand entry to the instruction kind conversion row.
1806 ConversionRow.push_back(ID);
1807 ConversionRow.push_back(OpInfo.AsmOperandNum + 1);
1809 if (!IsNewConverter)
1812 // This is a new operand kind. Add a handler for it to the
1813 // converter driver.
1814 CvtOS << " case " << Name << ":\n"
1815 << " static_cast<" << TargetOperandClass
1816 << "*>(Operands[*(p + 1)])->"
1817 << Op.Class->RenderMethod << "(Inst, " << OpInfo.MINumOperands
1821 // Add a handler for the operand number lookup.
1822 OpOS << " case " << Name << ":\n"
1823 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
1825 if (Op.Class->isRegisterClass())
1826 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
1828 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
1829 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
1833 case MatchableInfo::ResOperand::TiedOperand: {
1834 // If this operand is tied to a previous one, just copy the MCInst
1835 // operand from the earlier one.We can only tie single MCOperand values.
1836 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1837 unsigned TiedOp = OpInfo.TiedOperandNum;
1838 assert(i > TiedOp && "Tied operand precedes its target!");
1839 Signature += "__Tie" + utostr(TiedOp);
1840 ConversionRow.push_back(CVT_Tied);
1841 ConversionRow.push_back(TiedOp);
1844 case MatchableInfo::ResOperand::ImmOperand: {
1845 int64_t Val = OpInfo.ImmVal;
1846 std::string Ty = "imm_" + itostr(Val);
1847 Signature += "__" + Ty;
1849 std::string Name = "CVT_" + Ty;
1850 bool IsNewConverter = false;
1851 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1853 // Add the operand entry to the instruction kind conversion row.
1854 ConversionRow.push_back(ID);
1855 ConversionRow.push_back(0);
1857 if (!IsNewConverter)
1860 CvtOS << " case " << Name << ":\n"
1861 << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"
1864 OpOS << " case " << Name << ":\n"
1865 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1866 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
1867 << " ++NumMCOperands;\n"
1871 case MatchableInfo::ResOperand::RegOperand: {
1872 std::string Reg, Name;
1873 if (OpInfo.Register == 0) {
1877 Reg = getQualifiedName(OpInfo.Register);
1878 Name = "reg" + OpInfo.Register->getName();
1880 Signature += "__" + Name;
1881 Name = "CVT_" + Name;
1882 bool IsNewConverter = false;
1883 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1885 // Add the operand entry to the instruction kind conversion row.
1886 ConversionRow.push_back(ID);
1887 ConversionRow.push_back(0);
1889 if (!IsNewConverter)
1891 CvtOS << " case " << Name << ":\n"
1892 << " Inst.addOperand(MCOperand::CreateReg(" << Reg << "));\n"
1895 OpOS << " case " << Name << ":\n"
1896 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1897 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
1898 << " ++NumMCOperands;\n"
1904 // If there were no operands, add to the signature to that effect
1905 if (Signature == "Convert")
1906 Signature += "_NoOperands";
1908 II.ConversionFnKind = Signature;
1910 // Save the signature. If we already have it, don't add a new row
1912 if (!InstructionConversionKinds.insert(Signature))
1915 // Add the row to the table.
1916 ConversionTable.push_back(ConversionRow);
1919 // Finish up the converter driver function.
1920 CvtOS << " }\n }\n}\n\n";
1922 // Finish up the operand number lookup function.
1923 OpOS << " }\n }\n}\n\n";
1925 OS << "namespace {\n";
1927 // Output the operand conversion kind enum.
1928 OS << "enum OperatorConversionKind {\n";
1929 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i)
1930 OS << " " << OperandConversionKinds[i] << ",\n";
1931 OS << " CVT_NUM_CONVERTERS\n";
1934 // Output the instruction conversion kind enum.
1935 OS << "enum InstructionConversionKind {\n";
1936 for (SetVector<std::string>::const_iterator
1937 i = InstructionConversionKinds.begin(),
1938 e = InstructionConversionKinds.end(); i != e; ++i)
1939 OS << " " << *i << ",\n";
1940 OS << " CVT_NUM_SIGNATURES\n";
1944 OS << "} // end anonymous namespace\n\n";
1946 // Output the conversion table.
1947 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
1948 << MaxRowLength << "] = {\n";
1950 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
1951 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
1952 OS << " // " << InstructionConversionKinds[Row] << "\n";
1954 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
1955 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
1956 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
1957 OS << "CVT_Done },\n";
1962 // Spit out the conversion driver function.
1965 // Spit out the operand number lookup function.
1969 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
1970 static void emitMatchClassEnumeration(CodeGenTarget &Target,
1971 std::vector<ClassInfo*> &Infos,
1973 OS << "namespace {\n\n";
1975 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1976 << "/// instruction matching.\n";
1977 OS << "enum MatchClassKind {\n";
1978 OS << " InvalidMatchClass = 0,\n";
1979 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1980 ie = Infos.end(); it != ie; ++it) {
1981 ClassInfo &CI = **it;
1982 OS << " " << CI.Name << ", // ";
1983 if (CI.Kind == ClassInfo::Token) {
1984 OS << "'" << CI.ValueName << "'\n";
1985 } else if (CI.isRegisterClass()) {
1986 if (!CI.ValueName.empty())
1987 OS << "register class '" << CI.ValueName << "'\n";
1989 OS << "derived register class\n";
1991 OS << "user defined class '" << CI.ValueName << "'\n";
1994 OS << " NumMatchClassKinds\n";
2000 /// emitValidateOperandClass - Emit the function to validate an operand class.
2001 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2003 OS << "static unsigned validateOperandClass(MCParsedAsmOperand *GOp, "
2004 << "MatchClassKind Kind) {\n";
2005 OS << " " << Info.Target.getName() << "Operand &Operand = *("
2006 << Info.Target.getName() << "Operand*)GOp;\n";
2008 // The InvalidMatchClass is not to match any operand.
2009 OS << " if (Kind == InvalidMatchClass)\n";
2010 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2012 // Check for Token operands first.
2013 // FIXME: Use a more specific diagnostic type.
2014 OS << " if (Operand.isToken())\n";
2015 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2016 << " MCTargetAsmParser::Match_Success :\n"
2017 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2019 // Check the user classes. We don't care what order since we're only
2020 // actually matching against one of them.
2021 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
2022 ie = Info.Classes.end(); it != ie; ++it) {
2023 ClassInfo &CI = **it;
2025 if (!CI.isUserClass())
2028 OS << " // '" << CI.ClassName << "' class\n";
2029 OS << " if (Kind == " << CI.Name << ") {\n";
2030 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2031 OS << " return MCTargetAsmParser::Match_Success;\n";
2032 if (!CI.DiagnosticType.empty())
2033 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2034 << CI.DiagnosticType << ";\n";
2038 // Check for register operands, including sub-classes.
2039 OS << " if (Operand.isReg()) {\n";
2040 OS << " MatchClassKind OpKind;\n";
2041 OS << " switch (Operand.getReg()) {\n";
2042 OS << " default: OpKind = InvalidMatchClass; break;\n";
2043 for (AsmMatcherInfo::RegisterClassesTy::iterator
2044 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
2046 OS << " case " << Info.Target.getName() << "::"
2047 << it->first->getName() << ": OpKind = " << it->second->Name
2050 OS << " return isSubclass(OpKind, Kind) ? "
2051 << "MCTargetAsmParser::Match_Success :\n "
2052 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2054 // Generic fallthrough match failure case for operands that don't have
2055 // specialized diagnostic types.
2056 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2060 /// emitIsSubclass - Emit the subclass predicate function.
2061 static void emitIsSubclass(CodeGenTarget &Target,
2062 std::vector<ClassInfo*> &Infos,
2064 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2065 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2066 OS << " if (A == B)\n";
2067 OS << " return true;\n\n";
2069 OS << " switch (A) {\n";
2070 OS << " default:\n";
2071 OS << " return false;\n";
2072 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2073 ie = Infos.end(); it != ie; ++it) {
2074 ClassInfo &A = **it;
2076 std::vector<StringRef> SuperClasses;
2077 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2078 ie = Infos.end(); it != ie; ++it) {
2079 ClassInfo &B = **it;
2081 if (&A != &B && A.isSubsetOf(B))
2082 SuperClasses.push_back(B.Name);
2085 if (SuperClasses.empty())
2088 OS << "\n case " << A.Name << ":\n";
2090 if (SuperClasses.size() == 1) {
2091 OS << " return B == " << SuperClasses.back() << ";\n";
2095 OS << " switch (B) {\n";
2096 OS << " default: return false;\n";
2097 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
2098 OS << " case " << SuperClasses[i] << ": return true;\n";
2105 /// emitMatchTokenString - Emit the function to match a token string to the
2106 /// appropriate match class value.
2107 static void emitMatchTokenString(CodeGenTarget &Target,
2108 std::vector<ClassInfo*> &Infos,
2110 // Construct the match list.
2111 std::vector<StringMatcher::StringPair> Matches;
2112 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2113 ie = Infos.end(); it != ie; ++it) {
2114 ClassInfo &CI = **it;
2116 if (CI.Kind == ClassInfo::Token)
2117 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
2118 "return " + CI.Name + ";"));
2121 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2123 StringMatcher("Name", Matches, OS).Emit();
2125 OS << " return InvalidMatchClass;\n";
2129 /// emitMatchRegisterName - Emit the function to match a string to the target
2130 /// specific register enum.
2131 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2133 // Construct the match list.
2134 std::vector<StringMatcher::StringPair> Matches;
2135 const std::vector<CodeGenRegister*> &Regs =
2136 Target.getRegBank().getRegisters();
2137 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2138 const CodeGenRegister *Reg = Regs[i];
2139 if (Reg->TheDef->getValueAsString("AsmName").empty())
2142 Matches.push_back(StringMatcher::StringPair(
2143 Reg->TheDef->getValueAsString("AsmName"),
2144 "return " + utostr(Reg->EnumValue) + ";"));
2147 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2149 StringMatcher("Name", Matches, OS).Emit();
2151 OS << " return 0;\n";
2155 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2157 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2159 OS << "// Flags for subtarget features that participate in "
2160 << "instruction matching.\n";
2161 OS << "enum SubtargetFeatureFlag {\n";
2162 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2163 it = Info.SubtargetFeatures.begin(),
2164 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2165 SubtargetFeatureInfo &SFI = *it->second;
2166 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
2168 OS << " Feature_None = 0\n";
2172 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2173 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2174 // Get the set of diagnostic types from all of the operand classes.
2175 std::set<StringRef> Types;
2176 for (std::map<Record*, ClassInfo*>::const_iterator
2177 I = Info.AsmOperandClasses.begin(),
2178 E = Info.AsmOperandClasses.end(); I != E; ++I) {
2179 if (!I->second->DiagnosticType.empty())
2180 Types.insert(I->second->DiagnosticType);
2183 if (Types.empty()) return;
2185 // Now emit the enum entries.
2186 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end();
2188 OS << " Match_" << *I << ",\n";
2189 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2192 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2193 /// user-level name for a subtarget feature.
2194 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2195 OS << "// User-level names for subtarget features that participate in\n"
2196 << "// instruction matching.\n"
2197 << "static const char *getSubtargetFeatureName(unsigned Val) {\n"
2198 << " switch(Val) {\n";
2199 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2200 it = Info.SubtargetFeatures.begin(),
2201 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2202 SubtargetFeatureInfo &SFI = *it->second;
2203 // FIXME: Totally just a placeholder name to get the algorithm working.
2204 OS << " case " << SFI.getEnumName() << ": return \""
2205 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2207 OS << " default: return \"(unknown)\";\n";
2211 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2212 /// available features given a subtarget.
2213 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2215 std::string ClassName =
2216 Info.AsmParser->getValueAsString("AsmParserClassName");
2218 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
2219 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
2220 OS << " unsigned Features = 0;\n";
2221 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2222 it = Info.SubtargetFeatures.begin(),
2223 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2224 SubtargetFeatureInfo &SFI = *it->second;
2227 std::string CondStorage =
2228 SFI.TheDef->getValueAsString("AssemblerCondString");
2229 StringRef Conds = CondStorage;
2230 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2237 StringRef Cond = Comma.first;
2238 if (Cond[0] == '!') {
2240 Cond = Cond.substr(1);
2243 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
2250 if (Comma.second.empty())
2254 Comma = Comma.second.split(',');
2258 OS << " Features |= " << SFI.getEnumName() << ";\n";
2260 OS << " return Features;\n";
2264 static std::string GetAliasRequiredFeatures(Record *R,
2265 const AsmMatcherInfo &Info) {
2266 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2268 unsigned NumFeatures = 0;
2269 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2270 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2273 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2274 "' is not marked as an AssemblerPredicate!");
2279 Result += F->getEnumName();
2283 if (NumFeatures > 1)
2284 Result = '(' + Result + ')';
2288 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2289 std::vector<Record*> &Aliases,
2290 unsigned Indent = 0,
2291 StringRef AsmParserVariantName = StringRef()){
2292 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2293 // iteration order of the map is stable.
2294 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2296 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2297 Record *R = Aliases[i];
2298 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2299 std::string AsmVariantName = R->getValueAsString("AsmVariantName");
2300 if (AsmVariantName != AsmParserVariantName)
2302 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2304 if (AliasesFromMnemonic.empty())
2307 // Process each alias a "from" mnemonic at a time, building the code executed
2308 // by the string remapper.
2309 std::vector<StringMatcher::StringPair> Cases;
2310 for (std::map<std::string, std::vector<Record*> >::iterator
2311 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2313 const std::vector<Record*> &ToVec = I->second;
2315 // Loop through each alias and emit code that handles each case. If there
2316 // are two instructions without predicates, emit an error. If there is one,
2318 std::string MatchCode;
2319 int AliasWithNoPredicate = -1;
2321 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2322 Record *R = ToVec[i];
2323 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2325 // If this unconditionally matches, remember it for later and diagnose
2327 if (FeatureMask.empty()) {
2328 if (AliasWithNoPredicate != -1) {
2329 // We can't have two aliases from the same mnemonic with no predicate.
2330 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2331 "two MnemonicAliases with the same 'from' mnemonic!");
2332 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2335 AliasWithNoPredicate = i;
2338 if (R->getValueAsString("ToMnemonic") == I->first)
2339 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2341 if (!MatchCode.empty())
2342 MatchCode += "else ";
2343 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2344 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2347 if (AliasWithNoPredicate != -1) {
2348 Record *R = ToVec[AliasWithNoPredicate];
2349 if (!MatchCode.empty())
2350 MatchCode += "else\n ";
2351 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2354 MatchCode += "return;";
2356 Cases.push_back(std::make_pair(I->first, MatchCode));
2358 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2361 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2362 /// emit a function for them and return true, otherwise return false.
2363 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2364 CodeGenTarget &Target) {
2365 // Ignore aliases when match-prefix is set.
2366 if (!MatchPrefix.empty())
2369 std::vector<Record*> Aliases =
2370 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2371 if (Aliases.empty()) return false;
2373 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2374 "unsigned Features, unsigned VariantID) {\n";
2375 OS << " switch (VariantID) {\n";
2376 unsigned VariantCount = Target.getAsmParserVariantCount();
2377 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2378 Record *AsmVariant = Target.getAsmParserVariant(VC);
2379 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2380 std::string AsmParserVariantName = AsmVariant->getValueAsString("Name");
2381 OS << " case " << AsmParserVariantNo << ":\n";
2382 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2383 AsmParserVariantName);
2388 // Emit aliases that apply to all variants.
2389 emitMnemonicAliasVariant(OS, Info, Aliases);
2396 static const char *getMinimalTypeForRange(uint64_t Range) {
2397 assert(Range < 0xFFFFFFFFULL && "Enum too large");
2405 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2406 const AsmMatcherInfo &Info, StringRef ClassName,
2407 StringToOffsetTable &StringTable,
2408 unsigned MaxMnemonicIndex) {
2409 unsigned MaxMask = 0;
2410 for (std::vector<OperandMatchEntry>::const_iterator it =
2411 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2413 MaxMask |= it->OperandMask;
2416 // Emit the static custom operand parsing table;
2417 OS << "namespace {\n";
2418 OS << " struct OperandMatchEntry {\n";
2419 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2420 << " RequiredFeatures;\n";
2421 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2423 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2425 OS << " " << getMinimalTypeForRange(MaxMask)
2426 << " OperandMask;\n\n";
2427 OS << " StringRef getMnemonic() const {\n";
2428 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2429 OS << " MnemonicTable[Mnemonic]);\n";
2433 OS << " // Predicate for searching for an opcode.\n";
2434 OS << " struct LessOpcodeOperand {\n";
2435 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2436 OS << " return LHS.getMnemonic() < RHS;\n";
2438 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2439 OS << " return LHS < RHS.getMnemonic();\n";
2441 OS << " bool operator()(const OperandMatchEntry &LHS,";
2442 OS << " const OperandMatchEntry &RHS) {\n";
2443 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2447 OS << "} // end anonymous namespace.\n\n";
2449 OS << "static const OperandMatchEntry OperandMatchTable["
2450 << Info.OperandMatchInfo.size() << "] = {\n";
2452 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2453 for (std::vector<OperandMatchEntry>::const_iterator it =
2454 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2456 const OperandMatchEntry &OMI = *it;
2457 const MatchableInfo &II = *OMI.MI;
2461 // Write the required features mask.
2462 if (!II.RequiredFeatures.empty()) {
2463 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2465 OS << II.RequiredFeatures[i]->getEnumName();
2470 // Store a pascal-style length byte in the mnemonic.
2471 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2472 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2473 << " /* " << II.Mnemonic << " */, ";
2477 OS << ", " << OMI.OperandMask;
2479 bool printComma = false;
2480 for (int i = 0, e = 31; i !=e; ++i)
2481 if (OMI.OperandMask & (1 << i)) {
2493 // Emit the operand class switch to call the correct custom parser for
2494 // the found operand class.
2495 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2496 << Target.getName() << ClassName << "::\n"
2497 << "tryCustomParseOperand(SmallVectorImpl<MCParsedAsmOperand*>"
2498 << " &Operands,\n unsigned MCK) {\n\n"
2499 << " switch(MCK) {\n";
2501 for (std::vector<ClassInfo*>::const_iterator it = Info.Classes.begin(),
2502 ie = Info.Classes.end(); it != ie; ++it) {
2503 ClassInfo *CI = *it;
2504 if (CI->ParserMethod.empty())
2506 OS << " case " << CI->Name << ":\n"
2507 << " return " << CI->ParserMethod << "(Operands);\n";
2510 OS << " default:\n";
2511 OS << " return MatchOperand_NoMatch;\n";
2513 OS << " return MatchOperand_NoMatch;\n";
2516 // Emit the static custom operand parser. This code is very similar with
2517 // the other matcher. Also use MatchResultTy here just in case we go for
2518 // a better error handling.
2519 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2520 << Target.getName() << ClassName << "::\n"
2521 << "MatchOperandParserImpl(SmallVectorImpl<MCParsedAsmOperand*>"
2522 << " &Operands,\n StringRef Mnemonic) {\n";
2524 // Emit code to get the available features.
2525 OS << " // Get the current feature set.\n";
2526 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2528 OS << " // Get the next operand index.\n";
2529 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2531 // Emit code to search the table.
2532 OS << " // Search the table.\n";
2533 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2534 OS << " MnemonicRange =\n";
2535 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2536 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2537 << " LessOpcodeOperand());\n\n";
2539 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2540 OS << " return MatchOperand_NoMatch;\n\n";
2542 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2543 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2545 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2546 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2548 // Emit check that the required features are available.
2549 OS << " // check if the available features match\n";
2550 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2551 << "!= it->RequiredFeatures) {\n";
2552 OS << " continue;\n";
2555 // Emit check to ensure the operand number matches.
2556 OS << " // check if the operand in question has a custom parser.\n";
2557 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2558 OS << " continue;\n\n";
2560 // Emit call to the custom parser method
2561 OS << " // call custom parse method to handle the operand\n";
2562 OS << " OperandMatchResultTy Result = ";
2563 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2564 OS << " if (Result != MatchOperand_NoMatch)\n";
2565 OS << " return Result;\n";
2568 OS << " // Okay, we had no match.\n";
2569 OS << " return MatchOperand_NoMatch;\n";
2573 void AsmMatcherEmitter::run(raw_ostream &OS) {
2574 CodeGenTarget Target(Records);
2575 Record *AsmParser = Target.getAsmParser();
2576 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2578 // Compute the information on the instructions to match.
2579 AsmMatcherInfo Info(AsmParser, Target, Records);
2582 // Sort the instruction table using the partial order on classes. We use
2583 // stable_sort to ensure that ambiguous instructions are still
2584 // deterministically ordered.
2585 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2586 less_ptr<MatchableInfo>());
2588 DEBUG_WITH_TYPE("instruction_info", {
2589 for (std::vector<MatchableInfo*>::iterator
2590 it = Info.Matchables.begin(), ie = Info.Matchables.end();
2595 // Check for ambiguous matchables.
2596 DEBUG_WITH_TYPE("ambiguous_instrs", {
2597 unsigned NumAmbiguous = 0;
2598 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
2599 for (unsigned j = i + 1; j != e; ++j) {
2600 MatchableInfo &A = *Info.Matchables[i];
2601 MatchableInfo &B = *Info.Matchables[j];
2603 if (A.couldMatchAmbiguouslyWith(B)) {
2604 errs() << "warning: ambiguous matchables:\n";
2606 errs() << "\nis incomparable with:\n";
2614 errs() << "warning: " << NumAmbiguous
2615 << " ambiguous matchables!\n";
2618 // Compute the information on the custom operand parsing.
2619 Info.buildOperandMatchInfo();
2621 // Write the output.
2623 // Information for the class declaration.
2624 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2625 OS << "#undef GET_ASSEMBLER_HEADER\n";
2626 OS << " // This should be included into the middle of the declaration of\n";
2627 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2628 OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
2629 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2630 << "unsigned Opcode,\n"
2631 << " const SmallVectorImpl<MCParsedAsmOperand*> "
2633 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2634 OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands);\n";
2635 OS << " bool mnemonicIsValid(StringRef Mnemonic);\n";
2636 OS << " unsigned MatchInstructionImpl(\n";
2638 OS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n"
2639 << " MCInst &Inst,\n"
2640 << " unsigned &ErrorInfo,"
2641 << " bool matchingInlineAsm,\n"
2642 << " unsigned VariantID = 0);\n";
2644 if (Info.OperandMatchInfo.size()) {
2645 OS << "\n enum OperandMatchResultTy {\n";
2646 OS << " MatchOperand_Success, // operand matched successfully\n";
2647 OS << " MatchOperand_NoMatch, // operand did not match\n";
2648 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2650 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2651 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2652 OS << " StringRef Mnemonic);\n";
2654 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2655 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2656 OS << " unsigned MCK);\n\n";
2659 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2661 // Emit the operand match diagnostic enum names.
2662 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2663 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2664 emitOperandDiagnosticTypes(Info, OS);
2665 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2668 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2669 OS << "#undef GET_REGISTER_MATCHER\n\n";
2671 // Emit the subtarget feature enumeration.
2672 emitSubtargetFeatureFlagEnumeration(Info, OS);
2674 // Emit the function to match a register name to number.
2675 // This should be omitted for Mips target
2676 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2677 emitMatchRegisterName(Target, AsmParser, OS);
2679 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2681 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2682 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2684 // Generate the helper function to get the names for subtarget features.
2685 emitGetSubtargetFeatureName(Info, OS);
2687 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2689 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2690 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2692 // Generate the function that remaps for mnemonic aliases.
2693 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
2695 // Generate the convertToMCInst function to convert operands into an MCInst.
2696 // Also, generate the convertToMapAndConstraints function for MS-style inline
2697 // assembly. The latter doesn't actually generate a MCInst.
2698 emitConvertFuncs(Target, ClassName, Info.Matchables, OS);
2700 // Emit the enumeration for classes which participate in matching.
2701 emitMatchClassEnumeration(Target, Info.Classes, OS);
2703 // Emit the routine to match token strings to their match class.
2704 emitMatchTokenString(Target, Info.Classes, OS);
2706 // Emit the subclass predicate routine.
2707 emitIsSubclass(Target, Info.Classes, OS);
2709 // Emit the routine to validate an operand against a match class.
2710 emitValidateOperandClass(Info, OS);
2712 // Emit the available features compute function.
2713 emitComputeAvailableFeatures(Info, OS);
2716 StringToOffsetTable StringTable;
2718 size_t MaxNumOperands = 0;
2719 unsigned MaxMnemonicIndex = 0;
2720 for (std::vector<MatchableInfo*>::const_iterator it =
2721 Info.Matchables.begin(), ie = Info.Matchables.end();
2723 MatchableInfo &II = **it;
2724 MaxNumOperands = std::max(MaxNumOperands, II.AsmOperands.size());
2726 // Store a pascal-style length byte in the mnemonic.
2727 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2728 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2729 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2732 OS << "static const char *const MnemonicTable =\n";
2733 StringTable.EmitString(OS);
2736 // Emit the static match table; unused classes get initalized to 0 which is
2737 // guaranteed to be InvalidMatchClass.
2739 // FIXME: We can reduce the size of this table very easily. First, we change
2740 // it so that store the kinds in separate bit-fields for each index, which
2741 // only needs to be the max width used for classes at that index (we also need
2742 // to reject based on this during classification). If we then make sure to
2743 // order the match kinds appropriately (putting mnemonics last), then we
2744 // should only end up using a few bits for each class, especially the ones
2745 // following the mnemonic.
2746 OS << "namespace {\n";
2747 OS << " struct MatchEntry {\n";
2748 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2750 OS << " uint16_t Opcode;\n";
2751 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2753 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2754 << " RequiredFeatures;\n";
2755 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2756 << " Classes[" << MaxNumOperands << "];\n";
2757 OS << " uint8_t AsmVariantID;\n\n";
2758 OS << " StringRef getMnemonic() const {\n";
2759 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2760 OS << " MnemonicTable[Mnemonic]);\n";
2764 OS << " // Predicate for searching for an opcode.\n";
2765 OS << " struct LessOpcode {\n";
2766 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2767 OS << " return LHS.getMnemonic() < RHS;\n";
2769 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2770 OS << " return LHS < RHS.getMnemonic();\n";
2772 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2773 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2777 OS << "} // end anonymous namespace.\n\n";
2779 OS << "static const MatchEntry MatchTable["
2780 << Info.Matchables.size() << "] = {\n";
2782 for (std::vector<MatchableInfo*>::const_iterator it =
2783 Info.Matchables.begin(), ie = Info.Matchables.end();
2785 MatchableInfo &II = **it;
2787 // Store a pascal-style length byte in the mnemonic.
2788 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2789 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2790 << " /* " << II.Mnemonic << " */, "
2791 << Target.getName() << "::"
2792 << II.getResultInst()->TheDef->getName() << ", "
2793 << II.ConversionFnKind << ", ";
2795 // Write the required features mask.
2796 if (!II.RequiredFeatures.empty()) {
2797 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2799 OS << II.RequiredFeatures[i]->getEnumName();
2805 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
2806 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
2809 OS << Op.Class->Name;
2811 OS << " }, " << II.AsmVariantID;
2817 // A method to determine if a mnemonic is in the list.
2818 OS << "bool " << Target.getName() << ClassName << "::\n"
2819 << "mnemonicIsValid(StringRef Mnemonic) {\n";
2820 OS << " // Search the table.\n";
2821 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2822 OS << " std::equal_range(MatchTable, MatchTable+"
2823 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n";
2824 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2827 // Finally, build the match function.
2829 << Target.getName() << ClassName << "::\n"
2830 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
2832 OS << " MCInst &Inst,\n"
2833 << "unsigned &ErrorInfo, bool matchingInlineAsm, unsigned VariantID) {\n";
2835 OS << " // Eliminate obvious mismatches.\n";
2836 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2837 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2838 OS << " return Match_InvalidOperand;\n";
2841 // Emit code to get the available features.
2842 OS << " // Get the current feature set.\n";
2843 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2845 OS << " // Get the instruction mnemonic, which is the first token.\n";
2846 OS << " StringRef Mnemonic = ((" << Target.getName()
2847 << "Operand*)Operands[0])->getToken();\n\n";
2849 if (HasMnemonicAliases) {
2850 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2851 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
2854 // Emit code to compute the class list for this operand vector.
2855 OS << " // Some state to try to produce better error messages.\n";
2856 OS << " bool HadMatchOtherThanFeatures = false;\n";
2857 OS << " bool HadMatchOtherThanPredicate = false;\n";
2858 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2859 OS << " unsigned MissingFeatures = ~0U;\n";
2860 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2861 OS << " // wrong for all instances of the instruction.\n";
2862 OS << " ErrorInfo = ~0U;\n";
2864 // Emit code to search the table.
2865 OS << " // Search the table.\n";
2866 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2867 OS << " std::equal_range(MatchTable, MatchTable+"
2868 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n";
2870 OS << " // Return a more specific error code if no mnemonics match.\n";
2871 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2872 OS << " return Match_MnemonicFail;\n\n";
2874 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2875 << "*ie = MnemonicRange.second;\n";
2876 OS << " it != ie; ++it) {\n";
2878 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2879 OS << " assert(Mnemonic == it->getMnemonic());\n";
2881 // Emit check that the subclasses match.
2882 OS << " if (VariantID != it->AsmVariantID) continue;\n";
2883 OS << " bool OperandsValid = true;\n";
2884 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2885 OS << " if (i + 1 >= Operands.size()) {\n";
2886 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2887 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n";
2890 OS << " unsigned Diag = validateOperandClass(Operands[i+1],\n";
2892 OS << "(MatchClassKind)it->Classes[i]);\n";
2893 OS << " if (Diag == Match_Success)\n";
2894 OS << " continue;\n";
2895 OS << " // If the generic handler indicates an invalid operand\n";
2896 OS << " // failure, check for a special case.\n";
2897 OS << " if (Diag == Match_InvalidOperand) {\n";
2898 OS << " Diag = validateTargetOperandClass(Operands[i+1],\n";
2900 OS << "(MatchClassKind)it->Classes[i]);\n";
2901 OS << " if (Diag == Match_Success)\n";
2902 OS << " continue;\n";
2904 OS << " // If this operand is broken for all of the instances of this\n";
2905 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2906 OS << " // If we already had a match that only failed due to a\n";
2907 OS << " // target predicate, that diagnostic is preferred.\n";
2908 OS << " if (!HadMatchOtherThanPredicate &&\n";
2909 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n";
2910 OS << " ErrorInfo = i+1;\n";
2911 OS << " // InvalidOperand is the default. Prefer specificity.\n";
2912 OS << " if (Diag != Match_InvalidOperand)\n";
2913 OS << " RetCode = Diag;\n";
2915 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2916 OS << " OperandsValid = false;\n";
2920 OS << " if (!OperandsValid) continue;\n";
2922 // Emit check that the required features are available.
2923 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2924 << "!= it->RequiredFeatures) {\n";
2925 OS << " HadMatchOtherThanFeatures = true;\n";
2926 OS << " unsigned NewMissingFeatures = it->RequiredFeatures & "
2927 "~AvailableFeatures;\n";
2928 OS << " if (CountPopulation_32(NewMissingFeatures) <=\n"
2929 " CountPopulation_32(MissingFeatures))\n";
2930 OS << " MissingFeatures = NewMissingFeatures;\n";
2931 OS << " continue;\n";
2934 OS << " if (matchingInlineAsm) {\n";
2935 OS << " Inst.setOpcode(it->Opcode);\n";
2936 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
2937 OS << " return Match_Success;\n";
2939 OS << " // We have selected a definite instruction, convert the parsed\n"
2940 << " // operands into the appropriate MCInst.\n";
2941 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
2944 // Verify the instruction with the target-specific match predicate function.
2945 OS << " // We have a potential match. Check the target predicate to\n"
2946 << " // handle any context sensitive constraints.\n"
2947 << " unsigned MatchResult;\n"
2948 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
2949 << " Match_Success) {\n"
2950 << " Inst.clear();\n"
2951 << " RetCode = MatchResult;\n"
2952 << " HadMatchOtherThanPredicate = true;\n"
2956 // Call the post-processing function, if used.
2957 std::string InsnCleanupFn =
2958 AsmParser->getValueAsString("AsmParserInstCleanup");
2959 if (!InsnCleanupFn.empty())
2960 OS << " " << InsnCleanupFn << "(Inst);\n";
2962 OS << " return Match_Success;\n";
2965 OS << " // Okay, we had no match. Try to return a useful error code.\n";
2966 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
2967 OS << " return RetCode;\n\n";
2968 OS << " // Missing feature matches return which features were missing\n";
2969 OS << " ErrorInfo = MissingFeatures;\n";
2970 OS << " return Match_MissingFeature;\n";
2973 if (Info.OperandMatchInfo.size())
2974 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
2977 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
2982 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
2983 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
2984 AsmMatcherEmitter(RK).run(OS);
2987 } // End llvm namespace