1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "llvm/ADT/PointerUnion.h"
101 #include "llvm/ADT/STLExtras.h"
102 #include "llvm/ADT/SmallPtrSet.h"
103 #include "llvm/ADT/SmallVector.h"
104 #include "llvm/ADT/StringExtras.h"
105 #include "llvm/Support/CommandLine.h"
106 #include "llvm/Support/Debug.h"
107 #include "llvm/Support/ErrorHandling.h"
108 #include "llvm/TableGen/Error.h"
109 #include "llvm/TableGen/Record.h"
110 #include "llvm/TableGen/StringMatcher.h"
111 #include "llvm/TableGen/StringToOffsetTable.h"
112 #include "llvm/TableGen/TableGenBackend.h"
118 #include <forward_list>
119 using namespace llvm;
121 #define DEBUG_TYPE "asm-matcher-emitter"
123 static cl::opt<std::string>
124 MatchPrefix("match-prefix", cl::init(""),
125 cl::desc("Only match instructions with the given prefix"));
128 class AsmMatcherInfo;
129 struct SubtargetFeatureInfo;
131 // Register sets are used as keys in some second-order sets TableGen creates
132 // when generating its data structures. This means that the order of two
133 // RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
134 // can even affect compiler output (at least seen in diagnostics produced when
135 // all matches fail). So we use a type that sorts them consistently.
136 typedef std::set<Record*, LessRecordByID> RegisterSet;
138 class AsmMatcherEmitter {
139 RecordKeeper &Records;
141 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
143 void run(raw_ostream &o);
146 /// ClassInfo - Helper class for storing the information about a particular
147 /// class of operands which can be matched.
150 /// Invalid kind, for use as a sentinel value.
153 /// The class for a particular token.
156 /// The (first) register class, subsequent register classes are
157 /// RegisterClass0+1, and so on.
160 /// The (first) user defined class, subsequent user defined classes are
161 /// UserClass0+1, and so on.
165 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
166 /// N) for the Nth user defined class.
169 /// SuperClasses - The super classes of this class. Note that for simplicities
170 /// sake user operands only record their immediate super class, while register
171 /// operands include all superclasses.
172 std::vector<ClassInfo*> SuperClasses;
174 /// Name - The full class name, suitable for use in an enum.
177 /// ClassName - The unadorned generic name for this class (e.g., Token).
178 std::string ClassName;
180 /// ValueName - The name of the value this class represents; for a token this
181 /// is the literal token string, for an operand it is the TableGen class (or
182 /// empty if this is a derived class).
183 std::string ValueName;
185 /// PredicateMethod - The name of the operand method to test whether the
186 /// operand matches this class; this is not valid for Token or register kinds.
187 std::string PredicateMethod;
189 /// RenderMethod - The name of the operand method to add this operand to an
190 /// MCInst; this is not valid for Token or register kinds.
191 std::string RenderMethod;
193 /// ParserMethod - The name of the operand method to do a target specific
194 /// parsing on the operand.
195 std::string ParserMethod;
197 /// For register classes: the records for all the registers in this class.
198 RegisterSet Registers;
200 /// For custom match classes: the diagnostic kind for when the predicate fails.
201 std::string DiagnosticType;
203 /// isRegisterClass() - Check if this is a register class.
204 bool isRegisterClass() const {
205 return Kind >= RegisterClass0 && Kind < UserClass0;
208 /// isUserClass() - Check if this is a user defined class.
209 bool isUserClass() const {
210 return Kind >= UserClass0;
213 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
214 /// are related if they are in the same class hierarchy.
215 bool isRelatedTo(const ClassInfo &RHS) const {
216 // Tokens are only related to tokens.
217 if (Kind == Token || RHS.Kind == Token)
218 return Kind == Token && RHS.Kind == Token;
220 // Registers classes are only related to registers classes, and only if
221 // their intersection is non-empty.
222 if (isRegisterClass() || RHS.isRegisterClass()) {
223 if (!isRegisterClass() || !RHS.isRegisterClass())
227 std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin());
228 std::set_intersection(Registers.begin(), Registers.end(),
229 RHS.Registers.begin(), RHS.Registers.end(),
230 II, LessRecordByID());
235 // Otherwise we have two users operands; they are related if they are in the
236 // same class hierarchy.
238 // FIXME: This is an oversimplification, they should only be related if they
239 // intersect, however we don't have that information.
240 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
241 const ClassInfo *Root = this;
242 while (!Root->SuperClasses.empty())
243 Root = Root->SuperClasses.front();
245 const ClassInfo *RHSRoot = &RHS;
246 while (!RHSRoot->SuperClasses.empty())
247 RHSRoot = RHSRoot->SuperClasses.front();
249 return Root == RHSRoot;
252 /// isSubsetOf - Test whether this class is a subset of \p RHS.
253 bool isSubsetOf(const ClassInfo &RHS) const {
254 // This is a subset of RHS if it is the same class...
258 // ... or if any of its super classes are a subset of RHS.
259 for (const ClassInfo *CI : SuperClasses)
260 if (CI->isSubsetOf(RHS))
266 /// operator< - Compare two classes.
267 bool operator<(const ClassInfo &RHS) const {
271 // Unrelated classes can be ordered by kind.
272 if (!isRelatedTo(RHS))
273 return Kind < RHS.Kind;
277 llvm_unreachable("Invalid kind!");
280 // This class precedes the RHS if it is a proper subset of the RHS.
283 if (RHS.isSubsetOf(*this))
286 // Otherwise, order by name to ensure we have a total ordering.
287 return ValueName < RHS.ValueName;
292 /// MatchableInfo - Helper class for storing the necessary information for an
293 /// instruction or alias which is capable of being matched.
294 struct MatchableInfo {
296 /// Token - This is the token that the operand came from.
299 /// The unique class instance this operand should match.
302 /// The operand name this is, if anything.
305 /// The suboperand index within SrcOpName, or -1 for the entire operand.
308 /// Register record if this token is singleton register.
309 Record *SingletonReg;
311 explicit AsmOperand(StringRef T) : Token(T), Class(nullptr), SubOpIdx(-1),
312 SingletonReg(nullptr) {}
315 /// ResOperand - This represents a single operand in the result instruction
316 /// generated by the match. In cases (like addressing modes) where a single
317 /// assembler operand expands to multiple MCOperands, this represents the
318 /// single assembler operand, not the MCOperand.
321 /// RenderAsmOperand - This represents an operand result that is
322 /// generated by calling the render method on the assembly operand. The
323 /// corresponding AsmOperand is specified by AsmOperandNum.
326 /// TiedOperand - This represents a result operand that is a duplicate of
327 /// a previous result operand.
330 /// ImmOperand - This represents an immediate value that is dumped into
334 /// RegOperand - This represents a fixed register that is dumped in.
339 /// This is the operand # in the AsmOperands list that this should be
341 unsigned AsmOperandNum;
343 /// TiedOperandNum - This is the (earlier) result operand that should be
345 unsigned TiedOperandNum;
347 /// ImmVal - This is the immediate value added to the instruction.
350 /// Register - This is the register record.
354 /// MINumOperands - The number of MCInst operands populated by this
356 unsigned MINumOperands;
358 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
360 X.Kind = RenderAsmOperand;
361 X.AsmOperandNum = AsmOpNum;
362 X.MINumOperands = NumOperands;
366 static ResOperand getTiedOp(unsigned TiedOperandNum) {
368 X.Kind = TiedOperand;
369 X.TiedOperandNum = TiedOperandNum;
374 static ResOperand getImmOp(int64_t Val) {
382 static ResOperand getRegOp(Record *Reg) {
391 /// AsmVariantID - Target's assembly syntax variant no.
394 /// AsmString - The assembly string for this instruction (with variants
395 /// removed), e.g. "movsx $src, $dst".
396 std::string AsmString;
398 /// TheDef - This is the definition of the instruction or InstAlias that this
399 /// matchable came from.
400 Record *const TheDef;
402 /// DefRec - This is the definition that it came from.
403 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
405 const CodeGenInstruction *getResultInst() const {
406 if (DefRec.is<const CodeGenInstruction*>())
407 return DefRec.get<const CodeGenInstruction*>();
408 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
411 /// ResOperands - This is the operand list that should be built for the result
413 SmallVector<ResOperand, 8> ResOperands;
415 /// Mnemonic - This is the first token of the matched instruction, its
419 /// AsmOperands - The textual operands that this instruction matches,
420 /// annotated with a class and where in the OperandList they were defined.
421 /// This directly corresponds to the tokenized AsmString after the mnemonic is
423 SmallVector<AsmOperand, 8> AsmOperands;
425 /// Predicates - The required subtarget features to match this instruction.
426 SmallVector<const SubtargetFeatureInfo *, 4> RequiredFeatures;
428 /// ConversionFnKind - The enum value which is passed to the generated
429 /// convertToMCInst to convert parsed operands into an MCInst for this
431 std::string ConversionFnKind;
433 /// If this instruction is deprecated in some form.
436 MatchableInfo(const CodeGenInstruction &CGI)
437 : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef), DefRec(&CGI) {
440 MatchableInfo(std::unique_ptr<const CodeGenInstAlias> Alias)
441 : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef), DefRec(Alias.release()) {
445 delete DefRec.dyn_cast<const CodeGenInstAlias*>();
448 // Two-operand aliases clone from the main matchable, but mark the second
449 // operand as a tied operand of the first for purposes of the assembler.
450 void formTwoOperandAlias(StringRef Constraint);
452 void initialize(const AsmMatcherInfo &Info,
453 SmallPtrSetImpl<Record*> &SingletonRegisters,
454 int AsmVariantNo, std::string &RegisterPrefix);
456 /// validate - Return true if this matchable is a valid thing to match against
457 /// and perform a bunch of validity checking.
458 bool validate(StringRef CommentDelimiter, bool Hack) const;
460 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
461 /// if present, from specified token.
463 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info,
464 std::string &RegisterPrefix);
466 /// findAsmOperand - Find the AsmOperand with the specified name and
467 /// suboperand index.
468 int findAsmOperand(StringRef N, int SubOpIdx) const {
469 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
470 if (N == AsmOperands[i].SrcOpName &&
471 SubOpIdx == AsmOperands[i].SubOpIdx)
476 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
477 /// This does not check the suboperand index.
478 int findAsmOperandNamed(StringRef N) const {
479 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
480 if (N == AsmOperands[i].SrcOpName)
485 void buildInstructionResultOperands();
486 void buildAliasResultOperands();
488 /// operator< - Compare two matchables.
489 bool operator<(const MatchableInfo &RHS) const {
490 // The primary comparator is the instruction mnemonic.
491 if (Mnemonic != RHS.Mnemonic)
492 return Mnemonic < RHS.Mnemonic;
494 if (AsmOperands.size() != RHS.AsmOperands.size())
495 return AsmOperands.size() < RHS.AsmOperands.size();
497 // Compare lexicographically by operand. The matcher validates that other
498 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
499 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
500 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
502 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
506 // Give matches that require more features higher precedence. This is useful
507 // because we cannot define AssemblerPredicates with the negation of
508 // processor features. For example, ARM v6 "nop" may be either a HINT or
509 // MOV. With v6, we want to match HINT. The assembler has no way to
510 // predicate MOV under "NoV6", but HINT will always match first because it
511 // requires V6 while MOV does not.
512 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
513 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
518 /// couldMatchAmbiguouslyWith - Check whether this matchable could
519 /// ambiguously match the same set of operands as \p RHS (without being a
520 /// strictly superior match).
521 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) const {
522 // The primary comparator is the instruction mnemonic.
523 if (Mnemonic != RHS.Mnemonic)
526 // The number of operands is unambiguous.
527 if (AsmOperands.size() != RHS.AsmOperands.size())
530 // Otherwise, make sure the ordering of the two instructions is unambiguous
531 // by checking that either (a) a token or operand kind discriminates them,
532 // or (b) the ordering among equivalent kinds is consistent.
534 // Tokens and operand kinds are unambiguous (assuming a correct target
536 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
537 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
538 AsmOperands[i].Class->Kind == ClassInfo::Token)
539 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
540 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
543 // Otherwise, this operand could commute if all operands are equivalent, or
544 // there is a pair of operands that compare less than and a pair that
545 // compare greater than.
546 bool HasLT = false, HasGT = false;
547 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
548 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
550 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
554 return !(HasLT ^ HasGT);
560 void tokenizeAsmString(const AsmMatcherInfo &Info);
563 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
564 /// feature which participates in instruction matching.
565 struct SubtargetFeatureInfo {
566 /// \brief The predicate record for this feature.
569 /// \brief An unique index assigned to represent this feature.
572 SubtargetFeatureInfo(Record *D, uint64_t Idx) : TheDef(D), Index(Idx) {}
574 /// \brief The name of the enumerated constant identifying this feature.
575 std::string getEnumName() const {
576 return "Feature_" + TheDef->getName();
580 errs() << getEnumName() << " " << Index << "\n";
585 struct OperandMatchEntry {
586 unsigned OperandMask;
587 const MatchableInfo* MI;
590 static OperandMatchEntry create(const MatchableInfo *mi, ClassInfo *ci,
593 X.OperandMask = opMask;
601 class AsmMatcherInfo {
604 RecordKeeper &Records;
606 /// The tablegen AsmParser record.
609 /// Target - The target information.
610 CodeGenTarget &Target;
612 /// The classes which are needed for matching.
613 std::forward_list<ClassInfo> Classes;
615 /// The information on the matchables to match.
616 std::vector<std::unique_ptr<MatchableInfo>> Matchables;
618 /// Info for custom matching operands by user defined methods.
619 std::vector<OperandMatchEntry> OperandMatchInfo;
621 /// Map of Register records to their class information.
622 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
623 RegisterClassesTy RegisterClasses;
625 /// Map of Predicate records to their subtarget information.
626 std::map<Record *, SubtargetFeatureInfo, LessRecordByID> SubtargetFeatures;
628 /// Map of AsmOperandClass records to their class information.
629 std::map<Record*, ClassInfo*> AsmOperandClasses;
632 /// Map of token to class information which has already been constructed.
633 std::map<std::string, ClassInfo*> TokenClasses;
635 /// Map of RegisterClass records to their class information.
636 std::map<Record*, ClassInfo*> RegisterClassClasses;
639 /// getTokenClass - Lookup or create the class for the given token.
640 ClassInfo *getTokenClass(StringRef Token);
642 /// getOperandClass - Lookup or create the class for the given operand.
643 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
645 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
647 /// buildRegisterClasses - Build the ClassInfo* instances for register
649 void buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters);
651 /// buildOperandClasses - Build the ClassInfo* instances for user defined
653 void buildOperandClasses();
655 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
657 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
658 MatchableInfo::AsmOperand &Op);
661 AsmMatcherInfo(Record *AsmParser,
662 CodeGenTarget &Target,
663 RecordKeeper &Records);
665 /// buildInfo - Construct the various tables used during matching.
668 /// buildOperandMatchInfo - Build the necessary information to handle user
669 /// defined operand parsing methods.
670 void buildOperandMatchInfo();
672 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
674 const SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
675 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
676 const auto &I = SubtargetFeatures.find(Def);
677 return I == SubtargetFeatures.end() ? nullptr : &I->second;
680 RecordKeeper &getRecords() const {
685 } // End anonymous namespace
687 void MatchableInfo::dump() const {
688 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
690 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
691 const AsmOperand &Op = AsmOperands[i];
692 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
693 errs() << '\"' << Op.Token << "\"\n";
697 static std::pair<StringRef, StringRef>
698 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
699 // Split via the '='.
700 std::pair<StringRef, StringRef> Ops = S.split('=');
701 if (Ops.second == "")
702 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
703 // Trim whitespace and the leading '$' on the operand names.
704 size_t start = Ops.first.find_first_of('$');
705 if (start == std::string::npos)
706 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
707 Ops.first = Ops.first.slice(start + 1, std::string::npos);
708 size_t end = Ops.first.find_last_of(" \t");
709 Ops.first = Ops.first.slice(0, end);
710 // Now the second operand.
711 start = Ops.second.find_first_of('$');
712 if (start == std::string::npos)
713 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
714 Ops.second = Ops.second.slice(start + 1, std::string::npos);
715 end = Ops.second.find_last_of(" \t");
716 Ops.first = Ops.first.slice(0, end);
720 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
721 // Figure out which operands are aliased and mark them as tied.
722 std::pair<StringRef, StringRef> Ops =
723 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
725 // Find the AsmOperands that refer to the operands we're aliasing.
726 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
727 int DstAsmOperand = findAsmOperandNamed(Ops.second);
728 if (SrcAsmOperand == -1)
729 PrintFatalError(TheDef->getLoc(),
730 "unknown source two-operand alias operand '" + Ops.first +
732 if (DstAsmOperand == -1)
733 PrintFatalError(TheDef->getLoc(),
734 "unknown destination two-operand alias operand '" +
737 // Find the ResOperand that refers to the operand we're aliasing away
738 // and update it to refer to the combined operand instead.
739 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
740 ResOperand &Op = ResOperands[i];
741 if (Op.Kind == ResOperand::RenderAsmOperand &&
742 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
743 Op.AsmOperandNum = DstAsmOperand;
747 // Remove the AsmOperand for the alias operand.
748 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
749 // Adjust the ResOperand references to any AsmOperands that followed
750 // the one we just deleted.
751 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
752 ResOperand &Op = ResOperands[i];
755 // Nothing to do for operands that don't reference AsmOperands.
757 case ResOperand::RenderAsmOperand:
758 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
761 case ResOperand::TiedOperand:
762 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
769 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
770 SmallPtrSetImpl<Record*> &SingletonRegisters,
771 int AsmVariantNo, std::string &RegisterPrefix) {
772 AsmVariantID = AsmVariantNo;
774 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
776 tokenizeAsmString(Info);
778 // Compute the require features.
779 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
780 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
781 if (const SubtargetFeatureInfo *Feature =
782 Info.getSubtargetFeature(Predicates[i]))
783 RequiredFeatures.push_back(Feature);
785 // Collect singleton registers, if used.
786 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
787 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix);
788 if (Record *Reg = AsmOperands[i].SingletonReg)
789 SingletonRegisters.insert(Reg);
792 const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask");
794 DepMask = TheDef->getValue("ComplexDeprecationPredicate");
797 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
800 /// tokenizeAsmString - Tokenize a simplified assembly string.
801 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
802 StringRef String = AsmString;
805 for (unsigned i = 0, e = String.size(); i != e; ++i) {
815 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
818 if (!isspace(String[i]) && String[i] != ',')
819 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
825 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
829 assert(i != String.size() && "Invalid quoted character");
830 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
836 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
840 // If this isn't "${", treat like a normal token.
841 if (i + 1 == String.size() || String[i + 1] != '{') {
846 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
847 assert(End != String.end() && "Missing brace in operand reference!");
848 size_t EndPos = End - String.begin();
849 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
856 if (!Info.AsmParser->getValueAsBit("MnemonicContainsDot")) {
858 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
868 if (InTok && Prev != String.size())
869 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
871 // The first token of the instruction is the mnemonic, which must be a
872 // simple string, not a $foo variable or a singleton register.
873 if (AsmOperands.empty())
874 PrintFatalError(TheDef->getLoc(),
875 "Instruction '" + TheDef->getName() + "' has no tokens");
876 Mnemonic = AsmOperands[0].Token;
877 if (Mnemonic.empty())
878 PrintFatalError(TheDef->getLoc(),
879 "Missing instruction mnemonic");
880 // FIXME : Check and raise an error if it is a register.
881 if (Mnemonic[0] == '$')
882 PrintFatalError(TheDef->getLoc(),
883 "Invalid instruction mnemonic '" + Mnemonic + "'!");
885 // Remove the first operand, it is tracked in the mnemonic field.
886 AsmOperands.erase(AsmOperands.begin());
889 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
890 // Reject matchables with no .s string.
891 if (AsmString.empty())
892 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
894 // Reject any matchables with a newline in them, they should be marked
895 // isCodeGenOnly if they are pseudo instructions.
896 if (AsmString.find('\n') != std::string::npos)
897 PrintFatalError(TheDef->getLoc(),
898 "multiline instruction is not valid for the asmparser, "
899 "mark it isCodeGenOnly");
901 // Remove comments from the asm string. We know that the asmstring only
903 if (!CommentDelimiter.empty() &&
904 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
905 PrintFatalError(TheDef->getLoc(),
906 "asmstring for instruction has comment character in it, "
907 "mark it isCodeGenOnly");
909 // Reject matchables with operand modifiers, these aren't something we can
910 // handle, the target should be refactored to use operands instead of
913 // Also, check for instructions which reference the operand multiple times;
914 // this implies a constraint we would not honor.
915 std::set<std::string> OperandNames;
916 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
917 StringRef Tok = AsmOperands[i].Token;
918 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
919 PrintFatalError(TheDef->getLoc(),
920 "matchable with operand modifier '" + Tok +
921 "' not supported by asm matcher. Mark isCodeGenOnly!");
923 // Verify that any operand is only mentioned once.
924 // We reject aliases and ignore instructions for now.
925 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
927 PrintFatalError(TheDef->getLoc(),
928 "ERROR: matchable with tied operand '" + Tok +
929 "' can never be matched!");
930 // FIXME: Should reject these. The ARM backend hits this with $lane in a
931 // bunch of instructions. It is unclear what the right answer is.
933 errs() << "warning: '" << TheDef->getName() << "': "
934 << "ignoring instruction with tied operand '"
944 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
945 /// if present, from specified token.
947 extractSingletonRegisterForAsmOperand(unsigned OperandNo,
948 const AsmMatcherInfo &Info,
949 std::string &RegisterPrefix) {
950 StringRef Tok = AsmOperands[OperandNo].Token;
951 if (RegisterPrefix.empty()) {
952 std::string LoweredTok = Tok.lower();
953 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
954 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
958 if (!Tok.startswith(RegisterPrefix))
961 StringRef RegName = Tok.substr(RegisterPrefix.size());
962 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
963 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
965 // If there is no register prefix (i.e. "%" in "%eax"), then this may
966 // be some random non-register token, just ignore it.
970 static std::string getEnumNameForToken(StringRef Str) {
973 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
975 case '*': Res += "_STAR_"; break;
976 case '%': Res += "_PCT_"; break;
977 case ':': Res += "_COLON_"; break;
978 case '!': Res += "_EXCLAIM_"; break;
979 case '.': Res += "_DOT_"; break;
980 case '<': Res += "_LT_"; break;
981 case '>': Res += "_GT_"; break;
982 case '-': Res += "_MINUS_"; break;
984 if ((*it >= 'A' && *it <= 'Z') ||
985 (*it >= 'a' && *it <= 'z') ||
986 (*it >= '0' && *it <= '9'))
989 Res += "_" + utostr((unsigned) *it) + "_";
996 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
997 ClassInfo *&Entry = TokenClasses[Token];
1000 Classes.emplace_front();
1001 Entry = &Classes.front();
1002 Entry->Kind = ClassInfo::Token;
1003 Entry->ClassName = "Token";
1004 Entry->Name = "MCK_" + getEnumNameForToken(Token);
1005 Entry->ValueName = Token;
1006 Entry->PredicateMethod = "<invalid>";
1007 Entry->RenderMethod = "<invalid>";
1008 Entry->ParserMethod = "";
1009 Entry->DiagnosticType = "";
1016 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1018 Record *Rec = OI.Rec;
1020 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1021 return getOperandClass(Rec, SubOpIdx);
1025 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1026 if (Rec->isSubClassOf("RegisterOperand")) {
1027 // RegisterOperand may have an associated ParserMatchClass. If it does,
1028 // use it, else just fall back to the underlying register class.
1029 const RecordVal *R = Rec->getValue("ParserMatchClass");
1030 if (!R || !R->getValue())
1031 PrintFatalError("Record `" + Rec->getName() +
1032 "' does not have a ParserMatchClass!\n");
1034 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1035 Record *MatchClass = DI->getDef();
1036 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1040 // No custom match class. Just use the register class.
1041 Record *ClassRec = Rec->getValueAsDef("RegClass");
1043 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1044 "' has no associated register class!\n");
1045 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1047 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1051 if (Rec->isSubClassOf("RegisterClass")) {
1052 if (ClassInfo *CI = RegisterClassClasses[Rec])
1054 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1057 if (!Rec->isSubClassOf("Operand"))
1058 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1059 "' does not derive from class Operand!\n");
1060 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1061 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1064 PrintFatalError(Rec->getLoc(), "operand has no match class!");
1067 struct LessRegisterSet {
1068 bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const {
1069 // std::set<T> defines its own compariso "operator<", but it
1070 // performs a lexicographical comparison by T's innate comparison
1071 // for some reason. We don't want non-deterministic pointer
1072 // comparisons so use this instead.
1073 return std::lexicographical_compare(LHS.begin(), LHS.end(),
1074 RHS.begin(), RHS.end(),
1079 void AsmMatcherInfo::
1080 buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
1081 const auto &Registers = Target.getRegBank().getRegisters();
1082 auto &RegClassList = Target.getRegBank().getRegClasses();
1084 typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet;
1086 // The register sets used for matching.
1087 RegisterSetSet RegisterSets;
1089 // Gather the defined sets.
1090 for (const CodeGenRegisterClass &RC : RegClassList)
1091 RegisterSets.insert(
1092 RegisterSet(RC.getOrder().begin(), RC.getOrder().end()));
1094 // Add any required singleton sets.
1095 for (Record *Rec : SingletonRegisters) {
1096 RegisterSets.insert(RegisterSet(&Rec, &Rec + 1));
1099 // Introduce derived sets where necessary (when a register does not determine
1100 // a unique register set class), and build the mapping of registers to the set
1101 // they should classify to.
1102 std::map<Record*, RegisterSet> RegisterMap;
1103 for (const CodeGenRegister &CGR : Registers) {
1104 // Compute the intersection of all sets containing this register.
1105 RegisterSet ContainingSet;
1107 for (const RegisterSet &RS : RegisterSets) {
1108 if (!RS.count(CGR.TheDef))
1111 if (ContainingSet.empty()) {
1117 std::swap(Tmp, ContainingSet);
1118 std::insert_iterator<RegisterSet> II(ContainingSet,
1119 ContainingSet.begin());
1120 std::set_intersection(Tmp.begin(), Tmp.end(), RS.begin(), RS.end(), II,
1124 if (!ContainingSet.empty()) {
1125 RegisterSets.insert(ContainingSet);
1126 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1130 // Construct the register classes.
1131 std::map<RegisterSet, ClassInfo*, LessRegisterSet> RegisterSetClasses;
1133 for (const RegisterSet &RS : RegisterSets) {
1134 Classes.emplace_front();
1135 ClassInfo *CI = &Classes.front();
1136 CI->Kind = ClassInfo::RegisterClass0 + Index;
1137 CI->ClassName = "Reg" + utostr(Index);
1138 CI->Name = "MCK_Reg" + utostr(Index);
1140 CI->PredicateMethod = ""; // unused
1141 CI->RenderMethod = "addRegOperands";
1143 // FIXME: diagnostic type.
1144 CI->DiagnosticType = "";
1145 RegisterSetClasses.insert(std::make_pair(RS, CI));
1149 // Find the superclasses; we could compute only the subgroup lattice edges,
1150 // but there isn't really a point.
1151 for (const RegisterSet &RS : RegisterSets) {
1152 ClassInfo *CI = RegisterSetClasses[RS];
1153 for (const RegisterSet &RS2 : RegisterSets)
1155 std::includes(RS2.begin(), RS2.end(), RS.begin(), RS.end(),
1157 CI->SuperClasses.push_back(RegisterSetClasses[RS2]);
1160 // Name the register classes which correspond to a user defined RegisterClass.
1161 for (const CodeGenRegisterClass &RC : RegClassList) {
1162 // Def will be NULL for non-user defined register classes.
1163 Record *Def = RC.getDef();
1166 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(),
1167 RC.getOrder().end())];
1168 if (CI->ValueName.empty()) {
1169 CI->ClassName = RC.getName();
1170 CI->Name = "MCK_" + RC.getName();
1171 CI->ValueName = RC.getName();
1173 CI->ValueName = CI->ValueName + "," + RC.getName();
1175 RegisterClassClasses.insert(std::make_pair(Def, CI));
1178 // Populate the map for individual registers.
1179 for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(),
1180 ie = RegisterMap.end(); it != ie; ++it)
1181 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1183 // Name the register classes which correspond to singleton registers.
1184 for (Record *Rec : SingletonRegisters) {
1185 ClassInfo *CI = RegisterClasses[Rec];
1186 assert(CI && "Missing singleton register class info!");
1188 if (CI->ValueName.empty()) {
1189 CI->ClassName = Rec->getName();
1190 CI->Name = "MCK_" + Rec->getName();
1191 CI->ValueName = Rec->getName();
1193 CI->ValueName = CI->ValueName + "," + Rec->getName();
1197 void AsmMatcherInfo::buildOperandClasses() {
1198 std::vector<Record*> AsmOperands =
1199 Records.getAllDerivedDefinitions("AsmOperandClass");
1201 // Pre-populate AsmOperandClasses map.
1202 for (Record *Rec : AsmOperands) {
1203 Classes.emplace_front();
1204 AsmOperandClasses[Rec] = &Classes.front();
1208 for (Record *Rec : AsmOperands) {
1209 ClassInfo *CI = AsmOperandClasses[Rec];
1210 CI->Kind = ClassInfo::UserClass0 + Index;
1212 ListInit *Supers = Rec->getValueAsListInit("SuperClasses");
1213 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
1214 DefInit *DI = dyn_cast<DefInit>(Supers->getElement(i));
1216 PrintError(Rec->getLoc(), "Invalid super class reference!");
1220 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1222 PrintError(Rec->getLoc(), "Invalid super class reference!");
1224 CI->SuperClasses.push_back(SC);
1226 CI->ClassName = Rec->getValueAsString("Name");
1227 CI->Name = "MCK_" + CI->ClassName;
1228 CI->ValueName = Rec->getName();
1230 // Get or construct the predicate method name.
1231 Init *PMName = Rec->getValueInit("PredicateMethod");
1232 if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1233 CI->PredicateMethod = SI->getValue();
1235 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1236 CI->PredicateMethod = "is" + CI->ClassName;
1239 // Get or construct the render method name.
1240 Init *RMName = Rec->getValueInit("RenderMethod");
1241 if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1242 CI->RenderMethod = SI->getValue();
1244 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1245 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1248 // Get the parse method name or leave it as empty.
1249 Init *PRMName = Rec->getValueInit("ParserMethod");
1250 if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1251 CI->ParserMethod = SI->getValue();
1253 // Get the diagnostic type or leave it as empty.
1254 // Get the parse method name or leave it as empty.
1255 Init *DiagnosticType = Rec->getValueInit("DiagnosticType");
1256 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1257 CI->DiagnosticType = SI->getValue();
1263 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1264 CodeGenTarget &target,
1265 RecordKeeper &records)
1266 : Records(records), AsmParser(asmParser), Target(target) {
1269 /// buildOperandMatchInfo - Build the necessary information to handle user
1270 /// defined operand parsing methods.
1271 void AsmMatcherInfo::buildOperandMatchInfo() {
1273 /// Map containing a mask with all operands indices that can be found for
1274 /// that class inside a instruction.
1275 typedef std::map<ClassInfo *, unsigned, less_ptr<ClassInfo>> OpClassMaskTy;
1276 OpClassMaskTy OpClassMask;
1278 for (const auto &MI : Matchables) {
1279 OpClassMask.clear();
1281 // Keep track of all operands of this instructions which belong to the
1283 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
1284 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
1285 if (Op.Class->ParserMethod.empty())
1287 unsigned &OperandMask = OpClassMask[Op.Class];
1288 OperandMask |= (1 << i);
1291 // Generate operand match info for each mnemonic/operand class pair.
1292 for (const auto &OCM : OpClassMask) {
1293 unsigned OpMask = OCM.second;
1294 ClassInfo *CI = OCM.first;
1295 OperandMatchInfo.push_back(OperandMatchEntry::create(MI.get(), CI,
1301 void AsmMatcherInfo::buildInfo() {
1302 // Build information about all of the AssemblerPredicates.
1303 std::vector<Record*> AllPredicates =
1304 Records.getAllDerivedDefinitions("Predicate");
1305 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1306 Record *Pred = AllPredicates[i];
1307 // Ignore predicates that are not intended for the assembler.
1308 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1311 if (Pred->getName().empty())
1312 PrintFatalError(Pred->getLoc(), "Predicate has no name!");
1314 SubtargetFeatures.insert(std::make_pair(
1315 Pred, SubtargetFeatureInfo(Pred, SubtargetFeatures.size())));
1316 DEBUG(SubtargetFeatures.find(Pred)->second.dump());
1317 assert(SubtargetFeatures.size() <= 64 && "Too many subtarget features!");
1320 // Parse the instructions; we need to do this first so that we can gather the
1321 // singleton register classes.
1322 SmallPtrSet<Record*, 16> SingletonRegisters;
1323 unsigned VariantCount = Target.getAsmParserVariantCount();
1324 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1325 Record *AsmVariant = Target.getAsmParserVariant(VC);
1326 std::string CommentDelimiter =
1327 AsmVariant->getValueAsString("CommentDelimiter");
1328 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1329 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1331 for (const CodeGenInstruction *CGI : Target.instructions()) {
1333 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1334 // filter the set of instructions we consider.
1335 if (!StringRef(CGI->TheDef->getName()).startswith(MatchPrefix))
1338 // Ignore "codegen only" instructions.
1339 if (CGI->TheDef->getValueAsBit("isCodeGenOnly"))
1342 std::unique_ptr<MatchableInfo> II(new MatchableInfo(*CGI));
1344 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1346 // Ignore instructions which shouldn't be matched and diagnose invalid
1347 // instruction definitions with an error.
1348 if (!II->validate(CommentDelimiter, true))
1351 Matchables.push_back(std::move(II));
1354 // Parse all of the InstAlias definitions and stick them in the list of
1356 std::vector<Record*> AllInstAliases =
1357 Records.getAllDerivedDefinitions("InstAlias");
1358 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1359 auto Alias = llvm::make_unique<CodeGenInstAlias>(AllInstAliases[i],
1360 AsmVariantNo, Target);
1362 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1363 // filter the set of instruction aliases we consider, based on the target
1365 if (!StringRef(Alias->ResultInst->TheDef->getName())
1366 .startswith( MatchPrefix))
1369 std::unique_ptr<MatchableInfo> II(new MatchableInfo(std::move(Alias)));
1371 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1373 // Validate the alias definitions.
1374 II->validate(CommentDelimiter, false);
1376 Matchables.push_back(std::move(II));
1380 // Build info for the register classes.
1381 buildRegisterClasses(SingletonRegisters);
1383 // Build info for the user defined assembly operand classes.
1384 buildOperandClasses();
1386 // Build the information about matchables, now that we have fully formed
1388 std::vector<std::unique_ptr<MatchableInfo>> NewMatchables;
1389 for (auto &II : Matchables) {
1390 // Parse the tokens after the mnemonic.
1391 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1392 // don't precompute the loop bound.
1393 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1394 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1395 StringRef Token = Op.Token;
1397 // Check for singleton registers.
1398 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1399 Op.Class = RegisterClasses[RegRecord];
1400 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1401 "Unexpected class for singleton register");
1405 // Check for simple tokens.
1406 if (Token[0] != '$') {
1407 Op.Class = getTokenClass(Token);
1411 if (Token.size() > 1 && isdigit(Token[1])) {
1412 Op.Class = getTokenClass(Token);
1416 // Otherwise this is an operand reference.
1417 StringRef OperandName;
1418 if (Token[1] == '{')
1419 OperandName = Token.substr(2, Token.size() - 3);
1421 OperandName = Token.substr(1);
1423 if (II->DefRec.is<const CodeGenInstruction*>())
1424 buildInstructionOperandReference(II.get(), OperandName, i);
1426 buildAliasOperandReference(II.get(), OperandName, Op);
1429 if (II->DefRec.is<const CodeGenInstruction*>()) {
1430 II->buildInstructionResultOperands();
1431 // If the instruction has a two-operand alias, build up the
1432 // matchable here. We'll add them in bulk at the end to avoid
1433 // confusing this loop.
1434 std::string Constraint =
1435 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1436 if (Constraint != "") {
1437 // Start by making a copy of the original matchable.
1438 std::unique_ptr<MatchableInfo> AliasII(new MatchableInfo(*II));
1440 // Adjust it to be a two-operand alias.
1441 AliasII->formTwoOperandAlias(Constraint);
1443 // Add the alias to the matchables list.
1444 NewMatchables.push_back(std::move(AliasII));
1447 II->buildAliasResultOperands();
1449 if (!NewMatchables.empty())
1450 std::move(NewMatchables.begin(), NewMatchables.end(),
1451 std::back_inserter(Matchables));
1453 // Process token alias definitions and set up the associated superclass
1455 std::vector<Record*> AllTokenAliases =
1456 Records.getAllDerivedDefinitions("TokenAlias");
1457 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1458 Record *Rec = AllTokenAliases[i];
1459 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1460 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1461 if (FromClass == ToClass)
1462 PrintFatalError(Rec->getLoc(),
1463 "error: Destination value identical to source value.");
1464 FromClass->SuperClasses.push_back(ToClass);
1467 // Reorder classes so that classes precede super classes.
1471 /// buildInstructionOperandReference - The specified operand is a reference to a
1472 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1473 void AsmMatcherInfo::
1474 buildInstructionOperandReference(MatchableInfo *II,
1475 StringRef OperandName,
1476 unsigned AsmOpIdx) {
1477 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1478 const CGIOperandList &Operands = CGI.Operands;
1479 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1481 // Map this token to an operand.
1483 if (!Operands.hasOperandNamed(OperandName, Idx))
1484 PrintFatalError(II->TheDef->getLoc(),
1485 "error: unable to find operand: '" + OperandName + "'");
1487 // If the instruction operand has multiple suboperands, but the parser
1488 // match class for the asm operand is still the default "ImmAsmOperand",
1489 // then handle each suboperand separately.
1490 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1491 Record *Rec = Operands[Idx].Rec;
1492 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1493 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1494 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1495 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1496 StringRef Token = Op->Token; // save this in case Op gets moved
1497 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1498 MatchableInfo::AsmOperand NewAsmOp(Token);
1499 NewAsmOp.SubOpIdx = SI;
1500 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1502 // Replace Op with first suboperand.
1503 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1508 // Set up the operand class.
1509 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1511 // If the named operand is tied, canonicalize it to the untied operand.
1512 // For example, something like:
1513 // (outs GPR:$dst), (ins GPR:$src)
1514 // with an asmstring of
1516 // we want to canonicalize to:
1518 // so that we know how to provide the $dst operand when filling in the result.
1520 if (Operands[Idx].MINumOperands == 1)
1521 OITied = Operands[Idx].getTiedRegister();
1523 // The tied operand index is an MIOperand index, find the operand that
1525 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1526 OperandName = Operands[Idx.first].Name;
1527 Op->SubOpIdx = Idx.second;
1530 Op->SrcOpName = OperandName;
1533 /// buildAliasOperandReference - When parsing an operand reference out of the
1534 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1535 /// operand reference is by looking it up in the result pattern definition.
1536 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1537 StringRef OperandName,
1538 MatchableInfo::AsmOperand &Op) {
1539 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1541 // Set up the operand class.
1542 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1543 if (CGA.ResultOperands[i].isRecord() &&
1544 CGA.ResultOperands[i].getName() == OperandName) {
1545 // It's safe to go with the first one we find, because CodeGenInstAlias
1546 // validates that all operands with the same name have the same record.
1547 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1548 // Use the match class from the Alias definition, not the
1549 // destination instruction, as we may have an immediate that's
1550 // being munged by the match class.
1551 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1553 Op.SrcOpName = OperandName;
1557 PrintFatalError(II->TheDef->getLoc(),
1558 "error: unable to find operand: '" + OperandName + "'");
1561 void MatchableInfo::buildInstructionResultOperands() {
1562 const CodeGenInstruction *ResultInst = getResultInst();
1564 // Loop over all operands of the result instruction, determining how to
1566 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1567 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1569 // If this is a tied operand, just copy from the previously handled operand.
1571 if (OpInfo.MINumOperands == 1)
1572 TiedOp = OpInfo.getTiedRegister();
1574 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1578 // Find out what operand from the asmparser this MCInst operand comes from.
1579 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1580 if (OpInfo.Name.empty() || SrcOperand == -1) {
1581 // This may happen for operands that are tied to a suboperand of a
1582 // complex operand. Simply use a dummy value here; nobody should
1583 // use this operand slot.
1584 // FIXME: The long term goal is for the MCOperand list to not contain
1585 // tied operands at all.
1586 ResOperands.push_back(ResOperand::getImmOp(0));
1590 // Check if the one AsmOperand populates the entire operand.
1591 unsigned NumOperands = OpInfo.MINumOperands;
1592 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1593 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1597 // Add a separate ResOperand for each suboperand.
1598 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1599 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1600 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1601 "unexpected AsmOperands for suboperands");
1602 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1607 void MatchableInfo::buildAliasResultOperands() {
1608 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1609 const CodeGenInstruction *ResultInst = getResultInst();
1611 // Loop over all operands of the result instruction, determining how to
1613 unsigned AliasOpNo = 0;
1614 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1615 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1616 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1618 // If this is a tied operand, just copy from the previously handled operand.
1620 if (OpInfo->MINumOperands == 1)
1621 TiedOp = OpInfo->getTiedRegister();
1623 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1627 // Handle all the suboperands for this operand.
1628 const std::string &OpName = OpInfo->Name;
1629 for ( ; AliasOpNo < LastOpNo &&
1630 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1631 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1633 // Find out what operand from the asmparser that this MCInst operand
1635 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1636 case CodeGenInstAlias::ResultOperand::K_Record: {
1637 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1638 int SrcOperand = findAsmOperand(Name, SubIdx);
1639 if (SrcOperand == -1)
1640 PrintFatalError(TheDef->getLoc(), "Instruction '" +
1641 TheDef->getName() + "' has operand '" + OpName +
1642 "' that doesn't appear in asm string!");
1643 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1644 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1648 case CodeGenInstAlias::ResultOperand::K_Imm: {
1649 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1650 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1653 case CodeGenInstAlias::ResultOperand::K_Reg: {
1654 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1655 ResOperands.push_back(ResOperand::getRegOp(Reg));
1663 static unsigned getConverterOperandID(const std::string &Name,
1664 SetVector<std::string> &Table,
1666 IsNew = Table.insert(Name);
1668 unsigned ID = IsNew ? Table.size() - 1 :
1669 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1671 assert(ID < Table.size());
1677 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1678 std::vector<std::unique_ptr<MatchableInfo>> &Infos,
1680 SetVector<std::string> OperandConversionKinds;
1681 SetVector<std::string> InstructionConversionKinds;
1682 std::vector<std::vector<uint8_t> > ConversionTable;
1683 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1685 // TargetOperandClass - This is the target's operand class, like X86Operand.
1686 std::string TargetOperandClass = Target.getName() + "Operand";
1688 // Write the convert function to a separate stream, so we can drop it after
1689 // the enum. We'll build up the conversion handlers for the individual
1690 // operand types opportunistically as we encounter them.
1691 std::string ConvertFnBody;
1692 raw_string_ostream CvtOS(ConvertFnBody);
1693 // Start the unified conversion function.
1694 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1695 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1696 << "unsigned Opcode,\n"
1697 << " const OperandVector"
1698 << " &Operands) {\n"
1699 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1700 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1701 << " Inst.setOpcode(Opcode);\n"
1702 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1703 << " switch (*p) {\n"
1704 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1705 << " case CVT_Reg:\n"
1706 << " static_cast<" << TargetOperandClass
1707 << "&>(*Operands[*(p + 1)]).addRegOperands(Inst, 1);\n"
1709 << " case CVT_Tied:\n"
1710 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1713 std::string OperandFnBody;
1714 raw_string_ostream OpOS(OperandFnBody);
1715 // Start the operand number lookup function.
1716 OpOS << "void " << Target.getName() << ClassName << "::\n"
1717 << "convertToMapAndConstraints(unsigned Kind,\n";
1719 OpOS << "const OperandVector &Operands) {\n"
1720 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1721 << " unsigned NumMCOperands = 0;\n"
1722 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1723 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1724 << " switch (*p) {\n"
1725 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1726 << " case CVT_Reg:\n"
1727 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1728 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
1729 << " ++NumMCOperands;\n"
1731 << " case CVT_Tied:\n"
1732 << " ++NumMCOperands;\n"
1735 // Pre-populate the operand conversion kinds with the standard always
1736 // available entries.
1737 OperandConversionKinds.insert("CVT_Done");
1738 OperandConversionKinds.insert("CVT_Reg");
1739 OperandConversionKinds.insert("CVT_Tied");
1740 enum { CVT_Done, CVT_Reg, CVT_Tied };
1742 for (auto &II : Infos) {
1743 // Check if we have a custom match function.
1744 std::string AsmMatchConverter =
1745 II->getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1746 if (!AsmMatchConverter.empty()) {
1747 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1748 II->ConversionFnKind = Signature;
1750 // Check if we have already generated this signature.
1751 if (!InstructionConversionKinds.insert(Signature))
1754 // Remember this converter for the kind enum.
1755 unsigned KindID = OperandConversionKinds.size();
1756 OperandConversionKinds.insert("CVT_" +
1757 getEnumNameForToken(AsmMatchConverter));
1759 // Add the converter row for this instruction.
1760 ConversionTable.push_back(std::vector<uint8_t>());
1761 ConversionTable.back().push_back(KindID);
1762 ConversionTable.back().push_back(CVT_Done);
1764 // Add the handler to the conversion driver function.
1765 CvtOS << " case CVT_"
1766 << getEnumNameForToken(AsmMatchConverter) << ":\n"
1767 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1770 // FIXME: Handle the operand number lookup for custom match functions.
1774 // Build the conversion function signature.
1775 std::string Signature = "Convert";
1777 std::vector<uint8_t> ConversionRow;
1779 // Compute the convert enum and the case body.
1780 MaxRowLength = std::max(MaxRowLength, II->ResOperands.size()*2 + 1 );
1782 for (unsigned i = 0, e = II->ResOperands.size(); i != e; ++i) {
1783 const MatchableInfo::ResOperand &OpInfo = II->ResOperands[i];
1785 // Generate code to populate each result operand.
1786 switch (OpInfo.Kind) {
1787 case MatchableInfo::ResOperand::RenderAsmOperand: {
1788 // This comes from something we parsed.
1789 const MatchableInfo::AsmOperand &Op =
1790 II->AsmOperands[OpInfo.AsmOperandNum];
1792 // Registers are always converted the same, don't duplicate the
1793 // conversion function based on them.
1796 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1798 Signature += utostr(OpInfo.MINumOperands);
1799 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1801 // Add the conversion kind, if necessary, and get the associated ID
1802 // the index of its entry in the vector).
1803 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1804 Op.Class->RenderMethod);
1805 Name = getEnumNameForToken(Name);
1807 bool IsNewConverter = false;
1808 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1811 // Add the operand entry to the instruction kind conversion row.
1812 ConversionRow.push_back(ID);
1813 ConversionRow.push_back(OpInfo.AsmOperandNum + 1);
1815 if (!IsNewConverter)
1818 // This is a new operand kind. Add a handler for it to the
1819 // converter driver.
1820 CvtOS << " case " << Name << ":\n"
1821 << " static_cast<" << TargetOperandClass
1822 << "&>(*Operands[*(p + 1)])." << Op.Class->RenderMethod
1823 << "(Inst, " << OpInfo.MINumOperands << ");\n"
1826 // Add a handler for the operand number lookup.
1827 OpOS << " case " << Name << ":\n"
1828 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
1830 if (Op.Class->isRegisterClass())
1831 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
1833 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
1834 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
1838 case MatchableInfo::ResOperand::TiedOperand: {
1839 // If this operand is tied to a previous one, just copy the MCInst
1840 // operand from the earlier one.We can only tie single MCOperand values.
1841 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1842 unsigned TiedOp = OpInfo.TiedOperandNum;
1843 assert(i > TiedOp && "Tied operand precedes its target!");
1844 Signature += "__Tie" + utostr(TiedOp);
1845 ConversionRow.push_back(CVT_Tied);
1846 ConversionRow.push_back(TiedOp);
1849 case MatchableInfo::ResOperand::ImmOperand: {
1850 int64_t Val = OpInfo.ImmVal;
1851 std::string Ty = "imm_" + itostr(Val);
1852 Ty = getEnumNameForToken(Ty);
1853 Signature += "__" + Ty;
1855 std::string Name = "CVT_" + Ty;
1856 bool IsNewConverter = false;
1857 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1859 // Add the operand entry to the instruction kind conversion row.
1860 ConversionRow.push_back(ID);
1861 ConversionRow.push_back(0);
1863 if (!IsNewConverter)
1866 CvtOS << " case " << Name << ":\n"
1867 << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"
1870 OpOS << " case " << Name << ":\n"
1871 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1872 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
1873 << " ++NumMCOperands;\n"
1877 case MatchableInfo::ResOperand::RegOperand: {
1878 std::string Reg, Name;
1879 if (!OpInfo.Register) {
1883 Reg = getQualifiedName(OpInfo.Register);
1884 Name = "reg" + OpInfo.Register->getName();
1886 Signature += "__" + Name;
1887 Name = "CVT_" + Name;
1888 bool IsNewConverter = false;
1889 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1891 // Add the operand entry to the instruction kind conversion row.
1892 ConversionRow.push_back(ID);
1893 ConversionRow.push_back(0);
1895 if (!IsNewConverter)
1897 CvtOS << " case " << Name << ":\n"
1898 << " Inst.addOperand(MCOperand::CreateReg(" << Reg << "));\n"
1901 OpOS << " case " << Name << ":\n"
1902 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1903 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
1904 << " ++NumMCOperands;\n"
1910 // If there were no operands, add to the signature to that effect
1911 if (Signature == "Convert")
1912 Signature += "_NoOperands";
1914 II->ConversionFnKind = Signature;
1916 // Save the signature. If we already have it, don't add a new row
1918 if (!InstructionConversionKinds.insert(Signature))
1921 // Add the row to the table.
1922 ConversionTable.push_back(ConversionRow);
1925 // Finish up the converter driver function.
1926 CvtOS << " }\n }\n}\n\n";
1928 // Finish up the operand number lookup function.
1929 OpOS << " }\n }\n}\n\n";
1931 OS << "namespace {\n";
1933 // Output the operand conversion kind enum.
1934 OS << "enum OperatorConversionKind {\n";
1935 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i)
1936 OS << " " << OperandConversionKinds[i] << ",\n";
1937 OS << " CVT_NUM_CONVERTERS\n";
1940 // Output the instruction conversion kind enum.
1941 OS << "enum InstructionConversionKind {\n";
1942 for (SetVector<std::string>::const_iterator
1943 i = InstructionConversionKinds.begin(),
1944 e = InstructionConversionKinds.end(); i != e; ++i)
1945 OS << " " << *i << ",\n";
1946 OS << " CVT_NUM_SIGNATURES\n";
1950 OS << "} // end anonymous namespace\n\n";
1952 // Output the conversion table.
1953 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
1954 << MaxRowLength << "] = {\n";
1956 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
1957 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
1958 OS << " // " << InstructionConversionKinds[Row] << "\n";
1960 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
1961 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
1962 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
1963 OS << "CVT_Done },\n";
1968 // Spit out the conversion driver function.
1971 // Spit out the operand number lookup function.
1975 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
1976 static void emitMatchClassEnumeration(CodeGenTarget &Target,
1977 std::forward_list<ClassInfo> &Infos,
1979 OS << "namespace {\n\n";
1981 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1982 << "/// instruction matching.\n";
1983 OS << "enum MatchClassKind {\n";
1984 OS << " InvalidMatchClass = 0,\n";
1985 for (const auto &CI : Infos) {
1986 OS << " " << CI.Name << ", // ";
1987 if (CI.Kind == ClassInfo::Token) {
1988 OS << "'" << CI.ValueName << "'\n";
1989 } else if (CI.isRegisterClass()) {
1990 if (!CI.ValueName.empty())
1991 OS << "register class '" << CI.ValueName << "'\n";
1993 OS << "derived register class\n";
1995 OS << "user defined class '" << CI.ValueName << "'\n";
1998 OS << " NumMatchClassKinds\n";
2004 /// emitValidateOperandClass - Emit the function to validate an operand class.
2005 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2007 OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, "
2008 << "MatchClassKind Kind) {\n";
2009 OS << " " << Info.Target.getName() << "Operand &Operand = ("
2010 << Info.Target.getName() << "Operand&)GOp;\n";
2012 // The InvalidMatchClass is not to match any operand.
2013 OS << " if (Kind == InvalidMatchClass)\n";
2014 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2016 // Check for Token operands first.
2017 // FIXME: Use a more specific diagnostic type.
2018 OS << " if (Operand.isToken())\n";
2019 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2020 << " MCTargetAsmParser::Match_Success :\n"
2021 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2023 // Check the user classes. We don't care what order since we're only
2024 // actually matching against one of them.
2025 for (const auto &CI : Info.Classes) {
2026 if (!CI.isUserClass())
2029 OS << " // '" << CI.ClassName << "' class\n";
2030 OS << " if (Kind == " << CI.Name << ") {\n";
2031 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2032 OS << " return MCTargetAsmParser::Match_Success;\n";
2033 if (!CI.DiagnosticType.empty())
2034 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2035 << CI.DiagnosticType << ";\n";
2039 // Check for register operands, including sub-classes.
2040 OS << " if (Operand.isReg()) {\n";
2041 OS << " MatchClassKind OpKind;\n";
2042 OS << " switch (Operand.getReg()) {\n";
2043 OS << " default: OpKind = InvalidMatchClass; break;\n";
2044 for (const auto &RC : Info.RegisterClasses)
2045 OS << " case " << Info.Target.getName() << "::"
2046 << RC.first->getName() << ": OpKind = " << RC.second->Name
2049 OS << " return isSubclass(OpKind, Kind) ? "
2050 << "MCTargetAsmParser::Match_Success :\n "
2051 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2053 // Generic fallthrough match failure case for operands that don't have
2054 // specialized diagnostic types.
2055 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2059 /// emitIsSubclass - Emit the subclass predicate function.
2060 static void emitIsSubclass(CodeGenTarget &Target,
2061 std::forward_list<ClassInfo> &Infos,
2063 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2064 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2065 OS << " if (A == B)\n";
2066 OS << " return true;\n\n";
2069 raw_string_ostream SS(OStr);
2071 SS << " switch (A) {\n";
2072 SS << " default:\n";
2073 SS << " return false;\n";
2074 for (const auto &A : Infos) {
2075 std::vector<StringRef> SuperClasses;
2076 for (const auto &B : Infos) {
2077 if (&A != &B && A.isSubsetOf(B))
2078 SuperClasses.push_back(B.Name);
2081 if (SuperClasses.empty())
2085 SS << "\n case " << A.Name << ":\n";
2087 if (SuperClasses.size() == 1) {
2088 SS << " return B == " << SuperClasses.back().str() << ";\n";
2092 if (!SuperClasses.empty()) {
2093 SS << " switch (B) {\n";
2094 SS << " default: return false;\n";
2095 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
2096 SS << " case " << SuperClasses[i].str() << ": return true;\n";
2099 // No case statement to emit
2100 SS << " return false;\n";
2105 // If there were case statements emitted into the string stream, write them
2106 // to the output stream, otherwise write the default.
2110 OS << " return false;\n";
2115 /// emitMatchTokenString - Emit the function to match a token string to the
2116 /// appropriate match class value.
2117 static void emitMatchTokenString(CodeGenTarget &Target,
2118 std::forward_list<ClassInfo> &Infos,
2120 // Construct the match list.
2121 std::vector<StringMatcher::StringPair> Matches;
2122 for (const auto &CI : Infos) {
2123 if (CI.Kind == ClassInfo::Token)
2125 StringMatcher::StringPair(CI.ValueName, "return " + CI.Name + ";"));
2128 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2130 StringMatcher("Name", Matches, OS).Emit();
2132 OS << " return InvalidMatchClass;\n";
2136 /// emitMatchRegisterName - Emit the function to match a string to the target
2137 /// specific register enum.
2138 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2140 // Construct the match list.
2141 std::vector<StringMatcher::StringPair> Matches;
2142 const auto &Regs = Target.getRegBank().getRegisters();
2143 for (const CodeGenRegister &Reg : Regs) {
2144 if (Reg.TheDef->getValueAsString("AsmName").empty())
2148 StringMatcher::StringPair(Reg.TheDef->getValueAsString("AsmName"),
2149 "return " + utostr(Reg.EnumValue) + ";"));
2152 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2154 StringMatcher("Name", Matches, OS).Emit();
2156 OS << " return 0;\n";
2160 static const char *getMinimalTypeForRange(uint64_t Range) {
2161 assert(Range <= 0xFFFFFFFFFFFFFFFFULL && "Enum too large");
2162 if (Range > 0xFFFFFFFFULL)
2171 static const char *getMinimalRequiredFeaturesType(const AsmMatcherInfo &Info) {
2172 uint64_t MaxIndex = Info.SubtargetFeatures.size();
2175 return getMinimalTypeForRange(1ULL << MaxIndex);
2178 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2180 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2182 OS << "// Flags for subtarget features that participate in "
2183 << "instruction matching.\n";
2184 OS << "enum SubtargetFeatureFlag : " << getMinimalRequiredFeaturesType(Info)
2186 for (const auto &SF : Info.SubtargetFeatures) {
2187 const SubtargetFeatureInfo &SFI = SF.second;
2188 OS << " " << SFI.getEnumName() << " = (1ULL << " << SFI.Index << "),\n";
2190 OS << " Feature_None = 0\n";
2194 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2195 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2196 // Get the set of diagnostic types from all of the operand classes.
2197 std::set<StringRef> Types;
2198 for (std::map<Record*, ClassInfo*>::const_iterator
2199 I = Info.AsmOperandClasses.begin(),
2200 E = Info.AsmOperandClasses.end(); I != E; ++I) {
2201 if (!I->second->DiagnosticType.empty())
2202 Types.insert(I->second->DiagnosticType);
2205 if (Types.empty()) return;
2207 // Now emit the enum entries.
2208 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end();
2210 OS << " Match_" << *I << ",\n";
2211 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2214 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2215 /// user-level name for a subtarget feature.
2216 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2217 OS << "// User-level names for subtarget features that participate in\n"
2218 << "// instruction matching.\n"
2219 << "static const char *getSubtargetFeatureName(uint64_t Val) {\n";
2220 if (!Info.SubtargetFeatures.empty()) {
2221 OS << " switch(Val) {\n";
2222 for (const auto &SF : Info.SubtargetFeatures) {
2223 const SubtargetFeatureInfo &SFI = SF.second;
2224 // FIXME: Totally just a placeholder name to get the algorithm working.
2225 OS << " case " << SFI.getEnumName() << ": return \""
2226 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2228 OS << " default: return \"(unknown)\";\n";
2231 // Nothing to emit, so skip the switch
2232 OS << " return \"(unknown)\";\n";
2237 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2238 /// available features given a subtarget.
2239 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2241 std::string ClassName =
2242 Info.AsmParser->getValueAsString("AsmParserClassName");
2244 OS << "uint64_t " << Info.Target.getName() << ClassName << "::\n"
2245 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
2246 OS << " uint64_t Features = 0;\n";
2247 for (const auto &SF : Info.SubtargetFeatures) {
2248 const SubtargetFeatureInfo &SFI = SF.second;
2251 std::string CondStorage =
2252 SFI.TheDef->getValueAsString("AssemblerCondString");
2253 StringRef Conds = CondStorage;
2254 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2261 StringRef Cond = Comma.first;
2262 if (Cond[0] == '!') {
2264 Cond = Cond.substr(1);
2267 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
2274 if (Comma.second.empty())
2278 Comma = Comma.second.split(',');
2282 OS << " Features |= " << SFI.getEnumName() << ";\n";
2284 OS << " return Features;\n";
2288 static std::string GetAliasRequiredFeatures(Record *R,
2289 const AsmMatcherInfo &Info) {
2290 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2292 unsigned NumFeatures = 0;
2293 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2294 const SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2297 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2298 "' is not marked as an AssemblerPredicate!");
2303 Result += F->getEnumName();
2307 if (NumFeatures > 1)
2308 Result = '(' + Result + ')';
2312 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2313 std::vector<Record*> &Aliases,
2314 unsigned Indent = 0,
2315 StringRef AsmParserVariantName = StringRef()){
2316 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2317 // iteration order of the map is stable.
2318 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2320 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2321 Record *R = Aliases[i];
2322 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2323 std::string AsmVariantName = R->getValueAsString("AsmVariantName");
2324 if (AsmVariantName != AsmParserVariantName)
2326 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2328 if (AliasesFromMnemonic.empty())
2331 // Process each alias a "from" mnemonic at a time, building the code executed
2332 // by the string remapper.
2333 std::vector<StringMatcher::StringPair> Cases;
2334 for (std::map<std::string, std::vector<Record*> >::iterator
2335 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2337 const std::vector<Record*> &ToVec = I->second;
2339 // Loop through each alias and emit code that handles each case. If there
2340 // are two instructions without predicates, emit an error. If there is one,
2342 std::string MatchCode;
2343 int AliasWithNoPredicate = -1;
2345 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2346 Record *R = ToVec[i];
2347 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2349 // If this unconditionally matches, remember it for later and diagnose
2351 if (FeatureMask.empty()) {
2352 if (AliasWithNoPredicate != -1) {
2353 // We can't have two aliases from the same mnemonic with no predicate.
2354 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2355 "two MnemonicAliases with the same 'from' mnemonic!");
2356 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2359 AliasWithNoPredicate = i;
2362 if (R->getValueAsString("ToMnemonic") == I->first)
2363 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2365 if (!MatchCode.empty())
2366 MatchCode += "else ";
2367 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2368 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2371 if (AliasWithNoPredicate != -1) {
2372 Record *R = ToVec[AliasWithNoPredicate];
2373 if (!MatchCode.empty())
2374 MatchCode += "else\n ";
2375 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2378 MatchCode += "return;";
2380 Cases.push_back(std::make_pair(I->first, MatchCode));
2382 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2385 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2386 /// emit a function for them and return true, otherwise return false.
2387 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2388 CodeGenTarget &Target) {
2389 // Ignore aliases when match-prefix is set.
2390 if (!MatchPrefix.empty())
2393 std::vector<Record*> Aliases =
2394 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2395 if (Aliases.empty()) return false;
2397 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2398 "uint64_t Features, unsigned VariantID) {\n";
2399 OS << " switch (VariantID) {\n";
2400 unsigned VariantCount = Target.getAsmParserVariantCount();
2401 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2402 Record *AsmVariant = Target.getAsmParserVariant(VC);
2403 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2404 std::string AsmParserVariantName = AsmVariant->getValueAsString("Name");
2405 OS << " case " << AsmParserVariantNo << ":\n";
2406 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2407 AsmParserVariantName);
2412 // Emit aliases that apply to all variants.
2413 emitMnemonicAliasVariant(OS, Info, Aliases);
2420 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2421 const AsmMatcherInfo &Info, StringRef ClassName,
2422 StringToOffsetTable &StringTable,
2423 unsigned MaxMnemonicIndex) {
2424 unsigned MaxMask = 0;
2425 for (std::vector<OperandMatchEntry>::const_iterator it =
2426 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2428 MaxMask |= it->OperandMask;
2431 // Emit the static custom operand parsing table;
2432 OS << "namespace {\n";
2433 OS << " struct OperandMatchEntry {\n";
2434 OS << " " << getMinimalRequiredFeaturesType(Info)
2435 << " RequiredFeatures;\n";
2436 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2438 OS << " " << getMinimalTypeForRange(std::distance(
2439 Info.Classes.begin(), Info.Classes.end())) << " Class;\n";
2440 OS << " " << getMinimalTypeForRange(MaxMask)
2441 << " OperandMask;\n\n";
2442 OS << " StringRef getMnemonic() const {\n";
2443 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2444 OS << " MnemonicTable[Mnemonic]);\n";
2448 OS << " // Predicate for searching for an opcode.\n";
2449 OS << " struct LessOpcodeOperand {\n";
2450 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2451 OS << " return LHS.getMnemonic() < RHS;\n";
2453 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2454 OS << " return LHS < RHS.getMnemonic();\n";
2456 OS << " bool operator()(const OperandMatchEntry &LHS,";
2457 OS << " const OperandMatchEntry &RHS) {\n";
2458 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2462 OS << "} // end anonymous namespace.\n\n";
2464 OS << "static const OperandMatchEntry OperandMatchTable["
2465 << Info.OperandMatchInfo.size() << "] = {\n";
2467 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2468 for (std::vector<OperandMatchEntry>::const_iterator it =
2469 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2471 const OperandMatchEntry &OMI = *it;
2472 const MatchableInfo &II = *OMI.MI;
2476 // Write the required features mask.
2477 if (!II.RequiredFeatures.empty()) {
2478 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2480 OS << II.RequiredFeatures[i]->getEnumName();
2485 // Store a pascal-style length byte in the mnemonic.
2486 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2487 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2488 << " /* " << II.Mnemonic << " */, ";
2492 OS << ", " << OMI.OperandMask;
2494 bool printComma = false;
2495 for (int i = 0, e = 31; i !=e; ++i)
2496 if (OMI.OperandMask & (1 << i)) {
2508 // Emit the operand class switch to call the correct custom parser for
2509 // the found operand class.
2510 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2511 << Target.getName() << ClassName << "::\n"
2512 << "tryCustomParseOperand(OperandVector"
2513 << " &Operands,\n unsigned MCK) {\n\n"
2514 << " switch(MCK) {\n";
2516 for (const auto &CI : Info.Classes) {
2517 if (CI.ParserMethod.empty())
2519 OS << " case " << CI.Name << ":\n"
2520 << " return " << CI.ParserMethod << "(Operands);\n";
2523 OS << " default:\n";
2524 OS << " return MatchOperand_NoMatch;\n";
2526 OS << " return MatchOperand_NoMatch;\n";
2529 // Emit the static custom operand parser. This code is very similar with
2530 // the other matcher. Also use MatchResultTy here just in case we go for
2531 // a better error handling.
2532 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2533 << Target.getName() << ClassName << "::\n"
2534 << "MatchOperandParserImpl(OperandVector"
2535 << " &Operands,\n StringRef Mnemonic) {\n";
2537 // Emit code to get the available features.
2538 OS << " // Get the current feature set.\n";
2539 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2541 OS << " // Get the next operand index.\n";
2542 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2544 // Emit code to search the table.
2545 OS << " // Search the table.\n";
2546 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2547 OS << " MnemonicRange =\n";
2548 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2549 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2550 << " LessOpcodeOperand());\n\n";
2552 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2553 OS << " return MatchOperand_NoMatch;\n\n";
2555 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2556 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2558 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2559 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2561 // Emit check that the required features are available.
2562 OS << " // check if the available features match\n";
2563 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2564 << "!= it->RequiredFeatures) {\n";
2565 OS << " continue;\n";
2568 // Emit check to ensure the operand number matches.
2569 OS << " // check if the operand in question has a custom parser.\n";
2570 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2571 OS << " continue;\n\n";
2573 // Emit call to the custom parser method
2574 OS << " // call custom parse method to handle the operand\n";
2575 OS << " OperandMatchResultTy Result = ";
2576 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2577 OS << " if (Result != MatchOperand_NoMatch)\n";
2578 OS << " return Result;\n";
2581 OS << " // Okay, we had no match.\n";
2582 OS << " return MatchOperand_NoMatch;\n";
2586 void AsmMatcherEmitter::run(raw_ostream &OS) {
2587 CodeGenTarget Target(Records);
2588 Record *AsmParser = Target.getAsmParser();
2589 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2591 // Compute the information on the instructions to match.
2592 AsmMatcherInfo Info(AsmParser, Target, Records);
2595 // Sort the instruction table using the partial order on classes. We use
2596 // stable_sort to ensure that ambiguous instructions are still
2597 // deterministically ordered.
2598 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2599 [](const std::unique_ptr<MatchableInfo> &a,
2600 const std::unique_ptr<MatchableInfo> &b){
2603 DEBUG_WITH_TYPE("instruction_info", {
2604 for (const auto &MI : Info.Matchables)
2608 // Check for ambiguous matchables.
2609 DEBUG_WITH_TYPE("ambiguous_instrs", {
2610 unsigned NumAmbiguous = 0;
2611 for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
2613 for (auto J = std::next(I); J != E; ++J) {
2614 const MatchableInfo &A = **I;
2615 const MatchableInfo &B = **J;
2617 if (A.couldMatchAmbiguouslyWith(B)) {
2618 errs() << "warning: ambiguous matchables:\n";
2620 errs() << "\nis incomparable with:\n";
2628 errs() << "warning: " << NumAmbiguous
2629 << " ambiguous matchables!\n";
2632 // Compute the information on the custom operand parsing.
2633 Info.buildOperandMatchInfo();
2635 // Write the output.
2637 // Information for the class declaration.
2638 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2639 OS << "#undef GET_ASSEMBLER_HEADER\n";
2640 OS << " // This should be included into the middle of the declaration of\n";
2641 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2642 OS << " uint64_t ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
2643 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2644 << "unsigned Opcode,\n"
2645 << " const OperandVector "
2647 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2648 OS << " const OperandVector &Operands) override;\n";
2649 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) override;\n";
2650 OS << " unsigned MatchInstructionImpl(const OperandVector &Operands,\n"
2651 << " MCInst &Inst,\n"
2652 << " uint64_t &ErrorInfo,"
2653 << " bool matchingInlineAsm,\n"
2654 << " unsigned VariantID = 0);\n";
2656 if (!Info.OperandMatchInfo.empty()) {
2657 OS << "\n enum OperandMatchResultTy {\n";
2658 OS << " MatchOperand_Success, // operand matched successfully\n";
2659 OS << " MatchOperand_NoMatch, // operand did not match\n";
2660 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2662 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2663 OS << " OperandVector &Operands,\n";
2664 OS << " StringRef Mnemonic);\n";
2666 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2667 OS << " OperandVector &Operands,\n";
2668 OS << " unsigned MCK);\n\n";
2671 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2673 // Emit the operand match diagnostic enum names.
2674 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2675 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2676 emitOperandDiagnosticTypes(Info, OS);
2677 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2680 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2681 OS << "#undef GET_REGISTER_MATCHER\n\n";
2683 // Emit the subtarget feature enumeration.
2684 emitSubtargetFeatureFlagEnumeration(Info, OS);
2686 // Emit the function to match a register name to number.
2687 // This should be omitted for Mips target
2688 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2689 emitMatchRegisterName(Target, AsmParser, OS);
2691 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2693 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2694 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2696 // Generate the helper function to get the names for subtarget features.
2697 emitGetSubtargetFeatureName(Info, OS);
2699 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2701 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2702 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2704 // Generate the function that remaps for mnemonic aliases.
2705 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
2707 // Generate the convertToMCInst function to convert operands into an MCInst.
2708 // Also, generate the convertToMapAndConstraints function for MS-style inline
2709 // assembly. The latter doesn't actually generate a MCInst.
2710 emitConvertFuncs(Target, ClassName, Info.Matchables, OS);
2712 // Emit the enumeration for classes which participate in matching.
2713 emitMatchClassEnumeration(Target, Info.Classes, OS);
2715 // Emit the routine to match token strings to their match class.
2716 emitMatchTokenString(Target, Info.Classes, OS);
2718 // Emit the subclass predicate routine.
2719 emitIsSubclass(Target, Info.Classes, OS);
2721 // Emit the routine to validate an operand against a match class.
2722 emitValidateOperandClass(Info, OS);
2724 // Emit the available features compute function.
2725 emitComputeAvailableFeatures(Info, OS);
2728 StringToOffsetTable StringTable;
2730 size_t MaxNumOperands = 0;
2731 unsigned MaxMnemonicIndex = 0;
2732 bool HasDeprecation = false;
2733 for (const auto &MI : Info.Matchables) {
2734 MaxNumOperands = std::max(MaxNumOperands, MI->AsmOperands.size());
2735 HasDeprecation |= MI->HasDeprecation;
2737 // Store a pascal-style length byte in the mnemonic.
2738 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2739 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2740 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2743 OS << "static const char *const MnemonicTable =\n";
2744 StringTable.EmitString(OS);
2747 // Emit the static match table; unused classes get initalized to 0 which is
2748 // guaranteed to be InvalidMatchClass.
2750 // FIXME: We can reduce the size of this table very easily. First, we change
2751 // it so that store the kinds in separate bit-fields for each index, which
2752 // only needs to be the max width used for classes at that index (we also need
2753 // to reject based on this during classification). If we then make sure to
2754 // order the match kinds appropriately (putting mnemonics last), then we
2755 // should only end up using a few bits for each class, especially the ones
2756 // following the mnemonic.
2757 OS << "namespace {\n";
2758 OS << " struct MatchEntry {\n";
2759 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2761 OS << " uint16_t Opcode;\n";
2762 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2764 OS << " " << getMinimalRequiredFeaturesType(Info)
2765 << " RequiredFeatures;\n";
2766 OS << " " << getMinimalTypeForRange(
2767 std::distance(Info.Classes.begin(), Info.Classes.end()))
2768 << " Classes[" << MaxNumOperands << "];\n";
2769 OS << " StringRef getMnemonic() const {\n";
2770 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2771 OS << " MnemonicTable[Mnemonic]);\n";
2775 OS << " // Predicate for searching for an opcode.\n";
2776 OS << " struct LessOpcode {\n";
2777 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2778 OS << " return LHS.getMnemonic() < RHS;\n";
2780 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2781 OS << " return LHS < RHS.getMnemonic();\n";
2783 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2784 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2788 OS << "} // end anonymous namespace.\n\n";
2790 unsigned VariantCount = Target.getAsmParserVariantCount();
2791 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2792 Record *AsmVariant = Target.getAsmParserVariant(VC);
2793 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2795 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
2797 for (const auto &MI : Info.Matchables) {
2798 if (MI->AsmVariantID != AsmVariantNo)
2801 // Store a pascal-style length byte in the mnemonic.
2802 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2803 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2804 << " /* " << MI->Mnemonic << " */, "
2805 << Target.getName() << "::"
2806 << MI->getResultInst()->TheDef->getName() << ", "
2807 << MI->ConversionFnKind << ", ";
2809 // Write the required features mask.
2810 if (!MI->RequiredFeatures.empty()) {
2811 for (unsigned i = 0, e = MI->RequiredFeatures.size(); i != e; ++i) {
2813 OS << MI->RequiredFeatures[i]->getEnumName();
2819 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
2820 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
2823 OS << Op.Class->Name;
2831 // A method to determine if a mnemonic is in the list.
2832 OS << "bool " << Target.getName() << ClassName << "::\n"
2833 << "mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {\n";
2834 OS << " // Find the appropriate table for this asm variant.\n";
2835 OS << " const MatchEntry *Start, *End;\n";
2836 OS << " switch (VariantID) {\n";
2837 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
2838 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2839 Record *AsmVariant = Target.getAsmParserVariant(VC);
2840 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2841 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2842 << "); End = std::end(MatchTable" << VC << "); break;\n";
2845 OS << " // Search the table.\n";
2846 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2847 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n";
2848 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2851 // Finally, build the match function.
2852 OS << "unsigned " << Target.getName() << ClassName << "::\n"
2853 << "MatchInstructionImpl(const OperandVector &Operands,\n";
2854 OS << " MCInst &Inst, uint64_t &ErrorInfo,\n"
2855 << " bool matchingInlineAsm, unsigned VariantID) {\n";
2857 OS << " // Eliminate obvious mismatches.\n";
2858 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2859 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2860 OS << " return Match_InvalidOperand;\n";
2863 // Emit code to get the available features.
2864 OS << " // Get the current feature set.\n";
2865 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2867 OS << " // Get the instruction mnemonic, which is the first token.\n";
2868 OS << " StringRef Mnemonic = ((" << Target.getName()
2869 << "Operand&)*Operands[0]).getToken();\n\n";
2871 if (HasMnemonicAliases) {
2872 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2873 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
2876 // Emit code to compute the class list for this operand vector.
2877 OS << " // Some state to try to produce better error messages.\n";
2878 OS << " bool HadMatchOtherThanFeatures = false;\n";
2879 OS << " bool HadMatchOtherThanPredicate = false;\n";
2880 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2881 OS << " uint64_t MissingFeatures = ~0ULL;\n";
2882 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2883 OS << " // wrong for all instances of the instruction.\n";
2884 OS << " ErrorInfo = ~0U;\n";
2886 // Emit code to search the table.
2887 OS << " // Find the appropriate table for this asm variant.\n";
2888 OS << " const MatchEntry *Start, *End;\n";
2889 OS << " switch (VariantID) {\n";
2890 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
2891 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2892 Record *AsmVariant = Target.getAsmParserVariant(VC);
2893 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2894 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2895 << "); End = std::end(MatchTable" << VC << "); break;\n";
2898 OS << " // Search the table.\n";
2899 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2900 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
2902 OS << " // Return a more specific error code if no mnemonics match.\n";
2903 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2904 OS << " return Match_MnemonicFail;\n\n";
2906 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2907 << "*ie = MnemonicRange.second;\n";
2908 OS << " it != ie; ++it) {\n";
2910 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2911 OS << " assert(Mnemonic == it->getMnemonic());\n";
2913 // Emit check that the subclasses match.
2914 OS << " bool OperandsValid = true;\n";
2915 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2916 OS << " if (i + 1 >= Operands.size()) {\n";
2917 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2918 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n";
2921 OS << " unsigned Diag = validateOperandClass(*Operands[i+1],\n";
2923 OS << "(MatchClassKind)it->Classes[i]);\n";
2924 OS << " if (Diag == Match_Success)\n";
2925 OS << " continue;\n";
2926 OS << " // If the generic handler indicates an invalid operand\n";
2927 OS << " // failure, check for a special case.\n";
2928 OS << " if (Diag == Match_InvalidOperand) {\n";
2929 OS << " Diag = validateTargetOperandClass(*Operands[i+1],\n";
2931 OS << "(MatchClassKind)it->Classes[i]);\n";
2932 OS << " if (Diag == Match_Success)\n";
2933 OS << " continue;\n";
2935 OS << " // If this operand is broken for all of the instances of this\n";
2936 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2937 OS << " // If we already had a match that only failed due to a\n";
2938 OS << " // target predicate, that diagnostic is preferred.\n";
2939 OS << " if (!HadMatchOtherThanPredicate &&\n";
2940 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n";
2941 OS << " ErrorInfo = i+1;\n";
2942 OS << " // InvalidOperand is the default. Prefer specificity.\n";
2943 OS << " if (Diag != Match_InvalidOperand)\n";
2944 OS << " RetCode = Diag;\n";
2946 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2947 OS << " OperandsValid = false;\n";
2951 OS << " if (!OperandsValid) continue;\n";
2953 // Emit check that the required features are available.
2954 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2955 << "!= it->RequiredFeatures) {\n";
2956 OS << " HadMatchOtherThanFeatures = true;\n";
2957 OS << " uint64_t NewMissingFeatures = it->RequiredFeatures & "
2958 "~AvailableFeatures;\n";
2959 OS << " if (CountPopulation_64(NewMissingFeatures) <=\n"
2960 " CountPopulation_64(MissingFeatures))\n";
2961 OS << " MissingFeatures = NewMissingFeatures;\n";
2962 OS << " continue;\n";
2965 OS << " Inst.clear();\n\n";
2966 OS << " if (matchingInlineAsm) {\n";
2967 OS << " Inst.setOpcode(it->Opcode);\n";
2968 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
2969 OS << " return Match_Success;\n";
2971 OS << " // We have selected a definite instruction, convert the parsed\n"
2972 << " // operands into the appropriate MCInst.\n";
2973 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
2976 // Verify the instruction with the target-specific match predicate function.
2977 OS << " // We have a potential match. Check the target predicate to\n"
2978 << " // handle any context sensitive constraints.\n"
2979 << " unsigned MatchResult;\n"
2980 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
2981 << " Match_Success) {\n"
2982 << " Inst.clear();\n"
2983 << " RetCode = MatchResult;\n"
2984 << " HadMatchOtherThanPredicate = true;\n"
2988 // Call the post-processing function, if used.
2989 std::string InsnCleanupFn =
2990 AsmParser->getValueAsString("AsmParserInstCleanup");
2991 if (!InsnCleanupFn.empty())
2992 OS << " " << InsnCleanupFn << "(Inst);\n";
2994 if (HasDeprecation) {
2995 OS << " std::string Info;\n";
2996 OS << " if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, STI, Info)) {\n";
2997 OS << " SMLoc Loc = ((" << Target.getName()
2998 << "Operand&)*Operands[0]).getStartLoc();\n";
2999 OS << " getParser().Warning(Loc, Info, None);\n";
3003 OS << " return Match_Success;\n";
3006 OS << " // Okay, we had no match. Try to return a useful error code.\n";
3007 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
3008 OS << " return RetCode;\n\n";
3009 OS << " // Missing feature matches return which features were missing\n";
3010 OS << " ErrorInfo = MissingFeatures;\n";
3011 OS << " return Match_MissingFeature;\n";
3014 if (!Info.OperandMatchInfo.empty())
3015 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
3018 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
3023 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
3024 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
3025 AsmMatcherEmitter(RK).run(OS);
3028 } // End llvm namespace