1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "StringToOffsetTable.h"
101 #include "llvm/ADT/OwningPtr.h"
102 #include "llvm/ADT/PointerUnion.h"
103 #include "llvm/ADT/SmallPtrSet.h"
104 #include "llvm/ADT/SmallVector.h"
105 #include "llvm/ADT/STLExtras.h"
106 #include "llvm/ADT/StringExtras.h"
107 #include "llvm/Support/CommandLine.h"
108 #include "llvm/Support/Debug.h"
109 #include "llvm/Support/ErrorHandling.h"
110 #include "llvm/TableGen/Error.h"
111 #include "llvm/TableGen/Record.h"
112 #include "llvm/TableGen/StringMatcher.h"
113 #include "llvm/TableGen/TableGenBackend.h"
117 using namespace llvm;
119 static cl::opt<std::string>
120 MatchPrefix("match-prefix", cl::init(""),
121 cl::desc("Only match instructions with the given prefix"));
124 class AsmMatcherInfo;
125 struct SubtargetFeatureInfo;
127 class AsmMatcherEmitter {
128 RecordKeeper &Records;
130 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
132 void run(raw_ostream &o);
135 /// ClassInfo - Helper class for storing the information about a particular
136 /// class of operands which can be matched.
139 /// Invalid kind, for use as a sentinel value.
142 /// The class for a particular token.
145 /// The (first) register class, subsequent register classes are
146 /// RegisterClass0+1, and so on.
149 /// The (first) user defined class, subsequent user defined classes are
150 /// UserClass0+1, and so on.
154 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
155 /// N) for the Nth user defined class.
158 /// SuperClasses - The super classes of this class. Note that for simplicities
159 /// sake user operands only record their immediate super class, while register
160 /// operands include all superclasses.
161 std::vector<ClassInfo*> SuperClasses;
163 /// Name - The full class name, suitable for use in an enum.
166 /// ClassName - The unadorned generic name for this class (e.g., Token).
167 std::string ClassName;
169 /// ValueName - The name of the value this class represents; for a token this
170 /// is the literal token string, for an operand it is the TableGen class (or
171 /// empty if this is a derived class).
172 std::string ValueName;
174 /// PredicateMethod - The name of the operand method to test whether the
175 /// operand matches this class; this is not valid for Token or register kinds.
176 std::string PredicateMethod;
178 /// RenderMethod - The name of the operand method to add this operand to an
179 /// MCInst; this is not valid for Token or register kinds.
180 std::string RenderMethod;
182 /// ParserMethod - The name of the operand method to do a target specific
183 /// parsing on the operand.
184 std::string ParserMethod;
186 /// For register classes, the records for all the registers in this class.
187 std::set<Record*> Registers;
189 /// For custom match classes, he diagnostic kind for when the predicate fails.
190 std::string DiagnosticType;
192 /// isRegisterClass() - Check if this is a register class.
193 bool isRegisterClass() const {
194 return Kind >= RegisterClass0 && Kind < UserClass0;
197 /// isUserClass() - Check if this is a user defined class.
198 bool isUserClass() const {
199 return Kind >= UserClass0;
202 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
203 /// are related if they are in the same class hierarchy.
204 bool isRelatedTo(const ClassInfo &RHS) const {
205 // Tokens are only related to tokens.
206 if (Kind == Token || RHS.Kind == Token)
207 return Kind == Token && RHS.Kind == Token;
209 // Registers classes are only related to registers classes, and only if
210 // their intersection is non-empty.
211 if (isRegisterClass() || RHS.isRegisterClass()) {
212 if (!isRegisterClass() || !RHS.isRegisterClass())
215 std::set<Record*> Tmp;
216 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
217 std::set_intersection(Registers.begin(), Registers.end(),
218 RHS.Registers.begin(), RHS.Registers.end(),
224 // Otherwise we have two users operands; they are related if they are in the
225 // same class hierarchy.
227 // FIXME: This is an oversimplification, they should only be related if they
228 // intersect, however we don't have that information.
229 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
230 const ClassInfo *Root = this;
231 while (!Root->SuperClasses.empty())
232 Root = Root->SuperClasses.front();
234 const ClassInfo *RHSRoot = &RHS;
235 while (!RHSRoot->SuperClasses.empty())
236 RHSRoot = RHSRoot->SuperClasses.front();
238 return Root == RHSRoot;
241 /// isSubsetOf - Test whether this class is a subset of \p RHS.
242 bool isSubsetOf(const ClassInfo &RHS) const {
243 // This is a subset of RHS if it is the same class...
247 // ... or if any of its super classes are a subset of RHS.
248 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
249 ie = SuperClasses.end(); it != ie; ++it)
250 if ((*it)->isSubsetOf(RHS))
256 /// operator< - Compare two classes.
257 bool operator<(const ClassInfo &RHS) const {
261 // Unrelated classes can be ordered by kind.
262 if (!isRelatedTo(RHS))
263 return Kind < RHS.Kind;
267 llvm_unreachable("Invalid kind!");
270 // This class precedes the RHS if it is a proper subset of the RHS.
273 if (RHS.isSubsetOf(*this))
276 // Otherwise, order by name to ensure we have a total ordering.
277 return ValueName < RHS.ValueName;
283 /// Sort ClassInfo pointers independently of pointer value.
284 struct LessClassInfoPtr {
285 bool operator()(const ClassInfo *LHS, const ClassInfo *RHS) const {
291 /// MatchableInfo - Helper class for storing the necessary information for an
292 /// instruction or alias which is capable of being matched.
293 struct MatchableInfo {
295 /// Token - This is the token that the operand came from.
298 /// The unique class instance this operand should match.
301 /// The operand name this is, if anything.
304 /// The suboperand index within SrcOpName, or -1 for the entire operand.
307 /// Register record if this token is singleton register.
308 Record *SingletonReg;
310 explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1),
314 /// ResOperand - This represents a single operand in the result instruction
315 /// generated by the match. In cases (like addressing modes) where a single
316 /// assembler operand expands to multiple MCOperands, this represents the
317 /// single assembler operand, not the MCOperand.
320 /// RenderAsmOperand - This represents an operand result that is
321 /// generated by calling the render method on the assembly operand. The
322 /// corresponding AsmOperand is specified by AsmOperandNum.
325 /// TiedOperand - This represents a result operand that is a duplicate of
326 /// a previous result operand.
329 /// ImmOperand - This represents an immediate value that is dumped into
333 /// RegOperand - This represents a fixed register that is dumped in.
338 /// This is the operand # in the AsmOperands list that this should be
340 unsigned AsmOperandNum;
342 /// TiedOperandNum - This is the (earlier) result operand that should be
344 unsigned TiedOperandNum;
346 /// ImmVal - This is the immediate value added to the instruction.
349 /// Register - This is the register record.
353 /// MINumOperands - The number of MCInst operands populated by this
355 unsigned MINumOperands;
357 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
359 X.Kind = RenderAsmOperand;
360 X.AsmOperandNum = AsmOpNum;
361 X.MINumOperands = NumOperands;
365 static ResOperand getTiedOp(unsigned TiedOperandNum) {
367 X.Kind = TiedOperand;
368 X.TiedOperandNum = TiedOperandNum;
373 static ResOperand getImmOp(int64_t Val) {
381 static ResOperand getRegOp(Record *Reg) {
390 /// AsmVariantID - Target's assembly syntax variant no.
393 /// TheDef - This is the definition of the instruction or InstAlias that this
394 /// matchable came from.
395 Record *const TheDef;
397 /// DefRec - This is the definition that it came from.
398 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
400 const CodeGenInstruction *getResultInst() const {
401 if (DefRec.is<const CodeGenInstruction*>())
402 return DefRec.get<const CodeGenInstruction*>();
403 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
406 /// ResOperands - This is the operand list that should be built for the result
408 SmallVector<ResOperand, 8> ResOperands;
410 /// AsmString - The assembly string for this instruction (with variants
411 /// removed), e.g. "movsx $src, $dst".
412 std::string AsmString;
414 /// Mnemonic - This is the first token of the matched instruction, its
418 /// AsmOperands - The textual operands that this instruction matches,
419 /// annotated with a class and where in the OperandList they were defined.
420 /// This directly corresponds to the tokenized AsmString after the mnemonic is
422 SmallVector<AsmOperand, 8> AsmOperands;
424 /// Predicates - The required subtarget features to match this instruction.
425 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
427 /// ConversionFnKind - The enum value which is passed to the generated
428 /// convertToMCInst to convert parsed operands into an MCInst for this
430 std::string ConversionFnKind;
432 MatchableInfo(const CodeGenInstruction &CGI)
433 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI),
434 AsmString(CGI.AsmString) {
437 MatchableInfo(const CodeGenInstAlias *Alias)
438 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias),
439 AsmString(Alias->AsmString) {
442 // Two-operand aliases clone from the main matchable, but mark the second
443 // operand as a tied operand of the first for purposes of the assembler.
444 void formTwoOperandAlias(StringRef Constraint);
446 void initialize(const AsmMatcherInfo &Info,
447 SmallPtrSet<Record*, 16> &SingletonRegisters,
448 int AsmVariantNo, std::string &RegisterPrefix);
450 /// validate - Return true if this matchable is a valid thing to match against
451 /// and perform a bunch of validity checking.
452 bool validate(StringRef CommentDelimiter, bool Hack) const;
454 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
455 /// if present, from specified token.
457 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info,
458 std::string &RegisterPrefix);
460 /// findAsmOperand - Find the AsmOperand with the specified name and
461 /// suboperand index.
462 int findAsmOperand(StringRef N, int SubOpIdx) const {
463 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
464 if (N == AsmOperands[i].SrcOpName &&
465 SubOpIdx == AsmOperands[i].SubOpIdx)
470 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
471 /// This does not check the suboperand index.
472 int findAsmOperandNamed(StringRef N) const {
473 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
474 if (N == AsmOperands[i].SrcOpName)
479 void buildInstructionResultOperands();
480 void buildAliasResultOperands();
482 /// operator< - Compare two matchables.
483 bool operator<(const MatchableInfo &RHS) const {
484 // The primary comparator is the instruction mnemonic.
485 if (Mnemonic != RHS.Mnemonic)
486 return Mnemonic < RHS.Mnemonic;
488 if (AsmOperands.size() != RHS.AsmOperands.size())
489 return AsmOperands.size() < RHS.AsmOperands.size();
491 // Compare lexicographically by operand. The matcher validates that other
492 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
493 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
494 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
496 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
500 // Give matches that require more features higher precedence. This is useful
501 // because we cannot define AssemblerPredicates with the negation of
502 // processor features. For example, ARM v6 "nop" may be either a HINT or
503 // MOV. With v6, we want to match HINT. The assembler has no way to
504 // predicate MOV under "NoV6", but HINT will always match first because it
505 // requires V6 while MOV does not.
506 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
507 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
512 /// couldMatchAmbiguouslyWith - Check whether this matchable could
513 /// ambiguously match the same set of operands as \p RHS (without being a
514 /// strictly superior match).
515 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) {
516 // The primary comparator is the instruction mnemonic.
517 if (Mnemonic != RHS.Mnemonic)
520 // The number of operands is unambiguous.
521 if (AsmOperands.size() != RHS.AsmOperands.size())
524 // Otherwise, make sure the ordering of the two instructions is unambiguous
525 // by checking that either (a) a token or operand kind discriminates them,
526 // or (b) the ordering among equivalent kinds is consistent.
528 // Tokens and operand kinds are unambiguous (assuming a correct target
530 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
531 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
532 AsmOperands[i].Class->Kind == ClassInfo::Token)
533 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
534 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
537 // Otherwise, this operand could commute if all operands are equivalent, or
538 // there is a pair of operands that compare less than and a pair that
539 // compare greater than.
540 bool HasLT = false, HasGT = false;
541 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
542 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
544 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
548 return !(HasLT ^ HasGT);
554 void tokenizeAsmString(const AsmMatcherInfo &Info);
557 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
558 /// feature which participates in instruction matching.
559 struct SubtargetFeatureInfo {
560 /// \brief The predicate record for this feature.
563 /// \brief An unique index assigned to represent this feature.
566 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
568 /// \brief The name of the enumerated constant identifying this feature.
569 std::string getEnumName() const {
570 return "Feature_" + TheDef->getName();
574 struct OperandMatchEntry {
575 unsigned OperandMask;
579 static OperandMatchEntry create(MatchableInfo* mi, ClassInfo *ci,
582 X.OperandMask = opMask;
590 class AsmMatcherInfo {
593 RecordKeeper &Records;
595 /// The tablegen AsmParser record.
598 /// Target - The target information.
599 CodeGenTarget &Target;
601 /// The classes which are needed for matching.
602 std::vector<ClassInfo*> Classes;
604 /// The information on the matchables to match.
605 std::vector<MatchableInfo*> Matchables;
607 /// Info for custom matching operands by user defined methods.
608 std::vector<OperandMatchEntry> OperandMatchInfo;
610 /// Map of Register records to their class information.
611 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
612 RegisterClassesTy RegisterClasses;
614 /// Map of Predicate records to their subtarget information.
615 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
617 /// Map of AsmOperandClass records to their class information.
618 std::map<Record*, ClassInfo*> AsmOperandClasses;
621 /// Map of token to class information which has already been constructed.
622 std::map<std::string, ClassInfo*> TokenClasses;
624 /// Map of RegisterClass records to their class information.
625 std::map<Record*, ClassInfo*> RegisterClassClasses;
628 /// getTokenClass - Lookup or create the class for the given token.
629 ClassInfo *getTokenClass(StringRef Token);
631 /// getOperandClass - Lookup or create the class for the given operand.
632 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
634 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
636 /// buildRegisterClasses - Build the ClassInfo* instances for register
638 void buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
640 /// buildOperandClasses - Build the ClassInfo* instances for user defined
642 void buildOperandClasses();
644 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
646 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
647 MatchableInfo::AsmOperand &Op);
650 AsmMatcherInfo(Record *AsmParser,
651 CodeGenTarget &Target,
652 RecordKeeper &Records);
654 /// buildInfo - Construct the various tables used during matching.
657 /// buildOperandMatchInfo - Build the necessary information to handle user
658 /// defined operand parsing methods.
659 void buildOperandMatchInfo();
661 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
663 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
664 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
665 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
666 SubtargetFeatures.find(Def);
667 return I == SubtargetFeatures.end() ? 0 : I->second;
670 RecordKeeper &getRecords() const {
675 } // End anonymous namespace
677 void MatchableInfo::dump() {
678 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
680 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
681 AsmOperand &Op = AsmOperands[i];
682 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
683 errs() << '\"' << Op.Token << "\"\n";
687 static std::pair<StringRef, StringRef>
688 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
689 // Split via the '='.
690 std::pair<StringRef, StringRef> Ops = S.split('=');
691 if (Ops.second == "")
692 throw TGError(Loc, "missing '=' in two-operand alias constraint");
693 // Trim whitespace and the leading '$' on the operand names.
694 size_t start = Ops.first.find_first_of('$');
695 if (start == std::string::npos)
696 throw TGError(Loc, "expected '$' prefix on asm operand name");
697 Ops.first = Ops.first.slice(start + 1, std::string::npos);
698 size_t end = Ops.first.find_last_of(" \t");
699 Ops.first = Ops.first.slice(0, end);
700 // Now the second operand.
701 start = Ops.second.find_first_of('$');
702 if (start == std::string::npos)
703 throw TGError(Loc, "expected '$' prefix on asm operand name");
704 Ops.second = Ops.second.slice(start + 1, std::string::npos);
705 end = Ops.second.find_last_of(" \t");
706 Ops.first = Ops.first.slice(0, end);
710 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
711 // Figure out which operands are aliased and mark them as tied.
712 std::pair<StringRef, StringRef> Ops =
713 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
715 // Find the AsmOperands that refer to the operands we're aliasing.
716 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
717 int DstAsmOperand = findAsmOperandNamed(Ops.second);
718 if (SrcAsmOperand == -1)
719 throw TGError(TheDef->getLoc(),
720 "unknown source two-operand alias operand '" +
721 Ops.first.str() + "'.");
722 if (DstAsmOperand == -1)
723 throw TGError(TheDef->getLoc(),
724 "unknown destination two-operand alias operand '" +
725 Ops.second.str() + "'.");
727 // Find the ResOperand that refers to the operand we're aliasing away
728 // and update it to refer to the combined operand instead.
729 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
730 ResOperand &Op = ResOperands[i];
731 if (Op.Kind == ResOperand::RenderAsmOperand &&
732 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
733 Op.AsmOperandNum = DstAsmOperand;
737 // Remove the AsmOperand for the alias operand.
738 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
739 // Adjust the ResOperand references to any AsmOperands that followed
740 // the one we just deleted.
741 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
742 ResOperand &Op = ResOperands[i];
745 // Nothing to do for operands that don't reference AsmOperands.
747 case ResOperand::RenderAsmOperand:
748 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
751 case ResOperand::TiedOperand:
752 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
759 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
760 SmallPtrSet<Record*, 16> &SingletonRegisters,
761 int AsmVariantNo, std::string &RegisterPrefix) {
762 AsmVariantID = AsmVariantNo;
764 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
766 tokenizeAsmString(Info);
768 // Compute the require features.
769 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
770 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
771 if (SubtargetFeatureInfo *Feature =
772 Info.getSubtargetFeature(Predicates[i]))
773 RequiredFeatures.push_back(Feature);
775 // Collect singleton registers, if used.
776 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
777 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix);
778 if (Record *Reg = AsmOperands[i].SingletonReg)
779 SingletonRegisters.insert(Reg);
783 /// tokenizeAsmString - Tokenize a simplified assembly string.
784 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
785 StringRef String = AsmString;
788 for (unsigned i = 0, e = String.size(); i != e; ++i) {
798 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
801 if (!isspace(String[i]) && String[i] != ',')
802 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
808 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
812 assert(i != String.size() && "Invalid quoted character");
813 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
819 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
823 // If this isn't "${", treat like a normal token.
824 if (i + 1 == String.size() || String[i + 1] != '{') {
829 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
830 assert(End != String.end() && "Missing brace in operand reference!");
831 size_t EndPos = End - String.begin();
832 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
840 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
849 if (InTok && Prev != String.size())
850 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
852 // The first token of the instruction is the mnemonic, which must be a
853 // simple string, not a $foo variable or a singleton register.
854 if (AsmOperands.empty())
855 throw TGError(TheDef->getLoc(),
856 "Instruction '" + TheDef->getName() + "' has no tokens");
857 Mnemonic = AsmOperands[0].Token;
858 if (Mnemonic.empty())
859 throw TGError(TheDef->getLoc(),
860 "Missing instruction mnemonic");
861 // FIXME : Check and raise an error if it is a register.
862 if (Mnemonic[0] == '$')
863 throw TGError(TheDef->getLoc(),
864 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
866 // Remove the first operand, it is tracked in the mnemonic field.
867 AsmOperands.erase(AsmOperands.begin());
870 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
871 // Reject matchables with no .s string.
872 if (AsmString.empty())
873 throw TGError(TheDef->getLoc(), "instruction with empty asm string");
875 // Reject any matchables with a newline in them, they should be marked
876 // isCodeGenOnly if they are pseudo instructions.
877 if (AsmString.find('\n') != std::string::npos)
878 throw TGError(TheDef->getLoc(),
879 "multiline instruction is not valid for the asmparser, "
880 "mark it isCodeGenOnly");
882 // Remove comments from the asm string. We know that the asmstring only
884 if (!CommentDelimiter.empty() &&
885 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
886 throw TGError(TheDef->getLoc(),
887 "asmstring for instruction has comment character in it, "
888 "mark it isCodeGenOnly");
890 // Reject matchables with operand modifiers, these aren't something we can
891 // handle, the target should be refactored to use operands instead of
894 // Also, check for instructions which reference the operand multiple times;
895 // this implies a constraint we would not honor.
896 std::set<std::string> OperandNames;
897 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
898 StringRef Tok = AsmOperands[i].Token;
899 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
900 throw TGError(TheDef->getLoc(),
901 "matchable with operand modifier '" + Tok.str() +
902 "' not supported by asm matcher. Mark isCodeGenOnly!");
904 // Verify that any operand is only mentioned once.
905 // We reject aliases and ignore instructions for now.
906 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
908 throw TGError(TheDef->getLoc(),
909 "ERROR: matchable with tied operand '" + Tok.str() +
910 "' can never be matched!");
911 // FIXME: Should reject these. The ARM backend hits this with $lane in a
912 // bunch of instructions. It is unclear what the right answer is.
914 errs() << "warning: '" << TheDef->getName() << "': "
915 << "ignoring instruction with tied operand '"
916 << Tok.str() << "'\n";
925 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
926 /// if present, from specified token.
928 extractSingletonRegisterForAsmOperand(unsigned OperandNo,
929 const AsmMatcherInfo &Info,
930 std::string &RegisterPrefix) {
931 StringRef Tok = AsmOperands[OperandNo].Token;
932 if (RegisterPrefix.empty()) {
933 std::string LoweredTok = Tok.lower();
934 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
935 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
939 if (!Tok.startswith(RegisterPrefix))
942 StringRef RegName = Tok.substr(RegisterPrefix.size());
943 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
944 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
946 // If there is no register prefix (i.e. "%" in "%eax"), then this may
947 // be some random non-register token, just ignore it.
951 static std::string getEnumNameForToken(StringRef Str) {
954 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
956 case '*': Res += "_STAR_"; break;
957 case '%': Res += "_PCT_"; break;
958 case ':': Res += "_COLON_"; break;
959 case '!': Res += "_EXCLAIM_"; break;
960 case '.': Res += "_DOT_"; break;
965 Res += "_" + utostr((unsigned) *it) + "_";
972 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
973 ClassInfo *&Entry = TokenClasses[Token];
976 Entry = new ClassInfo();
977 Entry->Kind = ClassInfo::Token;
978 Entry->ClassName = "Token";
979 Entry->Name = "MCK_" + getEnumNameForToken(Token);
980 Entry->ValueName = Token;
981 Entry->PredicateMethod = "<invalid>";
982 Entry->RenderMethod = "<invalid>";
983 Entry->ParserMethod = "";
984 Entry->DiagnosticType = "";
985 Classes.push_back(Entry);
992 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
994 Record *Rec = OI.Rec;
996 Rec = dynamic_cast<DefInit*>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
997 return getOperandClass(Rec, SubOpIdx);
1001 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1002 if (Rec->isSubClassOf("RegisterOperand")) {
1003 // RegisterOperand may have an associated ParserMatchClass. If it does,
1004 // use it, else just fall back to the underlying register class.
1005 const RecordVal *R = Rec->getValue("ParserMatchClass");
1006 if (R == 0 || R->getValue() == 0)
1007 throw "Record `" + Rec->getName() +
1008 "' does not have a ParserMatchClass!\n";
1010 if (DefInit *DI= dynamic_cast<DefInit*>(R->getValue())) {
1011 Record *MatchClass = DI->getDef();
1012 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1016 // No custom match class. Just use the register class.
1017 Record *ClassRec = Rec->getValueAsDef("RegClass");
1019 throw TGError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1020 "' has no associated register class!\n");
1021 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1023 throw TGError(Rec->getLoc(), "register class has no class info!");
1027 if (Rec->isSubClassOf("RegisterClass")) {
1028 if (ClassInfo *CI = RegisterClassClasses[Rec])
1030 throw TGError(Rec->getLoc(), "register class has no class info!");
1033 if (!Rec->isSubClassOf("Operand"))
1034 throw TGError(Rec->getLoc(), "Operand `" + Rec->getName() +
1035 "' does not derive from class Operand!\n");
1036 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1037 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1040 throw TGError(Rec->getLoc(), "operand has no match class!");
1043 void AsmMatcherInfo::
1044 buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
1045 const std::vector<CodeGenRegister*> &Registers =
1046 Target.getRegBank().getRegisters();
1047 ArrayRef<CodeGenRegisterClass*> RegClassList =
1048 Target.getRegBank().getRegClasses();
1050 // The register sets used for matching.
1051 std::set< std::set<Record*> > RegisterSets;
1053 // Gather the defined sets.
1054 for (ArrayRef<CodeGenRegisterClass*>::const_iterator it =
1055 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
1056 RegisterSets.insert(std::set<Record*>(
1057 (*it)->getOrder().begin(), (*it)->getOrder().end()));
1059 // Add any required singleton sets.
1060 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1061 ie = SingletonRegisters.end(); it != ie; ++it) {
1063 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
1066 // Introduce derived sets where necessary (when a register does not determine
1067 // a unique register set class), and build the mapping of registers to the set
1068 // they should classify to.
1069 std::map<Record*, std::set<Record*> > RegisterMap;
1070 for (std::vector<CodeGenRegister*>::const_iterator it = Registers.begin(),
1071 ie = Registers.end(); it != ie; ++it) {
1072 const CodeGenRegister &CGR = **it;
1073 // Compute the intersection of all sets containing this register.
1074 std::set<Record*> ContainingSet;
1076 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1077 ie = RegisterSets.end(); it != ie; ++it) {
1078 if (!it->count(CGR.TheDef))
1081 if (ContainingSet.empty()) {
1082 ContainingSet = *it;
1086 std::set<Record*> Tmp;
1087 std::swap(Tmp, ContainingSet);
1088 std::insert_iterator< std::set<Record*> > II(ContainingSet,
1089 ContainingSet.begin());
1090 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
1093 if (!ContainingSet.empty()) {
1094 RegisterSets.insert(ContainingSet);
1095 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1099 // Construct the register classes.
1100 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
1102 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1103 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
1104 ClassInfo *CI = new ClassInfo();
1105 CI->Kind = ClassInfo::RegisterClass0 + Index;
1106 CI->ClassName = "Reg" + utostr(Index);
1107 CI->Name = "MCK_Reg" + utostr(Index);
1109 CI->PredicateMethod = ""; // unused
1110 CI->RenderMethod = "addRegOperands";
1111 CI->Registers = *it;
1112 // FIXME: diagnostic type.
1113 CI->DiagnosticType = "";
1114 Classes.push_back(CI);
1115 RegisterSetClasses.insert(std::make_pair(*it, CI));
1118 // Find the superclasses; we could compute only the subgroup lattice edges,
1119 // but there isn't really a point.
1120 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1121 ie = RegisterSets.end(); it != ie; ++it) {
1122 ClassInfo *CI = RegisterSetClasses[*it];
1123 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
1124 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
1126 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
1127 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
1130 // Name the register classes which correspond to a user defined RegisterClass.
1131 for (ArrayRef<CodeGenRegisterClass*>::const_iterator
1132 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
1133 const CodeGenRegisterClass &RC = **it;
1134 // Def will be NULL for non-user defined register classes.
1135 Record *Def = RC.getDef();
1138 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(RC.getOrder().begin(),
1139 RC.getOrder().end())];
1140 if (CI->ValueName.empty()) {
1141 CI->ClassName = RC.getName();
1142 CI->Name = "MCK_" + RC.getName();
1143 CI->ValueName = RC.getName();
1145 CI->ValueName = CI->ValueName + "," + RC.getName();
1147 RegisterClassClasses.insert(std::make_pair(Def, CI));
1150 // Populate the map for individual registers.
1151 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
1152 ie = RegisterMap.end(); it != ie; ++it)
1153 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1155 // Name the register classes which correspond to singleton registers.
1156 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1157 ie = SingletonRegisters.end(); it != ie; ++it) {
1159 ClassInfo *CI = RegisterClasses[Rec];
1160 assert(CI && "Missing singleton register class info!");
1162 if (CI->ValueName.empty()) {
1163 CI->ClassName = Rec->getName();
1164 CI->Name = "MCK_" + Rec->getName();
1165 CI->ValueName = Rec->getName();
1167 CI->ValueName = CI->ValueName + "," + Rec->getName();
1171 void AsmMatcherInfo::buildOperandClasses() {
1172 std::vector<Record*> AsmOperands =
1173 Records.getAllDerivedDefinitions("AsmOperandClass");
1175 // Pre-populate AsmOperandClasses map.
1176 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1177 ie = AsmOperands.end(); it != ie; ++it)
1178 AsmOperandClasses[*it] = new ClassInfo();
1181 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1182 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
1183 ClassInfo *CI = AsmOperandClasses[*it];
1184 CI->Kind = ClassInfo::UserClass0 + Index;
1186 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
1187 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
1188 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
1190 PrintError((*it)->getLoc(), "Invalid super class reference!");
1194 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1196 PrintError((*it)->getLoc(), "Invalid super class reference!");
1198 CI->SuperClasses.push_back(SC);
1200 CI->ClassName = (*it)->getValueAsString("Name");
1201 CI->Name = "MCK_" + CI->ClassName;
1202 CI->ValueName = (*it)->getName();
1204 // Get or construct the predicate method name.
1205 Init *PMName = (*it)->getValueInit("PredicateMethod");
1206 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
1207 CI->PredicateMethod = SI->getValue();
1209 assert(dynamic_cast<UnsetInit*>(PMName) &&
1210 "Unexpected PredicateMethod field!");
1211 CI->PredicateMethod = "is" + CI->ClassName;
1214 // Get or construct the render method name.
1215 Init *RMName = (*it)->getValueInit("RenderMethod");
1216 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
1217 CI->RenderMethod = SI->getValue();
1219 assert(dynamic_cast<UnsetInit*>(RMName) &&
1220 "Unexpected RenderMethod field!");
1221 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1224 // Get the parse method name or leave it as empty.
1225 Init *PRMName = (*it)->getValueInit("ParserMethod");
1226 if (StringInit *SI = dynamic_cast<StringInit*>(PRMName))
1227 CI->ParserMethod = SI->getValue();
1229 // Get the diagnostic type or leave it as empty.
1230 // Get the parse method name or leave it as empty.
1231 Init *DiagnosticType = (*it)->getValueInit("DiagnosticType");
1232 if (StringInit *SI = dynamic_cast<StringInit*>(DiagnosticType))
1233 CI->DiagnosticType = SI->getValue();
1235 AsmOperandClasses[*it] = CI;
1236 Classes.push_back(CI);
1240 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1241 CodeGenTarget &target,
1242 RecordKeeper &records)
1243 : Records(records), AsmParser(asmParser), Target(target) {
1246 /// buildOperandMatchInfo - Build the necessary information to handle user
1247 /// defined operand parsing methods.
1248 void AsmMatcherInfo::buildOperandMatchInfo() {
1250 /// Map containing a mask with all operands indices that can be found for
1251 /// that class inside a instruction.
1252 typedef std::map<ClassInfo*, unsigned, LessClassInfoPtr> OpClassMaskTy;
1253 OpClassMaskTy OpClassMask;
1255 for (std::vector<MatchableInfo*>::const_iterator it =
1256 Matchables.begin(), ie = Matchables.end();
1258 MatchableInfo &II = **it;
1259 OpClassMask.clear();
1261 // Keep track of all operands of this instructions which belong to the
1263 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1264 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1265 if (Op.Class->ParserMethod.empty())
1267 unsigned &OperandMask = OpClassMask[Op.Class];
1268 OperandMask |= (1 << i);
1271 // Generate operand match info for each mnemonic/operand class pair.
1272 for (OpClassMaskTy::iterator iit = OpClassMask.begin(),
1273 iie = OpClassMask.end(); iit != iie; ++iit) {
1274 unsigned OpMask = iit->second;
1275 ClassInfo *CI = iit->first;
1276 OperandMatchInfo.push_back(OperandMatchEntry::create(&II, CI, OpMask));
1281 void AsmMatcherInfo::buildInfo() {
1282 // Build information about all of the AssemblerPredicates.
1283 std::vector<Record*> AllPredicates =
1284 Records.getAllDerivedDefinitions("Predicate");
1285 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1286 Record *Pred = AllPredicates[i];
1287 // Ignore predicates that are not intended for the assembler.
1288 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1291 if (Pred->getName().empty())
1292 throw TGError(Pred->getLoc(), "Predicate has no name!");
1294 unsigned FeatureNo = SubtargetFeatures.size();
1295 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1296 assert(FeatureNo < 32 && "Too many subtarget features!");
1299 // Parse the instructions; we need to do this first so that we can gather the
1300 // singleton register classes.
1301 SmallPtrSet<Record*, 16> SingletonRegisters;
1302 unsigned VariantCount = Target.getAsmParserVariantCount();
1303 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1304 Record *AsmVariant = Target.getAsmParserVariant(VC);
1305 std::string CommentDelimiter =
1306 AsmVariant->getValueAsString("CommentDelimiter");
1307 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1308 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1310 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1311 E = Target.inst_end(); I != E; ++I) {
1312 const CodeGenInstruction &CGI = **I;
1314 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1315 // filter the set of instructions we consider.
1316 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1319 // Ignore "codegen only" instructions.
1320 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1323 // Validate the operand list to ensure we can handle this instruction.
1324 for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) {
1325 const CGIOperandList::OperandInfo &OI = CGI.Operands[i];
1327 // Validate tied operands.
1328 if (OI.getTiedRegister() != -1) {
1329 // If we have a tied operand that consists of multiple MCOperands,
1330 // reject it. We reject aliases and ignore instructions for now.
1331 if (OI.MINumOperands != 1) {
1332 // FIXME: Should reject these. The ARM backend hits this with $lane
1333 // in a bunch of instructions. The right answer is unclear.
1335 errs() << "warning: '" << CGI.TheDef->getName() << "': "
1336 << "ignoring instruction with multi-operand tied operand '"
1337 << OI.Name << "'\n";
1344 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1346 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1348 // Ignore instructions which shouldn't be matched and diagnose invalid
1349 // instruction definitions with an error.
1350 if (!II->validate(CommentDelimiter, true))
1353 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1355 // FIXME: This is a total hack.
1356 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1357 StringRef(II->TheDef->getName()).endswith("_Int"))
1360 Matchables.push_back(II.take());
1363 // Parse all of the InstAlias definitions and stick them in the list of
1365 std::vector<Record*> AllInstAliases =
1366 Records.getAllDerivedDefinitions("InstAlias");
1367 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1368 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1370 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1371 // filter the set of instruction aliases we consider, based on the target
1373 if (!StringRef(Alias->ResultInst->TheDef->getName())
1374 .startswith( MatchPrefix))
1377 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1379 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1381 // Validate the alias definitions.
1382 II->validate(CommentDelimiter, false);
1384 Matchables.push_back(II.take());
1388 // Build info for the register classes.
1389 buildRegisterClasses(SingletonRegisters);
1391 // Build info for the user defined assembly operand classes.
1392 buildOperandClasses();
1394 // Build the information about matchables, now that we have fully formed
1396 std::vector<MatchableInfo*> NewMatchables;
1397 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1398 ie = Matchables.end(); it != ie; ++it) {
1399 MatchableInfo *II = *it;
1401 // Parse the tokens after the mnemonic.
1402 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1403 // don't precompute the loop bound.
1404 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1405 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1406 StringRef Token = Op.Token;
1408 // Check for singleton registers.
1409 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1410 Op.Class = RegisterClasses[RegRecord];
1411 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1412 "Unexpected class for singleton register");
1416 // Check for simple tokens.
1417 if (Token[0] != '$') {
1418 Op.Class = getTokenClass(Token);
1422 if (Token.size() > 1 && isdigit(Token[1])) {
1423 Op.Class = getTokenClass(Token);
1427 // Otherwise this is an operand reference.
1428 StringRef OperandName;
1429 if (Token[1] == '{')
1430 OperandName = Token.substr(2, Token.size() - 3);
1432 OperandName = Token.substr(1);
1434 if (II->DefRec.is<const CodeGenInstruction*>())
1435 buildInstructionOperandReference(II, OperandName, i);
1437 buildAliasOperandReference(II, OperandName, Op);
1440 if (II->DefRec.is<const CodeGenInstruction*>()) {
1441 II->buildInstructionResultOperands();
1442 // If the instruction has a two-operand alias, build up the
1443 // matchable here. We'll add them in bulk at the end to avoid
1444 // confusing this loop.
1445 std::string Constraint =
1446 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1447 if (Constraint != "") {
1448 // Start by making a copy of the original matchable.
1449 OwningPtr<MatchableInfo> AliasII(new MatchableInfo(*II));
1451 // Adjust it to be a two-operand alias.
1452 AliasII->formTwoOperandAlias(Constraint);
1454 // Add the alias to the matchables list.
1455 NewMatchables.push_back(AliasII.take());
1458 II->buildAliasResultOperands();
1460 if (!NewMatchables.empty())
1461 Matchables.insert(Matchables.end(), NewMatchables.begin(),
1462 NewMatchables.end());
1464 // Process token alias definitions and set up the associated superclass
1466 std::vector<Record*> AllTokenAliases =
1467 Records.getAllDerivedDefinitions("TokenAlias");
1468 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1469 Record *Rec = AllTokenAliases[i];
1470 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1471 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1472 if (FromClass == ToClass)
1473 throw TGError(Rec->getLoc(),
1474 "error: Destination value identical to source value.");
1475 FromClass->SuperClasses.push_back(ToClass);
1478 // Reorder classes so that classes precede super classes.
1479 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1482 /// buildInstructionOperandReference - The specified operand is a reference to a
1483 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1484 void AsmMatcherInfo::
1485 buildInstructionOperandReference(MatchableInfo *II,
1486 StringRef OperandName,
1487 unsigned AsmOpIdx) {
1488 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1489 const CGIOperandList &Operands = CGI.Operands;
1490 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1492 // Map this token to an operand.
1494 if (!Operands.hasOperandNamed(OperandName, Idx))
1495 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1496 OperandName.str() + "'");
1498 // If the instruction operand has multiple suboperands, but the parser
1499 // match class for the asm operand is still the default "ImmAsmOperand",
1500 // then handle each suboperand separately.
1501 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1502 Record *Rec = Operands[Idx].Rec;
1503 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1504 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1505 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1506 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1507 StringRef Token = Op->Token; // save this in case Op gets moved
1508 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1509 MatchableInfo::AsmOperand NewAsmOp(Token);
1510 NewAsmOp.SubOpIdx = SI;
1511 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1513 // Replace Op with first suboperand.
1514 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1519 // Set up the operand class.
1520 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1522 // If the named operand is tied, canonicalize it to the untied operand.
1523 // For example, something like:
1524 // (outs GPR:$dst), (ins GPR:$src)
1525 // with an asmstring of
1527 // we want to canonicalize to:
1529 // so that we know how to provide the $dst operand when filling in the result.
1530 int OITied = Operands[Idx].getTiedRegister();
1532 // The tied operand index is an MIOperand index, find the operand that
1534 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1535 OperandName = Operands[Idx.first].Name;
1536 Op->SubOpIdx = Idx.second;
1539 Op->SrcOpName = OperandName;
1542 /// buildAliasOperandReference - When parsing an operand reference out of the
1543 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1544 /// operand reference is by looking it up in the result pattern definition.
1545 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1546 StringRef OperandName,
1547 MatchableInfo::AsmOperand &Op) {
1548 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1550 // Set up the operand class.
1551 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1552 if (CGA.ResultOperands[i].isRecord() &&
1553 CGA.ResultOperands[i].getName() == OperandName) {
1554 // It's safe to go with the first one we find, because CodeGenInstAlias
1555 // validates that all operands with the same name have the same record.
1556 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1557 // Use the match class from the Alias definition, not the
1558 // destination instruction, as we may have an immediate that's
1559 // being munged by the match class.
1560 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1562 Op.SrcOpName = OperandName;
1566 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1567 OperandName.str() + "'");
1570 void MatchableInfo::buildInstructionResultOperands() {
1571 const CodeGenInstruction *ResultInst = getResultInst();
1573 // Loop over all operands of the result instruction, determining how to
1575 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1576 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1578 // If this is a tied operand, just copy from the previously handled operand.
1579 int TiedOp = OpInfo.getTiedRegister();
1581 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1585 // Find out what operand from the asmparser this MCInst operand comes from.
1586 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1587 if (OpInfo.Name.empty() || SrcOperand == -1)
1588 throw TGError(TheDef->getLoc(), "Instruction '" +
1589 TheDef->getName() + "' has operand '" + OpInfo.Name +
1590 "' that doesn't appear in asm string!");
1592 // Check if the one AsmOperand populates the entire operand.
1593 unsigned NumOperands = OpInfo.MINumOperands;
1594 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1595 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1599 // Add a separate ResOperand for each suboperand.
1600 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1601 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1602 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1603 "unexpected AsmOperands for suboperands");
1604 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1609 void MatchableInfo::buildAliasResultOperands() {
1610 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1611 const CodeGenInstruction *ResultInst = getResultInst();
1613 // Loop over all operands of the result instruction, determining how to
1615 unsigned AliasOpNo = 0;
1616 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1617 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1618 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1620 // If this is a tied operand, just copy from the previously handled operand.
1621 int TiedOp = OpInfo->getTiedRegister();
1623 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1627 // Handle all the suboperands for this operand.
1628 const std::string &OpName = OpInfo->Name;
1629 for ( ; AliasOpNo < LastOpNo &&
1630 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1631 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1633 // Find out what operand from the asmparser that this MCInst operand
1635 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1636 case CodeGenInstAlias::ResultOperand::K_Record: {
1637 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1638 int SrcOperand = findAsmOperand(Name, SubIdx);
1639 if (SrcOperand == -1)
1640 throw TGError(TheDef->getLoc(), "Instruction '" +
1641 TheDef->getName() + "' has operand '" + OpName +
1642 "' that doesn't appear in asm string!");
1643 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1644 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1648 case CodeGenInstAlias::ResultOperand::K_Imm: {
1649 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1650 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1653 case CodeGenInstAlias::ResultOperand::K_Reg: {
1654 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1655 ResOperands.push_back(ResOperand::getRegOp(Reg));
1663 static unsigned getConverterOperandID(const std::string &Name,
1664 SetVector<std::string> &Table,
1666 IsNew = Table.insert(Name);
1668 unsigned ID = IsNew ? Table.size() - 1 :
1669 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1671 assert(ID < Table.size());
1677 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1678 std::vector<MatchableInfo*> &Infos,
1680 SetVector<std::string> OperandConversionKinds;
1681 SetVector<std::string> InstructionConversionKinds;
1682 std::vector<std::vector<uint8_t> > ConversionTable;
1683 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1685 // TargetOperandClass - This is the target's operand class, like X86Operand.
1686 std::string TargetOperandClass = Target.getName() + "Operand";
1688 // Write the convert function to a separate stream, so we can drop it after
1689 // the enum. We'll build up the conversion handlers for the individual
1690 // operand types opportunistically as we encounter them.
1691 std::string ConvertFnBody;
1692 raw_string_ostream CvtOS(ConvertFnBody);
1693 // Start the unified conversion function.
1694 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1695 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1696 << "unsigned Opcode,\n"
1697 << " const SmallVectorImpl<MCParsedAsmOperand*"
1698 << "> &Operands) {\n"
1699 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1700 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1701 << " Inst.setOpcode(Opcode);\n"
1702 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1703 << " switch (*p) {\n"
1704 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1705 << " case CVT_Reg:\n"
1706 << " static_cast<" << TargetOperandClass
1707 << "*>(Operands[*(p + 1)])->addRegOperands(Inst, 1);\n"
1709 << " case CVT_Tied:\n"
1710 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1713 std::string OperandFnBody;
1714 raw_string_ostream OpOS(OperandFnBody);
1715 // Start the operand number lookup function.
1716 OpOS << "void " << Target.getName() << ClassName << "::\n"
1717 << "convertToMapAndConstraints(unsigned Kind,\n";
1719 OpOS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
1721 OpOS << "MatchInstMapAndConstraintsImpl &MapAndConstraints) {\n"
1722 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1723 << " unsigned NumMCOperands = 0;\n"
1724 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1725 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1726 << " switch (*p) {\n"
1727 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1728 << " case CVT_Reg:\n"
1729 << " case CVT_Tied:\n"
1730 << " MapAndConstraints.push_back(std::make_pair(NumMCOperands,"
1732 << " ++NumMCOperands;\n"
1735 // Pre-populate the operand conversion kinds with the standard always
1736 // available entries.
1737 OperandConversionKinds.insert("CVT_Done");
1738 OperandConversionKinds.insert("CVT_Reg");
1739 OperandConversionKinds.insert("CVT_Tied");
1740 enum { CVT_Done, CVT_Reg, CVT_Tied };
1742 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1743 ie = Infos.end(); it != ie; ++it) {
1744 MatchableInfo &II = **it;
1746 // Check if we have a custom match function.
1747 std::string AsmMatchConverter =
1748 II.getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1749 if (!AsmMatchConverter.empty()) {
1750 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1751 II.ConversionFnKind = Signature;
1753 // Check if we have already generated this signature.
1754 if (!InstructionConversionKinds.insert(Signature))
1757 // Remember this converter for the kind enum.
1758 unsigned KindID = OperandConversionKinds.size();
1759 OperandConversionKinds.insert("CVT_" + AsmMatchConverter);
1761 // Add the converter row for this instruction.
1762 ConversionTable.push_back(std::vector<uint8_t>());
1763 ConversionTable.back().push_back(KindID);
1764 ConversionTable.back().push_back(CVT_Done);
1766 // Add the handler to the conversion driver function.
1767 CvtOS << " case CVT_" << AsmMatchConverter << ":\n"
1768 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1771 // FIXME: Handle the operand number lookup for custom match functions.
1775 // Build the conversion function signature.
1776 std::string Signature = "Convert";
1778 std::vector<uint8_t> ConversionRow;
1780 // Compute the convert enum and the case body.
1781 MaxRowLength = std::max(MaxRowLength, II.ResOperands.size()*2 + 1 );
1783 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1784 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1786 // Generate code to populate each result operand.
1787 switch (OpInfo.Kind) {
1788 case MatchableInfo::ResOperand::RenderAsmOperand: {
1789 // This comes from something we parsed.
1790 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1792 // Registers are always converted the same, don't duplicate the
1793 // conversion function based on them.
1796 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1798 Signature += utostr(OpInfo.MINumOperands);
1799 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1801 // Add the conversion kind, if necessary, and get the associated ID
1802 // the index of its entry in the vector).
1803 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1804 Op.Class->RenderMethod);
1806 bool IsNewConverter = false;
1807 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1810 // Add the operand entry to the instruction kind conversion row.
1811 ConversionRow.push_back(ID);
1812 ConversionRow.push_back(OpInfo.AsmOperandNum + 1);
1814 if (!IsNewConverter)
1817 // This is a new operand kind. Add a handler for it to the
1818 // converter driver.
1819 CvtOS << " case " << Name << ":\n"
1820 << " static_cast<" << TargetOperandClass
1821 << "*>(Operands[*(p + 1)])->"
1822 << Op.Class->RenderMethod << "(Inst, " << OpInfo.MINumOperands
1826 // Add a handler for the operand number lookup.
1827 OpOS << " case " << Name << ":\n"
1828 << " MapAndConstraints.push_back(std::make_pair(NumMCOperands"
1830 << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
1834 case MatchableInfo::ResOperand::TiedOperand: {
1835 // If this operand is tied to a previous one, just copy the MCInst
1836 // operand from the earlier one.We can only tie single MCOperand values.
1837 //assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1838 unsigned TiedOp = OpInfo.TiedOperandNum;
1839 assert(i > TiedOp && "Tied operand precedes its target!");
1840 Signature += "__Tie" + utostr(TiedOp);
1841 ConversionRow.push_back(CVT_Tied);
1842 ConversionRow.push_back(TiedOp);
1843 // FIXME: Handle the operand number lookup for tied operands.
1846 case MatchableInfo::ResOperand::ImmOperand: {
1847 int64_t Val = OpInfo.ImmVal;
1848 std::string Ty = "imm_" + itostr(Val);
1849 Signature += "__" + Ty;
1851 std::string Name = "CVT_" + Ty;
1852 bool IsNewConverter = false;
1853 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1855 // Add the operand entry to the instruction kind conversion row.
1856 ConversionRow.push_back(ID);
1857 ConversionRow.push_back(0);
1859 if (!IsNewConverter)
1862 CvtOS << " case " << Name << ":\n"
1863 << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"
1866 OpOS << " case " << Name << ":\n"
1867 << " MapAndConstraints.push_back(std::make_pair(NumMCOperands"
1869 << " ++NumMCOperands;\n"
1873 case MatchableInfo::ResOperand::RegOperand: {
1874 std::string Reg, Name;
1875 if (OpInfo.Register == 0) {
1879 Reg = getQualifiedName(OpInfo.Register);
1880 Name = "reg" + OpInfo.Register->getName();
1882 Signature += "__" + Name;
1883 Name = "CVT_" + Name;
1884 bool IsNewConverter = false;
1885 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1887 // Add the operand entry to the instruction kind conversion row.
1888 ConversionRow.push_back(ID);
1889 ConversionRow.push_back(0);
1891 if (!IsNewConverter)
1893 CvtOS << " case " << Name << ":\n"
1894 << " Inst.addOperand(MCOperand::CreateReg(" << Reg << "));\n"
1897 OpOS << " case " << Name << ":\n"
1898 << " MapAndConstraints.push_back(std::make_pair(NumMCOperands"
1900 << " ++NumMCOperands;\n"
1906 // If there were no operands, add to the signature to that effect
1907 if (Signature == "Convert")
1908 Signature += "_NoOperands";
1910 II.ConversionFnKind = Signature;
1912 // Save the signature. If we already have it, don't add a new row
1914 if (!InstructionConversionKinds.insert(Signature))
1917 // Add the row to the table.
1918 ConversionTable.push_back(ConversionRow);
1921 // Finish up the converter driver function.
1922 CvtOS << " }\n }\n}\n\n";
1924 // Finish up the operand number lookup function.
1925 OpOS << " }\n }\n}\n\n";
1927 OS << "namespace {\n";
1929 // Output the operand conversion kind enum.
1930 OS << "enum OperatorConversionKind {\n";
1931 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i)
1932 OS << " " << OperandConversionKinds[i] << ",\n";
1933 OS << " CVT_NUM_CONVERTERS\n";
1936 // Output the instruction conversion kind enum.
1937 OS << "enum InstructionConversionKind {\n";
1938 for (SetVector<std::string>::const_iterator
1939 i = InstructionConversionKinds.begin(),
1940 e = InstructionConversionKinds.end(); i != e; ++i)
1941 OS << " " << *i << ",\n";
1942 OS << " CVT_NUM_SIGNATURES\n";
1946 OS << "} // end anonymous namespace\n\n";
1948 // Output the conversion table.
1949 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
1950 << MaxRowLength << "] = {\n";
1952 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
1953 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
1954 OS << " // " << InstructionConversionKinds[Row] << "\n";
1956 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
1957 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
1958 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
1959 OS << "CVT_Done },\n";
1964 // Spit out the conversion driver function.
1967 // Spit out the operand number lookup function.
1971 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
1972 static void emitMatchClassEnumeration(CodeGenTarget &Target,
1973 std::vector<ClassInfo*> &Infos,
1975 OS << "namespace {\n\n";
1977 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1978 << "/// instruction matching.\n";
1979 OS << "enum MatchClassKind {\n";
1980 OS << " InvalidMatchClass = 0,\n";
1981 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1982 ie = Infos.end(); it != ie; ++it) {
1983 ClassInfo &CI = **it;
1984 OS << " " << CI.Name << ", // ";
1985 if (CI.Kind == ClassInfo::Token) {
1986 OS << "'" << CI.ValueName << "'\n";
1987 } else if (CI.isRegisterClass()) {
1988 if (!CI.ValueName.empty())
1989 OS << "register class '" << CI.ValueName << "'\n";
1991 OS << "derived register class\n";
1993 OS << "user defined class '" << CI.ValueName << "'\n";
1996 OS << " NumMatchClassKinds\n";
2002 /// emitValidateOperandClass - Emit the function to validate an operand class.
2003 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2005 OS << "static unsigned validateOperandClass(MCParsedAsmOperand *GOp, "
2006 << "MatchClassKind Kind) {\n";
2007 OS << " " << Info.Target.getName() << "Operand &Operand = *("
2008 << Info.Target.getName() << "Operand*)GOp;\n";
2010 // The InvalidMatchClass is not to match any operand.
2011 OS << " if (Kind == InvalidMatchClass)\n";
2012 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2014 // Check for Token operands first.
2015 // FIXME: Use a more specific diagnostic type.
2016 OS << " if (Operand.isToken())\n";
2017 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2018 << " MCTargetAsmParser::Match_Success :\n"
2019 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2021 // Check the user classes. We don't care what order since we're only
2022 // actually matching against one of them.
2023 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
2024 ie = Info.Classes.end(); it != ie; ++it) {
2025 ClassInfo &CI = **it;
2027 if (!CI.isUserClass())
2030 OS << " // '" << CI.ClassName << "' class\n";
2031 OS << " if (Kind == " << CI.Name << ") {\n";
2032 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2033 OS << " return MCTargetAsmParser::Match_Success;\n";
2034 if (!CI.DiagnosticType.empty())
2035 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2036 << CI.DiagnosticType << ";\n";
2040 // Check for register operands, including sub-classes.
2041 OS << " if (Operand.isReg()) {\n";
2042 OS << " MatchClassKind OpKind;\n";
2043 OS << " switch (Operand.getReg()) {\n";
2044 OS << " default: OpKind = InvalidMatchClass; break;\n";
2045 for (AsmMatcherInfo::RegisterClassesTy::iterator
2046 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
2048 OS << " case " << Info.Target.getName() << "::"
2049 << it->first->getName() << ": OpKind = " << it->second->Name
2052 OS << " return isSubclass(OpKind, Kind) ? "
2053 << "MCTargetAsmParser::Match_Success :\n "
2054 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2056 // Generic fallthrough match failure case for operands that don't have
2057 // specialized diagnostic types.
2058 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2062 /// emitIsSubclass - Emit the subclass predicate function.
2063 static void emitIsSubclass(CodeGenTarget &Target,
2064 std::vector<ClassInfo*> &Infos,
2066 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2067 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2068 OS << " if (A == B)\n";
2069 OS << " return true;\n\n";
2071 OS << " switch (A) {\n";
2072 OS << " default:\n";
2073 OS << " return false;\n";
2074 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2075 ie = Infos.end(); it != ie; ++it) {
2076 ClassInfo &A = **it;
2078 std::vector<StringRef> SuperClasses;
2079 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2080 ie = Infos.end(); it != ie; ++it) {
2081 ClassInfo &B = **it;
2083 if (&A != &B && A.isSubsetOf(B))
2084 SuperClasses.push_back(B.Name);
2087 if (SuperClasses.empty())
2090 OS << "\n case " << A.Name << ":\n";
2092 if (SuperClasses.size() == 1) {
2093 OS << " return B == " << SuperClasses.back() << ";\n";
2097 OS << " switch (B) {\n";
2098 OS << " default: return false;\n";
2099 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
2100 OS << " case " << SuperClasses[i] << ": return true;\n";
2107 /// emitMatchTokenString - Emit the function to match a token string to the
2108 /// appropriate match class value.
2109 static void emitMatchTokenString(CodeGenTarget &Target,
2110 std::vector<ClassInfo*> &Infos,
2112 // Construct the match list.
2113 std::vector<StringMatcher::StringPair> Matches;
2114 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2115 ie = Infos.end(); it != ie; ++it) {
2116 ClassInfo &CI = **it;
2118 if (CI.Kind == ClassInfo::Token)
2119 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
2120 "return " + CI.Name + ";"));
2123 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2125 StringMatcher("Name", Matches, OS).Emit();
2127 OS << " return InvalidMatchClass;\n";
2131 /// emitMatchRegisterName - Emit the function to match a string to the target
2132 /// specific register enum.
2133 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2135 // Construct the match list.
2136 std::vector<StringMatcher::StringPair> Matches;
2137 const std::vector<CodeGenRegister*> &Regs =
2138 Target.getRegBank().getRegisters();
2139 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2140 const CodeGenRegister *Reg = Regs[i];
2141 if (Reg->TheDef->getValueAsString("AsmName").empty())
2144 Matches.push_back(StringMatcher::StringPair(
2145 Reg->TheDef->getValueAsString("AsmName"),
2146 "return " + utostr(Reg->EnumValue) + ";"));
2149 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2151 StringMatcher("Name", Matches, OS).Emit();
2153 OS << " return 0;\n";
2157 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2159 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2161 OS << "// Flags for subtarget features that participate in "
2162 << "instruction matching.\n";
2163 OS << "enum SubtargetFeatureFlag {\n";
2164 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2165 it = Info.SubtargetFeatures.begin(),
2166 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2167 SubtargetFeatureInfo &SFI = *it->second;
2168 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
2170 OS << " Feature_None = 0\n";
2174 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2175 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2176 // Get the set of diagnostic types from all of the operand classes.
2177 std::set<StringRef> Types;
2178 for (std::map<Record*, ClassInfo*>::const_iterator
2179 I = Info.AsmOperandClasses.begin(),
2180 E = Info.AsmOperandClasses.end(); I != E; ++I) {
2181 if (!I->second->DiagnosticType.empty())
2182 Types.insert(I->second->DiagnosticType);
2185 if (Types.empty()) return;
2187 // Now emit the enum entries.
2188 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end();
2190 OS << " Match_" << *I << ",\n";
2191 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2194 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2195 /// user-level name for a subtarget feature.
2196 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2197 OS << "// User-level names for subtarget features that participate in\n"
2198 << "// instruction matching.\n"
2199 << "static const char *getSubtargetFeatureName(unsigned Val) {\n"
2200 << " switch(Val) {\n";
2201 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2202 it = Info.SubtargetFeatures.begin(),
2203 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2204 SubtargetFeatureInfo &SFI = *it->second;
2205 // FIXME: Totally just a placeholder name to get the algorithm working.
2206 OS << " case " << SFI.getEnumName() << ": return \""
2207 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2209 OS << " default: return \"(unknown)\";\n";
2213 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2214 /// available features given a subtarget.
2215 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2217 std::string ClassName =
2218 Info.AsmParser->getValueAsString("AsmParserClassName");
2220 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
2221 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
2222 OS << " unsigned Features = 0;\n";
2223 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2224 it = Info.SubtargetFeatures.begin(),
2225 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2226 SubtargetFeatureInfo &SFI = *it->second;
2229 std::string CondStorage =
2230 SFI.TheDef->getValueAsString("AssemblerCondString");
2231 StringRef Conds = CondStorage;
2232 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2239 StringRef Cond = Comma.first;
2240 if (Cond[0] == '!') {
2242 Cond = Cond.substr(1);
2245 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
2252 if (Comma.second.empty())
2256 Comma = Comma.second.split(',');
2260 OS << " Features |= " << SFI.getEnumName() << ";\n";
2262 OS << " return Features;\n";
2266 static std::string GetAliasRequiredFeatures(Record *R,
2267 const AsmMatcherInfo &Info) {
2268 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2270 unsigned NumFeatures = 0;
2271 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2272 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2275 throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2276 "' is not marked as an AssemblerPredicate!");
2281 Result += F->getEnumName();
2285 if (NumFeatures > 1)
2286 Result = '(' + Result + ')';
2290 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2291 /// emit a function for them and return true, otherwise return false.
2292 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) {
2293 // Ignore aliases when match-prefix is set.
2294 if (!MatchPrefix.empty())
2297 std::vector<Record*> Aliases =
2298 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2299 if (Aliases.empty()) return false;
2301 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2302 "unsigned Features) {\n";
2304 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2305 // iteration order of the map is stable.
2306 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2308 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2309 Record *R = Aliases[i];
2310 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2313 // Process each alias a "from" mnemonic at a time, building the code executed
2314 // by the string remapper.
2315 std::vector<StringMatcher::StringPair> Cases;
2316 for (std::map<std::string, std::vector<Record*> >::iterator
2317 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2319 const std::vector<Record*> &ToVec = I->second;
2321 // Loop through each alias and emit code that handles each case. If there
2322 // are two instructions without predicates, emit an error. If there is one,
2324 std::string MatchCode;
2325 int AliasWithNoPredicate = -1;
2327 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2328 Record *R = ToVec[i];
2329 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2331 // If this unconditionally matches, remember it for later and diagnose
2333 if (FeatureMask.empty()) {
2334 if (AliasWithNoPredicate != -1) {
2335 // We can't have two aliases from the same mnemonic with no predicate.
2336 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2337 "two MnemonicAliases with the same 'from' mnemonic!");
2338 throw TGError(R->getLoc(), "this is the other MnemonicAlias.");
2341 AliasWithNoPredicate = i;
2344 if (R->getValueAsString("ToMnemonic") == I->first)
2345 throw TGError(R->getLoc(), "MnemonicAlias to the same string");
2347 if (!MatchCode.empty())
2348 MatchCode += "else ";
2349 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2350 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2353 if (AliasWithNoPredicate != -1) {
2354 Record *R = ToVec[AliasWithNoPredicate];
2355 if (!MatchCode.empty())
2356 MatchCode += "else\n ";
2357 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2360 MatchCode += "return;";
2362 Cases.push_back(std::make_pair(I->first, MatchCode));
2365 StringMatcher("Mnemonic", Cases, OS).Emit();
2371 static const char *getMinimalTypeForRange(uint64_t Range) {
2372 assert(Range < 0xFFFFFFFFULL && "Enum too large");
2380 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2381 const AsmMatcherInfo &Info, StringRef ClassName,
2382 StringToOffsetTable &StringTable,
2383 unsigned MaxMnemonicIndex) {
2384 unsigned MaxMask = 0;
2385 for (std::vector<OperandMatchEntry>::const_iterator it =
2386 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2388 MaxMask |= it->OperandMask;
2391 // Emit the static custom operand parsing table;
2392 OS << "namespace {\n";
2393 OS << " struct OperandMatchEntry {\n";
2394 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2395 << " RequiredFeatures;\n";
2396 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2398 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2400 OS << " " << getMinimalTypeForRange(MaxMask)
2401 << " OperandMask;\n\n";
2402 OS << " StringRef getMnemonic() const {\n";
2403 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2404 OS << " MnemonicTable[Mnemonic]);\n";
2408 OS << " // Predicate for searching for an opcode.\n";
2409 OS << " struct LessOpcodeOperand {\n";
2410 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2411 OS << " return LHS.getMnemonic() < RHS;\n";
2413 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2414 OS << " return LHS < RHS.getMnemonic();\n";
2416 OS << " bool operator()(const OperandMatchEntry &LHS,";
2417 OS << " const OperandMatchEntry &RHS) {\n";
2418 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2422 OS << "} // end anonymous namespace.\n\n";
2424 OS << "static const OperandMatchEntry OperandMatchTable["
2425 << Info.OperandMatchInfo.size() << "] = {\n";
2427 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2428 for (std::vector<OperandMatchEntry>::const_iterator it =
2429 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2431 const OperandMatchEntry &OMI = *it;
2432 const MatchableInfo &II = *OMI.MI;
2436 // Write the required features mask.
2437 if (!II.RequiredFeatures.empty()) {
2438 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2440 OS << II.RequiredFeatures[i]->getEnumName();
2445 // Store a pascal-style length byte in the mnemonic.
2446 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2447 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2448 << " /* " << II.Mnemonic << " */, ";
2452 OS << ", " << OMI.OperandMask;
2454 bool printComma = false;
2455 for (int i = 0, e = 31; i !=e; ++i)
2456 if (OMI.OperandMask & (1 << i)) {
2468 // Emit the operand class switch to call the correct custom parser for
2469 // the found operand class.
2470 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2471 << Target.getName() << ClassName << "::\n"
2472 << "tryCustomParseOperand(SmallVectorImpl<MCParsedAsmOperand*>"
2473 << " &Operands,\n unsigned MCK) {\n\n"
2474 << " switch(MCK) {\n";
2476 for (std::vector<ClassInfo*>::const_iterator it = Info.Classes.begin(),
2477 ie = Info.Classes.end(); it != ie; ++it) {
2478 ClassInfo *CI = *it;
2479 if (CI->ParserMethod.empty())
2481 OS << " case " << CI->Name << ":\n"
2482 << " return " << CI->ParserMethod << "(Operands);\n";
2485 OS << " default:\n";
2486 OS << " return MatchOperand_NoMatch;\n";
2488 OS << " return MatchOperand_NoMatch;\n";
2491 // Emit the static custom operand parser. This code is very similar with
2492 // the other matcher. Also use MatchResultTy here just in case we go for
2493 // a better error handling.
2494 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2495 << Target.getName() << ClassName << "::\n"
2496 << "MatchOperandParserImpl(SmallVectorImpl<MCParsedAsmOperand*>"
2497 << " &Operands,\n StringRef Mnemonic) {\n";
2499 // Emit code to get the available features.
2500 OS << " // Get the current feature set.\n";
2501 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2503 OS << " // Get the next operand index.\n";
2504 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2506 // Emit code to search the table.
2507 OS << " // Search the table.\n";
2508 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2509 OS << " MnemonicRange =\n";
2510 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2511 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2512 << " LessOpcodeOperand());\n\n";
2514 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2515 OS << " return MatchOperand_NoMatch;\n\n";
2517 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2518 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2520 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2521 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2523 // Emit check that the required features are available.
2524 OS << " // check if the available features match\n";
2525 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2526 << "!= it->RequiredFeatures) {\n";
2527 OS << " continue;\n";
2530 // Emit check to ensure the operand number matches.
2531 OS << " // check if the operand in question has a custom parser.\n";
2532 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2533 OS << " continue;\n\n";
2535 // Emit call to the custom parser method
2536 OS << " // call custom parse method to handle the operand\n";
2537 OS << " OperandMatchResultTy Result = ";
2538 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2539 OS << " if (Result != MatchOperand_NoMatch)\n";
2540 OS << " return Result;\n";
2543 OS << " // Okay, we had no match.\n";
2544 OS << " return MatchOperand_NoMatch;\n";
2548 void AsmMatcherEmitter::run(raw_ostream &OS) {
2549 CodeGenTarget Target(Records);
2550 Record *AsmParser = Target.getAsmParser();
2551 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2553 // Compute the information on the instructions to match.
2554 AsmMatcherInfo Info(AsmParser, Target, Records);
2557 // Sort the instruction table using the partial order on classes. We use
2558 // stable_sort to ensure that ambiguous instructions are still
2559 // deterministically ordered.
2560 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2561 less_ptr<MatchableInfo>());
2563 DEBUG_WITH_TYPE("instruction_info", {
2564 for (std::vector<MatchableInfo*>::iterator
2565 it = Info.Matchables.begin(), ie = Info.Matchables.end();
2570 // Check for ambiguous matchables.
2571 DEBUG_WITH_TYPE("ambiguous_instrs", {
2572 unsigned NumAmbiguous = 0;
2573 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
2574 for (unsigned j = i + 1; j != e; ++j) {
2575 MatchableInfo &A = *Info.Matchables[i];
2576 MatchableInfo &B = *Info.Matchables[j];
2578 if (A.couldMatchAmbiguouslyWith(B)) {
2579 errs() << "warning: ambiguous matchables:\n";
2581 errs() << "\nis incomparable with:\n";
2589 errs() << "warning: " << NumAmbiguous
2590 << " ambiguous matchables!\n";
2593 // Compute the information on the custom operand parsing.
2594 Info.buildOperandMatchInfo();
2596 // Write the output.
2598 // Information for the class declaration.
2599 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2600 OS << "#undef GET_ASSEMBLER_HEADER\n";
2601 OS << " // This should be included into the middle of the declaration of\n";
2602 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2603 OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
2604 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2605 << "unsigned Opcode,\n"
2606 << " const SmallVectorImpl<MCParsedAsmOperand*> "
2608 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2609 OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2611 OS << "MatchInstMapAndConstraintsImpl &MapAndConstraints);\n";
2612 OS << " bool mnemonicIsValid(StringRef Mnemonic);\n";
2613 OS << " unsigned MatchInstructionImpl(\n";
2615 OS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n"
2616 << " unsigned &Kind, MCInst &Inst,\n";
2618 OS << "MatchInstMapAndConstraintsImpl &MapAndConstraints,\n"
2619 << " unsigned &ErrorInfo,"
2620 << " bool matchingInlineAsm,\n"
2621 << " unsigned VariantID = 0);\n";
2623 if (Info.OperandMatchInfo.size()) {
2624 OS << "\n enum OperandMatchResultTy {\n";
2625 OS << " MatchOperand_Success, // operand matched successfully\n";
2626 OS << " MatchOperand_NoMatch, // operand did not match\n";
2627 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2629 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2630 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2631 OS << " StringRef Mnemonic);\n";
2633 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2634 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2635 OS << " unsigned MCK);\n\n";
2638 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2640 // Emit the operand match diagnostic enum names.
2641 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2642 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2643 emitOperandDiagnosticTypes(Info, OS);
2644 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2647 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2648 OS << "#undef GET_REGISTER_MATCHER\n\n";
2650 // Emit the subtarget feature enumeration.
2651 emitSubtargetFeatureFlagEnumeration(Info, OS);
2653 // Emit the function to match a register name to number.
2654 // This should be omitted for Mips target
2655 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2656 emitMatchRegisterName(Target, AsmParser, OS);
2658 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2660 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2661 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2663 // Generate the helper function to get the names for subtarget features.
2664 emitGetSubtargetFeatureName(Info, OS);
2666 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2668 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2669 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2671 // Generate the function that remaps for mnemonic aliases.
2672 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info);
2674 // Generate the convertToMCInst function to convert operands into an MCInst.
2675 // Also, generate the convertToMapAndConstraints function for MS-style inline
2676 // assembly. The latter doesn't actually generate a MCInst.
2677 emitConvertFuncs(Target, ClassName, Info.Matchables, OS);
2679 // Emit the enumeration for classes which participate in matching.
2680 emitMatchClassEnumeration(Target, Info.Classes, OS);
2682 // Emit the routine to match token strings to their match class.
2683 emitMatchTokenString(Target, Info.Classes, OS);
2685 // Emit the subclass predicate routine.
2686 emitIsSubclass(Target, Info.Classes, OS);
2688 // Emit the routine to validate an operand against a match class.
2689 emitValidateOperandClass(Info, OS);
2691 // Emit the available features compute function.
2692 emitComputeAvailableFeatures(Info, OS);
2695 StringToOffsetTable StringTable;
2697 size_t MaxNumOperands = 0;
2698 unsigned MaxMnemonicIndex = 0;
2699 for (std::vector<MatchableInfo*>::const_iterator it =
2700 Info.Matchables.begin(), ie = Info.Matchables.end();
2702 MatchableInfo &II = **it;
2703 MaxNumOperands = std::max(MaxNumOperands, II.AsmOperands.size());
2705 // Store a pascal-style length byte in the mnemonic.
2706 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2707 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2708 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2711 OS << "static const char *const MnemonicTable =\n";
2712 StringTable.EmitString(OS);
2715 // Emit the static match table; unused classes get initalized to 0 which is
2716 // guaranteed to be InvalidMatchClass.
2718 // FIXME: We can reduce the size of this table very easily. First, we change
2719 // it so that store the kinds in separate bit-fields for each index, which
2720 // only needs to be the max width used for classes at that index (we also need
2721 // to reject based on this during classification). If we then make sure to
2722 // order the match kinds appropriately (putting mnemonics last), then we
2723 // should only end up using a few bits for each class, especially the ones
2724 // following the mnemonic.
2725 OS << "namespace {\n";
2726 OS << " struct MatchEntry {\n";
2727 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2729 OS << " uint16_t Opcode;\n";
2730 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2732 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2733 << " RequiredFeatures;\n";
2734 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2735 << " Classes[" << MaxNumOperands << "];\n";
2736 OS << " uint8_t AsmVariantID;\n\n";
2737 OS << " StringRef getMnemonic() const {\n";
2738 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2739 OS << " MnemonicTable[Mnemonic]);\n";
2743 OS << " // Predicate for searching for an opcode.\n";
2744 OS << " struct LessOpcode {\n";
2745 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2746 OS << " return LHS.getMnemonic() < RHS;\n";
2748 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2749 OS << " return LHS < RHS.getMnemonic();\n";
2751 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2752 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2756 OS << "} // end anonymous namespace.\n\n";
2758 OS << "static const MatchEntry MatchTable["
2759 << Info.Matchables.size() << "] = {\n";
2761 for (std::vector<MatchableInfo*>::const_iterator it =
2762 Info.Matchables.begin(), ie = Info.Matchables.end();
2764 MatchableInfo &II = **it;
2766 // Store a pascal-style length byte in the mnemonic.
2767 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2768 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2769 << " /* " << II.Mnemonic << " */, "
2770 << Target.getName() << "::"
2771 << II.getResultInst()->TheDef->getName() << ", "
2772 << II.ConversionFnKind << ", ";
2774 // Write the required features mask.
2775 if (!II.RequiredFeatures.empty()) {
2776 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2778 OS << II.RequiredFeatures[i]->getEnumName();
2784 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
2785 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
2788 OS << Op.Class->Name;
2790 OS << " }, " << II.AsmVariantID;
2796 // A method to determine if a mnemonic is in the list.
2797 OS << "bool " << Target.getName() << ClassName << "::\n"
2798 << "mnemonicIsValid(StringRef Mnemonic) {\n";
2799 OS << " // Search the table.\n";
2800 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2801 OS << " std::equal_range(MatchTable, MatchTable+"
2802 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n";
2803 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2806 // Finally, build the match function.
2808 << Target.getName() << ClassName << "::\n"
2809 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
2811 OS << " unsigned &Kind, MCInst &Inst,\n"
2812 << "SmallVectorImpl<std::pair< unsigned, std::string > > &MapAndConstraints,\n"
2813 << "unsigned &ErrorInfo, bool matchingInlineAsm, unsigned VariantID) {\n";
2815 OS << " // Eliminate obvious mismatches.\n";
2816 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2817 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2818 OS << " return Match_InvalidOperand;\n";
2821 // Emit code to get the available features.
2822 OS << " // Get the current feature set.\n";
2823 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2825 OS << " // Get the instruction mnemonic, which is the first token.\n";
2826 OS << " StringRef Mnemonic = ((" << Target.getName()
2827 << "Operand*)Operands[0])->getToken();\n\n";
2829 if (HasMnemonicAliases) {
2830 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2831 OS << " // FIXME : Add an entry in AsmParserVariant to check this.\n";
2832 OS << " if (!VariantID)\n";
2833 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n";
2836 // Emit code to compute the class list for this operand vector.
2837 OS << " // Some state to try to produce better error messages.\n";
2838 OS << " bool HadMatchOtherThanFeatures = false;\n";
2839 OS << " bool HadMatchOtherThanPredicate = false;\n";
2840 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2841 OS << " unsigned MissingFeatures = ~0U;\n";
2842 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2843 OS << " // wrong for all instances of the instruction.\n";
2844 OS << " ErrorInfo = ~0U;\n";
2846 // Emit code to search the table.
2847 OS << " // Search the table.\n";
2848 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2849 OS << " std::equal_range(MatchTable, MatchTable+"
2850 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n";
2852 OS << " // Return a more specific error code if no mnemonics match.\n";
2853 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2854 OS << " return Match_MnemonicFail;\n\n";
2856 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2857 << "*ie = MnemonicRange.second;\n";
2858 OS << " it != ie; ++it) {\n";
2860 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2861 OS << " assert(Mnemonic == it->getMnemonic());\n";
2863 // Emit check that the subclasses match.
2864 OS << " if (VariantID != it->AsmVariantID) continue;\n";
2865 OS << " bool OperandsValid = true;\n";
2866 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2867 OS << " if (i + 1 >= Operands.size()) {\n";
2868 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2869 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n";
2872 OS << " unsigned Diag = validateOperandClass(Operands[i+1],\n";
2874 OS << "(MatchClassKind)it->Classes[i]);\n";
2875 OS << " if (Diag == Match_Success)\n";
2876 OS << " continue;\n";
2877 OS << " // If this operand is broken for all of the instances of this\n";
2878 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2879 OS << " // If we already had a match that only failed due to a\n";
2880 OS << " // target predicate, that diagnostic is preferred.\n";
2881 OS << " if (!HadMatchOtherThanPredicate &&\n";
2882 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n";
2883 OS << " ErrorInfo = i+1;\n";
2884 OS << " // InvalidOperand is the default. Prefer specificity.\n";
2885 OS << " if (Diag != Match_InvalidOperand)\n";
2886 OS << " RetCode = Diag;\n";
2888 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2889 OS << " OperandsValid = false;\n";
2893 OS << " if (!OperandsValid) continue;\n";
2895 // Emit check that the required features are available.
2896 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2897 << "!= it->RequiredFeatures) {\n";
2898 OS << " HadMatchOtherThanFeatures = true;\n";
2899 OS << " unsigned NewMissingFeatures = it->RequiredFeatures & "
2900 "~AvailableFeatures;\n";
2901 OS << " if (CountPopulation_32(NewMissingFeatures) <=\n"
2902 " CountPopulation_32(MissingFeatures))\n";
2903 OS << " MissingFeatures = NewMissingFeatures;\n";
2904 OS << " continue;\n";
2907 OS << " if (matchingInlineAsm) {\n";
2908 OS << " Kind = it->ConvertFn;\n";
2909 OS << " Inst.setOpcode(it->Opcode);\n";
2910 OS << " convertToMapAndConstraints(it->ConvertFn, Operands, "
2911 << "MapAndConstraints);\n";
2912 OS << " return Match_Success;\n";
2914 OS << " // We have selected a definite instruction, convert the parsed\n"
2915 << " // operands into the appropriate MCInst.\n";
2916 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
2919 // Verify the instruction with the target-specific match predicate function.
2920 OS << " // We have a potential match. Check the target predicate to\n"
2921 << " // handle any context sensitive constraints.\n"
2922 << " unsigned MatchResult;\n"
2923 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
2924 << " Match_Success) {\n"
2925 << " Inst.clear();\n"
2926 << " RetCode = MatchResult;\n"
2927 << " HadMatchOtherThanPredicate = true;\n"
2931 // Call the post-processing function, if used.
2932 std::string InsnCleanupFn =
2933 AsmParser->getValueAsString("AsmParserInstCleanup");
2934 if (!InsnCleanupFn.empty())
2935 OS << " " << InsnCleanupFn << "(Inst);\n";
2937 OS << " return Match_Success;\n";
2940 OS << " // Okay, we had no match. Try to return a useful error code.\n";
2941 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
2942 OS << " return RetCode;\n\n";
2943 OS << " // Missing feature matches return which features were missing\n";
2944 OS << " ErrorInfo = MissingFeatures;\n";
2945 OS << " return Match_MissingFeature;\n";
2948 if (Info.OperandMatchInfo.size())
2949 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
2952 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
2957 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
2958 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
2959 AsmMatcherEmitter(RK).run(OS);
2962 } // End llvm namespace