1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "StringToOffsetTable.h"
101 #include "llvm/ADT/OwningPtr.h"
102 #include "llvm/ADT/PointerUnion.h"
103 #include "llvm/ADT/STLExtras.h"
104 #include "llvm/ADT/SmallPtrSet.h"
105 #include "llvm/ADT/SmallVector.h"
106 #include "llvm/ADT/StringExtras.h"
107 #include "llvm/Support/CommandLine.h"
108 #include "llvm/Support/Debug.h"
109 #include "llvm/Support/ErrorHandling.h"
110 #include "llvm/TableGen/Error.h"
111 #include "llvm/TableGen/Record.h"
112 #include "llvm/TableGen/StringMatcher.h"
113 #include "llvm/TableGen/TableGenBackend.h"
118 using namespace llvm;
120 static cl::opt<std::string>
121 MatchPrefix("match-prefix", cl::init(""),
122 cl::desc("Only match instructions with the given prefix"));
125 class AsmMatcherInfo;
126 struct SubtargetFeatureInfo;
128 class AsmMatcherEmitter {
129 RecordKeeper &Records;
131 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
133 void run(raw_ostream &o);
136 /// ClassInfo - Helper class for storing the information about a particular
137 /// class of operands which can be matched.
140 /// Invalid kind, for use as a sentinel value.
143 /// The class for a particular token.
146 /// The (first) register class, subsequent register classes are
147 /// RegisterClass0+1, and so on.
150 /// The (first) user defined class, subsequent user defined classes are
151 /// UserClass0+1, and so on.
155 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
156 /// N) for the Nth user defined class.
159 /// SuperClasses - The super classes of this class. Note that for simplicities
160 /// sake user operands only record their immediate super class, while register
161 /// operands include all superclasses.
162 std::vector<ClassInfo*> SuperClasses;
164 /// Name - The full class name, suitable for use in an enum.
167 /// ClassName - The unadorned generic name for this class (e.g., Token).
168 std::string ClassName;
170 /// ValueName - The name of the value this class represents; for a token this
171 /// is the literal token string, for an operand it is the TableGen class (or
172 /// empty if this is a derived class).
173 std::string ValueName;
175 /// PredicateMethod - The name of the operand method to test whether the
176 /// operand matches this class; this is not valid for Token or register kinds.
177 std::string PredicateMethod;
179 /// RenderMethod - The name of the operand method to add this operand to an
180 /// MCInst; this is not valid for Token or register kinds.
181 std::string RenderMethod;
183 /// ParserMethod - The name of the operand method to do a target specific
184 /// parsing on the operand.
185 std::string ParserMethod;
187 /// For register classes, the records for all the registers in this class.
188 std::set<Record*> Registers;
190 /// For custom match classes, he diagnostic kind for when the predicate fails.
191 std::string DiagnosticType;
193 /// isRegisterClass() - Check if this is a register class.
194 bool isRegisterClass() const {
195 return Kind >= RegisterClass0 && Kind < UserClass0;
198 /// isUserClass() - Check if this is a user defined class.
199 bool isUserClass() const {
200 return Kind >= UserClass0;
203 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
204 /// are related if they are in the same class hierarchy.
205 bool isRelatedTo(const ClassInfo &RHS) const {
206 // Tokens are only related to tokens.
207 if (Kind == Token || RHS.Kind == Token)
208 return Kind == Token && RHS.Kind == Token;
210 // Registers classes are only related to registers classes, and only if
211 // their intersection is non-empty.
212 if (isRegisterClass() || RHS.isRegisterClass()) {
213 if (!isRegisterClass() || !RHS.isRegisterClass())
216 std::set<Record*> Tmp;
217 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
218 std::set_intersection(Registers.begin(), Registers.end(),
219 RHS.Registers.begin(), RHS.Registers.end(),
225 // Otherwise we have two users operands; they are related if they are in the
226 // same class hierarchy.
228 // FIXME: This is an oversimplification, they should only be related if they
229 // intersect, however we don't have that information.
230 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
231 const ClassInfo *Root = this;
232 while (!Root->SuperClasses.empty())
233 Root = Root->SuperClasses.front();
235 const ClassInfo *RHSRoot = &RHS;
236 while (!RHSRoot->SuperClasses.empty())
237 RHSRoot = RHSRoot->SuperClasses.front();
239 return Root == RHSRoot;
242 /// isSubsetOf - Test whether this class is a subset of \p RHS.
243 bool isSubsetOf(const ClassInfo &RHS) const {
244 // This is a subset of RHS if it is the same class...
248 // ... or if any of its super classes are a subset of RHS.
249 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
250 ie = SuperClasses.end(); it != ie; ++it)
251 if ((*it)->isSubsetOf(RHS))
257 /// operator< - Compare two classes.
258 bool operator<(const ClassInfo &RHS) const {
262 // Unrelated classes can be ordered by kind.
263 if (!isRelatedTo(RHS))
264 return Kind < RHS.Kind;
268 llvm_unreachable("Invalid kind!");
271 // This class precedes the RHS if it is a proper subset of the RHS.
274 if (RHS.isSubsetOf(*this))
277 // Otherwise, order by name to ensure we have a total ordering.
278 return ValueName < RHS.ValueName;
284 /// Sort ClassInfo pointers independently of pointer value.
285 struct LessClassInfoPtr {
286 bool operator()(const ClassInfo *LHS, const ClassInfo *RHS) const {
292 /// MatchableInfo - Helper class for storing the necessary information for an
293 /// instruction or alias which is capable of being matched.
294 struct MatchableInfo {
296 /// Token - This is the token that the operand came from.
299 /// The unique class instance this operand should match.
302 /// The operand name this is, if anything.
305 /// The suboperand index within SrcOpName, or -1 for the entire operand.
308 /// Register record if this token is singleton register.
309 Record *SingletonReg;
311 explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1),
315 /// ResOperand - This represents a single operand in the result instruction
316 /// generated by the match. In cases (like addressing modes) where a single
317 /// assembler operand expands to multiple MCOperands, this represents the
318 /// single assembler operand, not the MCOperand.
321 /// RenderAsmOperand - This represents an operand result that is
322 /// generated by calling the render method on the assembly operand. The
323 /// corresponding AsmOperand is specified by AsmOperandNum.
326 /// TiedOperand - This represents a result operand that is a duplicate of
327 /// a previous result operand.
330 /// ImmOperand - This represents an immediate value that is dumped into
334 /// RegOperand - This represents a fixed register that is dumped in.
339 /// This is the operand # in the AsmOperands list that this should be
341 unsigned AsmOperandNum;
343 /// TiedOperandNum - This is the (earlier) result operand that should be
345 unsigned TiedOperandNum;
347 /// ImmVal - This is the immediate value added to the instruction.
350 /// Register - This is the register record.
354 /// MINumOperands - The number of MCInst operands populated by this
356 unsigned MINumOperands;
358 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
360 X.Kind = RenderAsmOperand;
361 X.AsmOperandNum = AsmOpNum;
362 X.MINumOperands = NumOperands;
366 static ResOperand getTiedOp(unsigned TiedOperandNum) {
368 X.Kind = TiedOperand;
369 X.TiedOperandNum = TiedOperandNum;
374 static ResOperand getImmOp(int64_t Val) {
382 static ResOperand getRegOp(Record *Reg) {
391 /// AsmVariantID - Target's assembly syntax variant no.
394 /// TheDef - This is the definition of the instruction or InstAlias that this
395 /// matchable came from.
396 Record *const TheDef;
398 /// DefRec - This is the definition that it came from.
399 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
401 const CodeGenInstruction *getResultInst() const {
402 if (DefRec.is<const CodeGenInstruction*>())
403 return DefRec.get<const CodeGenInstruction*>();
404 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
407 /// ResOperands - This is the operand list that should be built for the result
409 SmallVector<ResOperand, 8> ResOperands;
411 /// AsmString - The assembly string for this instruction (with variants
412 /// removed), e.g. "movsx $src, $dst".
413 std::string AsmString;
415 /// Mnemonic - This is the first token of the matched instruction, its
419 /// AsmOperands - The textual operands that this instruction matches,
420 /// annotated with a class and where in the OperandList they were defined.
421 /// This directly corresponds to the tokenized AsmString after the mnemonic is
423 SmallVector<AsmOperand, 8> AsmOperands;
425 /// Predicates - The required subtarget features to match this instruction.
426 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
428 /// ConversionFnKind - The enum value which is passed to the generated
429 /// convertToMCInst to convert parsed operands into an MCInst for this
431 std::string ConversionFnKind;
433 MatchableInfo(const CodeGenInstruction &CGI)
434 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI),
435 AsmString(CGI.AsmString) {
438 MatchableInfo(const CodeGenInstAlias *Alias)
439 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias),
440 AsmString(Alias->AsmString) {
443 // Two-operand aliases clone from the main matchable, but mark the second
444 // operand as a tied operand of the first for purposes of the assembler.
445 void formTwoOperandAlias(StringRef Constraint);
447 void initialize(const AsmMatcherInfo &Info,
448 SmallPtrSet<Record*, 16> &SingletonRegisters,
449 int AsmVariantNo, std::string &RegisterPrefix);
451 /// validate - Return true if this matchable is a valid thing to match against
452 /// and perform a bunch of validity checking.
453 bool validate(StringRef CommentDelimiter, bool Hack) const;
455 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
456 /// if present, from specified token.
458 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info,
459 std::string &RegisterPrefix);
461 /// findAsmOperand - Find the AsmOperand with the specified name and
462 /// suboperand index.
463 int findAsmOperand(StringRef N, int SubOpIdx) const {
464 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
465 if (N == AsmOperands[i].SrcOpName &&
466 SubOpIdx == AsmOperands[i].SubOpIdx)
471 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
472 /// This does not check the suboperand index.
473 int findAsmOperandNamed(StringRef N) const {
474 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
475 if (N == AsmOperands[i].SrcOpName)
480 void buildInstructionResultOperands();
481 void buildAliasResultOperands();
483 /// operator< - Compare two matchables.
484 bool operator<(const MatchableInfo &RHS) const {
485 // The primary comparator is the instruction mnemonic.
486 if (Mnemonic != RHS.Mnemonic)
487 return Mnemonic < RHS.Mnemonic;
489 if (AsmOperands.size() != RHS.AsmOperands.size())
490 return AsmOperands.size() < RHS.AsmOperands.size();
492 // Compare lexicographically by operand. The matcher validates that other
493 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
494 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
495 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
497 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
501 // Give matches that require more features higher precedence. This is useful
502 // because we cannot define AssemblerPredicates with the negation of
503 // processor features. For example, ARM v6 "nop" may be either a HINT or
504 // MOV. With v6, we want to match HINT. The assembler has no way to
505 // predicate MOV under "NoV6", but HINT will always match first because it
506 // requires V6 while MOV does not.
507 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
508 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
513 /// couldMatchAmbiguouslyWith - Check whether this matchable could
514 /// ambiguously match the same set of operands as \p RHS (without being a
515 /// strictly superior match).
516 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) {
517 // The primary comparator is the instruction mnemonic.
518 if (Mnemonic != RHS.Mnemonic)
521 // The number of operands is unambiguous.
522 if (AsmOperands.size() != RHS.AsmOperands.size())
525 // Otherwise, make sure the ordering of the two instructions is unambiguous
526 // by checking that either (a) a token or operand kind discriminates them,
527 // or (b) the ordering among equivalent kinds is consistent.
529 // Tokens and operand kinds are unambiguous (assuming a correct target
531 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
532 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
533 AsmOperands[i].Class->Kind == ClassInfo::Token)
534 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
535 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
538 // Otherwise, this operand could commute if all operands are equivalent, or
539 // there is a pair of operands that compare less than and a pair that
540 // compare greater than.
541 bool HasLT = false, HasGT = false;
542 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
543 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
545 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
549 return !(HasLT ^ HasGT);
555 void tokenizeAsmString(const AsmMatcherInfo &Info);
558 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
559 /// feature which participates in instruction matching.
560 struct SubtargetFeatureInfo {
561 /// \brief The predicate record for this feature.
564 /// \brief An unique index assigned to represent this feature.
567 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
569 /// \brief The name of the enumerated constant identifying this feature.
570 std::string getEnumName() const {
571 return "Feature_" + TheDef->getName();
575 struct OperandMatchEntry {
576 unsigned OperandMask;
580 static OperandMatchEntry create(MatchableInfo* mi, ClassInfo *ci,
583 X.OperandMask = opMask;
591 class AsmMatcherInfo {
594 RecordKeeper &Records;
596 /// The tablegen AsmParser record.
599 /// Target - The target information.
600 CodeGenTarget &Target;
602 /// The classes which are needed for matching.
603 std::vector<ClassInfo*> Classes;
605 /// The information on the matchables to match.
606 std::vector<MatchableInfo*> Matchables;
608 /// Info for custom matching operands by user defined methods.
609 std::vector<OperandMatchEntry> OperandMatchInfo;
611 /// Map of Register records to their class information.
612 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
613 RegisterClassesTy RegisterClasses;
615 /// Map of Predicate records to their subtarget information.
616 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
618 /// Map of AsmOperandClass records to their class information.
619 std::map<Record*, ClassInfo*> AsmOperandClasses;
622 /// Map of token to class information which has already been constructed.
623 std::map<std::string, ClassInfo*> TokenClasses;
625 /// Map of RegisterClass records to their class information.
626 std::map<Record*, ClassInfo*> RegisterClassClasses;
629 /// getTokenClass - Lookup or create the class for the given token.
630 ClassInfo *getTokenClass(StringRef Token);
632 /// getOperandClass - Lookup or create the class for the given operand.
633 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
635 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
637 /// buildRegisterClasses - Build the ClassInfo* instances for register
639 void buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
641 /// buildOperandClasses - Build the ClassInfo* instances for user defined
643 void buildOperandClasses();
645 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
647 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
648 MatchableInfo::AsmOperand &Op);
651 AsmMatcherInfo(Record *AsmParser,
652 CodeGenTarget &Target,
653 RecordKeeper &Records);
655 /// buildInfo - Construct the various tables used during matching.
658 /// buildOperandMatchInfo - Build the necessary information to handle user
659 /// defined operand parsing methods.
660 void buildOperandMatchInfo();
662 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
664 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
665 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
666 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
667 SubtargetFeatures.find(Def);
668 return I == SubtargetFeatures.end() ? 0 : I->second;
671 RecordKeeper &getRecords() const {
676 } // End anonymous namespace
678 void MatchableInfo::dump() {
679 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
681 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
682 AsmOperand &Op = AsmOperands[i];
683 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
684 errs() << '\"' << Op.Token << "\"\n";
688 static std::pair<StringRef, StringRef>
689 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
690 // Split via the '='.
691 std::pair<StringRef, StringRef> Ops = S.split('=');
692 if (Ops.second == "")
693 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
694 // Trim whitespace and the leading '$' on the operand names.
695 size_t start = Ops.first.find_first_of('$');
696 if (start == std::string::npos)
697 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
698 Ops.first = Ops.first.slice(start + 1, std::string::npos);
699 size_t end = Ops.first.find_last_of(" \t");
700 Ops.first = Ops.first.slice(0, end);
701 // Now the second operand.
702 start = Ops.second.find_first_of('$');
703 if (start == std::string::npos)
704 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
705 Ops.second = Ops.second.slice(start + 1, std::string::npos);
706 end = Ops.second.find_last_of(" \t");
707 Ops.first = Ops.first.slice(0, end);
711 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
712 // Figure out which operands are aliased and mark them as tied.
713 std::pair<StringRef, StringRef> Ops =
714 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
716 // Find the AsmOperands that refer to the operands we're aliasing.
717 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
718 int DstAsmOperand = findAsmOperandNamed(Ops.second);
719 if (SrcAsmOperand == -1)
720 PrintFatalError(TheDef->getLoc(),
721 "unknown source two-operand alias operand '" +
722 Ops.first.str() + "'.");
723 if (DstAsmOperand == -1)
724 PrintFatalError(TheDef->getLoc(),
725 "unknown destination two-operand alias operand '" +
726 Ops.second.str() + "'.");
728 // Find the ResOperand that refers to the operand we're aliasing away
729 // and update it to refer to the combined operand instead.
730 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
731 ResOperand &Op = ResOperands[i];
732 if (Op.Kind == ResOperand::RenderAsmOperand &&
733 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
734 Op.AsmOperandNum = DstAsmOperand;
738 // Remove the AsmOperand for the alias operand.
739 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
740 // Adjust the ResOperand references to any AsmOperands that followed
741 // the one we just deleted.
742 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
743 ResOperand &Op = ResOperands[i];
746 // Nothing to do for operands that don't reference AsmOperands.
748 case ResOperand::RenderAsmOperand:
749 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
752 case ResOperand::TiedOperand:
753 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
760 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
761 SmallPtrSet<Record*, 16> &SingletonRegisters,
762 int AsmVariantNo, std::string &RegisterPrefix) {
763 AsmVariantID = AsmVariantNo;
765 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
767 tokenizeAsmString(Info);
769 // Compute the require features.
770 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
771 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
772 if (SubtargetFeatureInfo *Feature =
773 Info.getSubtargetFeature(Predicates[i]))
774 RequiredFeatures.push_back(Feature);
776 // Collect singleton registers, if used.
777 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
778 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix);
779 if (Record *Reg = AsmOperands[i].SingletonReg)
780 SingletonRegisters.insert(Reg);
784 /// tokenizeAsmString - Tokenize a simplified assembly string.
785 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
786 StringRef String = AsmString;
789 for (unsigned i = 0, e = String.size(); i != e; ++i) {
799 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
802 if (!isspace(String[i]) && String[i] != ',')
803 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
809 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
813 assert(i != String.size() && "Invalid quoted character");
814 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
820 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
824 // If this isn't "${", treat like a normal token.
825 if (i + 1 == String.size() || String[i + 1] != '{') {
830 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
831 assert(End != String.end() && "Missing brace in operand reference!");
832 size_t EndPos = End - String.begin();
833 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
840 if (!Info.AsmParser->getValueAsBit("MnemonicContainsDot")) {
842 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
852 if (InTok && Prev != String.size())
853 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
855 // The first token of the instruction is the mnemonic, which must be a
856 // simple string, not a $foo variable or a singleton register.
857 if (AsmOperands.empty())
858 PrintFatalError(TheDef->getLoc(),
859 "Instruction '" + TheDef->getName() + "' has no tokens");
860 Mnemonic = AsmOperands[0].Token;
861 if (Mnemonic.empty())
862 PrintFatalError(TheDef->getLoc(),
863 "Missing instruction mnemonic");
864 // FIXME : Check and raise an error if it is a register.
865 if (Mnemonic[0] == '$')
866 PrintFatalError(TheDef->getLoc(),
867 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
869 // Remove the first operand, it is tracked in the mnemonic field.
870 AsmOperands.erase(AsmOperands.begin());
873 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
874 // Reject matchables with no .s string.
875 if (AsmString.empty())
876 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
878 // Reject any matchables with a newline in them, they should be marked
879 // isCodeGenOnly if they are pseudo instructions.
880 if (AsmString.find('\n') != std::string::npos)
881 PrintFatalError(TheDef->getLoc(),
882 "multiline instruction is not valid for the asmparser, "
883 "mark it isCodeGenOnly");
885 // Remove comments from the asm string. We know that the asmstring only
887 if (!CommentDelimiter.empty() &&
888 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
889 PrintFatalError(TheDef->getLoc(),
890 "asmstring for instruction has comment character in it, "
891 "mark it isCodeGenOnly");
893 // Reject matchables with operand modifiers, these aren't something we can
894 // handle, the target should be refactored to use operands instead of
897 // Also, check for instructions which reference the operand multiple times;
898 // this implies a constraint we would not honor.
899 std::set<std::string> OperandNames;
900 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
901 StringRef Tok = AsmOperands[i].Token;
902 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
903 PrintFatalError(TheDef->getLoc(),
904 "matchable with operand modifier '" + Tok.str() +
905 "' not supported by asm matcher. Mark isCodeGenOnly!");
907 // Verify that any operand is only mentioned once.
908 // We reject aliases and ignore instructions for now.
909 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
911 PrintFatalError(TheDef->getLoc(),
912 "ERROR: matchable with tied operand '" + Tok.str() +
913 "' can never be matched!");
914 // FIXME: Should reject these. The ARM backend hits this with $lane in a
915 // bunch of instructions. It is unclear what the right answer is.
917 errs() << "warning: '" << TheDef->getName() << "': "
918 << "ignoring instruction with tied operand '"
919 << Tok.str() << "'\n";
928 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
929 /// if present, from specified token.
931 extractSingletonRegisterForAsmOperand(unsigned OperandNo,
932 const AsmMatcherInfo &Info,
933 std::string &RegisterPrefix) {
934 StringRef Tok = AsmOperands[OperandNo].Token;
935 if (RegisterPrefix.empty()) {
936 std::string LoweredTok = Tok.lower();
937 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
938 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
942 if (!Tok.startswith(RegisterPrefix))
945 StringRef RegName = Tok.substr(RegisterPrefix.size());
946 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
947 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
949 // If there is no register prefix (i.e. "%" in "%eax"), then this may
950 // be some random non-register token, just ignore it.
954 static std::string getEnumNameForToken(StringRef Str) {
957 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
959 case '*': Res += "_STAR_"; break;
960 case '%': Res += "_PCT_"; break;
961 case ':': Res += "_COLON_"; break;
962 case '!': Res += "_EXCLAIM_"; break;
963 case '.': Res += "_DOT_"; break;
964 case '<': Res += "_LT_"; break;
965 case '>': Res += "_GT_"; break;
967 if ((*it >= 'A' && *it <= 'Z') ||
968 (*it >= 'a' && *it <= 'z') ||
969 (*it >= '0' && *it <= '9'))
972 Res += "_" + utostr((unsigned) *it) + "_";
979 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
980 ClassInfo *&Entry = TokenClasses[Token];
983 Entry = new ClassInfo();
984 Entry->Kind = ClassInfo::Token;
985 Entry->ClassName = "Token";
986 Entry->Name = "MCK_" + getEnumNameForToken(Token);
987 Entry->ValueName = Token;
988 Entry->PredicateMethod = "<invalid>";
989 Entry->RenderMethod = "<invalid>";
990 Entry->ParserMethod = "";
991 Entry->DiagnosticType = "";
992 Classes.push_back(Entry);
999 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1001 Record *Rec = OI.Rec;
1003 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1004 return getOperandClass(Rec, SubOpIdx);
1008 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1009 if (Rec->isSubClassOf("RegisterOperand")) {
1010 // RegisterOperand may have an associated ParserMatchClass. If it does,
1011 // use it, else just fall back to the underlying register class.
1012 const RecordVal *R = Rec->getValue("ParserMatchClass");
1013 if (R == 0 || R->getValue() == 0)
1014 PrintFatalError("Record `" + Rec->getName() +
1015 "' does not have a ParserMatchClass!\n");
1017 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1018 Record *MatchClass = DI->getDef();
1019 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1023 // No custom match class. Just use the register class.
1024 Record *ClassRec = Rec->getValueAsDef("RegClass");
1026 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1027 "' has no associated register class!\n");
1028 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1030 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1034 if (Rec->isSubClassOf("RegisterClass")) {
1035 if (ClassInfo *CI = RegisterClassClasses[Rec])
1037 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1040 if (!Rec->isSubClassOf("Operand"))
1041 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1042 "' does not derive from class Operand!\n");
1043 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1044 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1047 PrintFatalError(Rec->getLoc(), "operand has no match class!");
1050 void AsmMatcherInfo::
1051 buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
1052 const std::vector<CodeGenRegister*> &Registers =
1053 Target.getRegBank().getRegisters();
1054 ArrayRef<CodeGenRegisterClass*> RegClassList =
1055 Target.getRegBank().getRegClasses();
1057 // The register sets used for matching.
1058 std::set< std::set<Record*> > RegisterSets;
1060 // Gather the defined sets.
1061 for (ArrayRef<CodeGenRegisterClass*>::const_iterator it =
1062 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
1063 RegisterSets.insert(std::set<Record*>(
1064 (*it)->getOrder().begin(), (*it)->getOrder().end()));
1066 // Add any required singleton sets.
1067 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1068 ie = SingletonRegisters.end(); it != ie; ++it) {
1070 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
1073 // Introduce derived sets where necessary (when a register does not determine
1074 // a unique register set class), and build the mapping of registers to the set
1075 // they should classify to.
1076 std::map<Record*, std::set<Record*> > RegisterMap;
1077 for (std::vector<CodeGenRegister*>::const_iterator it = Registers.begin(),
1078 ie = Registers.end(); it != ie; ++it) {
1079 const CodeGenRegister &CGR = **it;
1080 // Compute the intersection of all sets containing this register.
1081 std::set<Record*> ContainingSet;
1083 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1084 ie = RegisterSets.end(); it != ie; ++it) {
1085 if (!it->count(CGR.TheDef))
1088 if (ContainingSet.empty()) {
1089 ContainingSet = *it;
1093 std::set<Record*> Tmp;
1094 std::swap(Tmp, ContainingSet);
1095 std::insert_iterator< std::set<Record*> > II(ContainingSet,
1096 ContainingSet.begin());
1097 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
1100 if (!ContainingSet.empty()) {
1101 RegisterSets.insert(ContainingSet);
1102 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1106 // Construct the register classes.
1107 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
1109 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1110 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
1111 ClassInfo *CI = new ClassInfo();
1112 CI->Kind = ClassInfo::RegisterClass0 + Index;
1113 CI->ClassName = "Reg" + utostr(Index);
1114 CI->Name = "MCK_Reg" + utostr(Index);
1116 CI->PredicateMethod = ""; // unused
1117 CI->RenderMethod = "addRegOperands";
1118 CI->Registers = *it;
1119 // FIXME: diagnostic type.
1120 CI->DiagnosticType = "";
1121 Classes.push_back(CI);
1122 RegisterSetClasses.insert(std::make_pair(*it, CI));
1125 // Find the superclasses; we could compute only the subgroup lattice edges,
1126 // but there isn't really a point.
1127 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1128 ie = RegisterSets.end(); it != ie; ++it) {
1129 ClassInfo *CI = RegisterSetClasses[*it];
1130 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
1131 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
1133 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
1134 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
1137 // Name the register classes which correspond to a user defined RegisterClass.
1138 for (ArrayRef<CodeGenRegisterClass*>::const_iterator
1139 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
1140 const CodeGenRegisterClass &RC = **it;
1141 // Def will be NULL for non-user defined register classes.
1142 Record *Def = RC.getDef();
1145 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(RC.getOrder().begin(),
1146 RC.getOrder().end())];
1147 if (CI->ValueName.empty()) {
1148 CI->ClassName = RC.getName();
1149 CI->Name = "MCK_" + RC.getName();
1150 CI->ValueName = RC.getName();
1152 CI->ValueName = CI->ValueName + "," + RC.getName();
1154 RegisterClassClasses.insert(std::make_pair(Def, CI));
1157 // Populate the map for individual registers.
1158 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
1159 ie = RegisterMap.end(); it != ie; ++it)
1160 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1162 // Name the register classes which correspond to singleton registers.
1163 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1164 ie = SingletonRegisters.end(); it != ie; ++it) {
1166 ClassInfo *CI = RegisterClasses[Rec];
1167 assert(CI && "Missing singleton register class info!");
1169 if (CI->ValueName.empty()) {
1170 CI->ClassName = Rec->getName();
1171 CI->Name = "MCK_" + Rec->getName();
1172 CI->ValueName = Rec->getName();
1174 CI->ValueName = CI->ValueName + "," + Rec->getName();
1178 void AsmMatcherInfo::buildOperandClasses() {
1179 std::vector<Record*> AsmOperands =
1180 Records.getAllDerivedDefinitions("AsmOperandClass");
1182 // Pre-populate AsmOperandClasses map.
1183 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1184 ie = AsmOperands.end(); it != ie; ++it)
1185 AsmOperandClasses[*it] = new ClassInfo();
1188 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1189 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
1190 ClassInfo *CI = AsmOperandClasses[*it];
1191 CI->Kind = ClassInfo::UserClass0 + Index;
1193 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
1194 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
1195 DefInit *DI = dyn_cast<DefInit>(Supers->getElement(i));
1197 PrintError((*it)->getLoc(), "Invalid super class reference!");
1201 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1203 PrintError((*it)->getLoc(), "Invalid super class reference!");
1205 CI->SuperClasses.push_back(SC);
1207 CI->ClassName = (*it)->getValueAsString("Name");
1208 CI->Name = "MCK_" + CI->ClassName;
1209 CI->ValueName = (*it)->getName();
1211 // Get or construct the predicate method name.
1212 Init *PMName = (*it)->getValueInit("PredicateMethod");
1213 if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1214 CI->PredicateMethod = SI->getValue();
1216 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1217 CI->PredicateMethod = "is" + CI->ClassName;
1220 // Get or construct the render method name.
1221 Init *RMName = (*it)->getValueInit("RenderMethod");
1222 if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1223 CI->RenderMethod = SI->getValue();
1225 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1226 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1229 // Get the parse method name or leave it as empty.
1230 Init *PRMName = (*it)->getValueInit("ParserMethod");
1231 if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1232 CI->ParserMethod = SI->getValue();
1234 // Get the diagnostic type or leave it as empty.
1235 // Get the parse method name or leave it as empty.
1236 Init *DiagnosticType = (*it)->getValueInit("DiagnosticType");
1237 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1238 CI->DiagnosticType = SI->getValue();
1240 AsmOperandClasses[*it] = CI;
1241 Classes.push_back(CI);
1245 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1246 CodeGenTarget &target,
1247 RecordKeeper &records)
1248 : Records(records), AsmParser(asmParser), Target(target) {
1251 /// buildOperandMatchInfo - Build the necessary information to handle user
1252 /// defined operand parsing methods.
1253 void AsmMatcherInfo::buildOperandMatchInfo() {
1255 /// Map containing a mask with all operands indices that can be found for
1256 /// that class inside a instruction.
1257 typedef std::map<ClassInfo*, unsigned, LessClassInfoPtr> OpClassMaskTy;
1258 OpClassMaskTy OpClassMask;
1260 for (std::vector<MatchableInfo*>::const_iterator it =
1261 Matchables.begin(), ie = Matchables.end();
1263 MatchableInfo &II = **it;
1264 OpClassMask.clear();
1266 // Keep track of all operands of this instructions which belong to the
1268 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1269 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1270 if (Op.Class->ParserMethod.empty())
1272 unsigned &OperandMask = OpClassMask[Op.Class];
1273 OperandMask |= (1 << i);
1276 // Generate operand match info for each mnemonic/operand class pair.
1277 for (OpClassMaskTy::iterator iit = OpClassMask.begin(),
1278 iie = OpClassMask.end(); iit != iie; ++iit) {
1279 unsigned OpMask = iit->second;
1280 ClassInfo *CI = iit->first;
1281 OperandMatchInfo.push_back(OperandMatchEntry::create(&II, CI, OpMask));
1286 void AsmMatcherInfo::buildInfo() {
1287 // Build information about all of the AssemblerPredicates.
1288 std::vector<Record*> AllPredicates =
1289 Records.getAllDerivedDefinitions("Predicate");
1290 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1291 Record *Pred = AllPredicates[i];
1292 // Ignore predicates that are not intended for the assembler.
1293 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1296 if (Pred->getName().empty())
1297 PrintFatalError(Pred->getLoc(), "Predicate has no name!");
1299 unsigned FeatureNo = SubtargetFeatures.size();
1300 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1301 assert(FeatureNo < 32 && "Too many subtarget features!");
1304 // Parse the instructions; we need to do this first so that we can gather the
1305 // singleton register classes.
1306 SmallPtrSet<Record*, 16> SingletonRegisters;
1307 unsigned VariantCount = Target.getAsmParserVariantCount();
1308 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1309 Record *AsmVariant = Target.getAsmParserVariant(VC);
1310 std::string CommentDelimiter =
1311 AsmVariant->getValueAsString("CommentDelimiter");
1312 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1313 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1315 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1316 E = Target.inst_end(); I != E; ++I) {
1317 const CodeGenInstruction &CGI = **I;
1319 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1320 // filter the set of instructions we consider.
1321 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1324 // Ignore "codegen only" instructions.
1325 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1328 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1330 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1332 // Ignore instructions which shouldn't be matched and diagnose invalid
1333 // instruction definitions with an error.
1334 if (!II->validate(CommentDelimiter, true))
1337 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1339 // FIXME: This is a total hack.
1340 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1341 StringRef(II->TheDef->getName()).endswith("_Int"))
1344 Matchables.push_back(II.take());
1347 // Parse all of the InstAlias definitions and stick them in the list of
1349 std::vector<Record*> AllInstAliases =
1350 Records.getAllDerivedDefinitions("InstAlias");
1351 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1352 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1354 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1355 // filter the set of instruction aliases we consider, based on the target
1357 if (!StringRef(Alias->ResultInst->TheDef->getName())
1358 .startswith( MatchPrefix))
1361 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1363 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1365 // Validate the alias definitions.
1366 II->validate(CommentDelimiter, false);
1368 Matchables.push_back(II.take());
1372 // Build info for the register classes.
1373 buildRegisterClasses(SingletonRegisters);
1375 // Build info for the user defined assembly operand classes.
1376 buildOperandClasses();
1378 // Build the information about matchables, now that we have fully formed
1380 std::vector<MatchableInfo*> NewMatchables;
1381 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1382 ie = Matchables.end(); it != ie; ++it) {
1383 MatchableInfo *II = *it;
1385 // Parse the tokens after the mnemonic.
1386 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1387 // don't precompute the loop bound.
1388 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1389 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1390 StringRef Token = Op.Token;
1392 // Check for singleton registers.
1393 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1394 Op.Class = RegisterClasses[RegRecord];
1395 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1396 "Unexpected class for singleton register");
1400 // Check for simple tokens.
1401 if (Token[0] != '$') {
1402 Op.Class = getTokenClass(Token);
1406 if (Token.size() > 1 && isdigit(Token[1])) {
1407 Op.Class = getTokenClass(Token);
1411 // Otherwise this is an operand reference.
1412 StringRef OperandName;
1413 if (Token[1] == '{')
1414 OperandName = Token.substr(2, Token.size() - 3);
1416 OperandName = Token.substr(1);
1418 if (II->DefRec.is<const CodeGenInstruction*>())
1419 buildInstructionOperandReference(II, OperandName, i);
1421 buildAliasOperandReference(II, OperandName, Op);
1424 if (II->DefRec.is<const CodeGenInstruction*>()) {
1425 II->buildInstructionResultOperands();
1426 // If the instruction has a two-operand alias, build up the
1427 // matchable here. We'll add them in bulk at the end to avoid
1428 // confusing this loop.
1429 std::string Constraint =
1430 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1431 if (Constraint != "") {
1432 // Start by making a copy of the original matchable.
1433 OwningPtr<MatchableInfo> AliasII(new MatchableInfo(*II));
1435 // Adjust it to be a two-operand alias.
1436 AliasII->formTwoOperandAlias(Constraint);
1438 // Add the alias to the matchables list.
1439 NewMatchables.push_back(AliasII.take());
1442 II->buildAliasResultOperands();
1444 if (!NewMatchables.empty())
1445 Matchables.insert(Matchables.end(), NewMatchables.begin(),
1446 NewMatchables.end());
1448 // Process token alias definitions and set up the associated superclass
1450 std::vector<Record*> AllTokenAliases =
1451 Records.getAllDerivedDefinitions("TokenAlias");
1452 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1453 Record *Rec = AllTokenAliases[i];
1454 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1455 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1456 if (FromClass == ToClass)
1457 PrintFatalError(Rec->getLoc(),
1458 "error: Destination value identical to source value.");
1459 FromClass->SuperClasses.push_back(ToClass);
1462 // Reorder classes so that classes precede super classes.
1463 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1466 /// buildInstructionOperandReference - The specified operand is a reference to a
1467 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1468 void AsmMatcherInfo::
1469 buildInstructionOperandReference(MatchableInfo *II,
1470 StringRef OperandName,
1471 unsigned AsmOpIdx) {
1472 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1473 const CGIOperandList &Operands = CGI.Operands;
1474 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1476 // Map this token to an operand.
1478 if (!Operands.hasOperandNamed(OperandName, Idx))
1479 PrintFatalError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1480 OperandName.str() + "'");
1482 // If the instruction operand has multiple suboperands, but the parser
1483 // match class for the asm operand is still the default "ImmAsmOperand",
1484 // then handle each suboperand separately.
1485 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1486 Record *Rec = Operands[Idx].Rec;
1487 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1488 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1489 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1490 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1491 StringRef Token = Op->Token; // save this in case Op gets moved
1492 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1493 MatchableInfo::AsmOperand NewAsmOp(Token);
1494 NewAsmOp.SubOpIdx = SI;
1495 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1497 // Replace Op with first suboperand.
1498 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1503 // Set up the operand class.
1504 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1506 // If the named operand is tied, canonicalize it to the untied operand.
1507 // For example, something like:
1508 // (outs GPR:$dst), (ins GPR:$src)
1509 // with an asmstring of
1511 // we want to canonicalize to:
1513 // so that we know how to provide the $dst operand when filling in the result.
1515 if (Operands[Idx].MINumOperands == 1)
1516 OITied = Operands[Idx].getTiedRegister();
1518 // The tied operand index is an MIOperand index, find the operand that
1520 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1521 OperandName = Operands[Idx.first].Name;
1522 Op->SubOpIdx = Idx.second;
1525 Op->SrcOpName = OperandName;
1528 /// buildAliasOperandReference - When parsing an operand reference out of the
1529 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1530 /// operand reference is by looking it up in the result pattern definition.
1531 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1532 StringRef OperandName,
1533 MatchableInfo::AsmOperand &Op) {
1534 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1536 // Set up the operand class.
1537 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1538 if (CGA.ResultOperands[i].isRecord() &&
1539 CGA.ResultOperands[i].getName() == OperandName) {
1540 // It's safe to go with the first one we find, because CodeGenInstAlias
1541 // validates that all operands with the same name have the same record.
1542 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1543 // Use the match class from the Alias definition, not the
1544 // destination instruction, as we may have an immediate that's
1545 // being munged by the match class.
1546 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1548 Op.SrcOpName = OperandName;
1552 PrintFatalError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1553 OperandName.str() + "'");
1556 void MatchableInfo::buildInstructionResultOperands() {
1557 const CodeGenInstruction *ResultInst = getResultInst();
1559 // Loop over all operands of the result instruction, determining how to
1561 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1562 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1564 // If this is a tied operand, just copy from the previously handled operand.
1566 if (OpInfo.MINumOperands == 1)
1567 TiedOp = OpInfo.getTiedRegister();
1569 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1573 // Find out what operand from the asmparser this MCInst operand comes from.
1574 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1575 if (OpInfo.Name.empty() || SrcOperand == -1) {
1576 // This may happen for operands that are tied to a suboperand of a
1577 // complex operand. Simply use a dummy value here; nobody should
1578 // use this operand slot.
1579 // FIXME: The long term goal is for the MCOperand list to not contain
1580 // tied operands at all.
1581 ResOperands.push_back(ResOperand::getImmOp(0));
1585 // Check if the one AsmOperand populates the entire operand.
1586 unsigned NumOperands = OpInfo.MINumOperands;
1587 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1588 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1592 // Add a separate ResOperand for each suboperand.
1593 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1594 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1595 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1596 "unexpected AsmOperands for suboperands");
1597 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1602 void MatchableInfo::buildAliasResultOperands() {
1603 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1604 const CodeGenInstruction *ResultInst = getResultInst();
1606 // Loop over all operands of the result instruction, determining how to
1608 unsigned AliasOpNo = 0;
1609 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1610 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1611 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1613 // If this is a tied operand, just copy from the previously handled operand.
1615 if (OpInfo->MINumOperands == 1)
1616 TiedOp = OpInfo->getTiedRegister();
1618 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1622 // Handle all the suboperands for this operand.
1623 const std::string &OpName = OpInfo->Name;
1624 for ( ; AliasOpNo < LastOpNo &&
1625 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1626 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1628 // Find out what operand from the asmparser that this MCInst operand
1630 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1631 case CodeGenInstAlias::ResultOperand::K_Record: {
1632 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1633 int SrcOperand = findAsmOperand(Name, SubIdx);
1634 if (SrcOperand == -1)
1635 PrintFatalError(TheDef->getLoc(), "Instruction '" +
1636 TheDef->getName() + "' has operand '" + OpName +
1637 "' that doesn't appear in asm string!");
1638 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1639 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1643 case CodeGenInstAlias::ResultOperand::K_Imm: {
1644 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1645 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1648 case CodeGenInstAlias::ResultOperand::K_Reg: {
1649 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1650 ResOperands.push_back(ResOperand::getRegOp(Reg));
1658 static unsigned getConverterOperandID(const std::string &Name,
1659 SetVector<std::string> &Table,
1661 IsNew = Table.insert(Name);
1663 unsigned ID = IsNew ? Table.size() - 1 :
1664 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1666 assert(ID < Table.size());
1672 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1673 std::vector<MatchableInfo*> &Infos,
1675 SetVector<std::string> OperandConversionKinds;
1676 SetVector<std::string> InstructionConversionKinds;
1677 std::vector<std::vector<uint8_t> > ConversionTable;
1678 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1680 // TargetOperandClass - This is the target's operand class, like X86Operand.
1681 std::string TargetOperandClass = Target.getName() + "Operand";
1683 // Write the convert function to a separate stream, so we can drop it after
1684 // the enum. We'll build up the conversion handlers for the individual
1685 // operand types opportunistically as we encounter them.
1686 std::string ConvertFnBody;
1687 raw_string_ostream CvtOS(ConvertFnBody);
1688 // Start the unified conversion function.
1689 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1690 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1691 << "unsigned Opcode,\n"
1692 << " const SmallVectorImpl<MCParsedAsmOperand*"
1693 << "> &Operands) {\n"
1694 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1695 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1696 << " Inst.setOpcode(Opcode);\n"
1697 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1698 << " switch (*p) {\n"
1699 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1700 << " case CVT_Reg:\n"
1701 << " static_cast<" << TargetOperandClass
1702 << "*>(Operands[*(p + 1)])->addRegOperands(Inst, 1);\n"
1704 << " case CVT_Tied:\n"
1705 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1708 std::string OperandFnBody;
1709 raw_string_ostream OpOS(OperandFnBody);
1710 // Start the operand number lookup function.
1711 OpOS << "void " << Target.getName() << ClassName << "::\n"
1712 << "convertToMapAndConstraints(unsigned Kind,\n";
1714 OpOS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {\n"
1715 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1716 << " unsigned NumMCOperands = 0;\n"
1717 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1718 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1719 << " switch (*p) {\n"
1720 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1721 << " case CVT_Reg:\n"
1722 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1723 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
1724 << " ++NumMCOperands;\n"
1726 << " case CVT_Tied:\n"
1727 << " ++NumMCOperands;\n"
1730 // Pre-populate the operand conversion kinds with the standard always
1731 // available entries.
1732 OperandConversionKinds.insert("CVT_Done");
1733 OperandConversionKinds.insert("CVT_Reg");
1734 OperandConversionKinds.insert("CVT_Tied");
1735 enum { CVT_Done, CVT_Reg, CVT_Tied };
1737 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1738 ie = Infos.end(); it != ie; ++it) {
1739 MatchableInfo &II = **it;
1741 // Check if we have a custom match function.
1742 std::string AsmMatchConverter =
1743 II.getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1744 if (!AsmMatchConverter.empty()) {
1745 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1746 II.ConversionFnKind = Signature;
1748 // Check if we have already generated this signature.
1749 if (!InstructionConversionKinds.insert(Signature))
1752 // Remember this converter for the kind enum.
1753 unsigned KindID = OperandConversionKinds.size();
1754 OperandConversionKinds.insert("CVT_" +
1755 getEnumNameForToken(AsmMatchConverter));
1757 // Add the converter row for this instruction.
1758 ConversionTable.push_back(std::vector<uint8_t>());
1759 ConversionTable.back().push_back(KindID);
1760 ConversionTable.back().push_back(CVT_Done);
1762 // Add the handler to the conversion driver function.
1763 CvtOS << " case CVT_"
1764 << getEnumNameForToken(AsmMatchConverter) << ":\n"
1765 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1768 // FIXME: Handle the operand number lookup for custom match functions.
1772 // Build the conversion function signature.
1773 std::string Signature = "Convert";
1775 std::vector<uint8_t> ConversionRow;
1777 // Compute the convert enum and the case body.
1778 MaxRowLength = std::max(MaxRowLength, II.ResOperands.size()*2 + 1 );
1780 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1781 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1783 // Generate code to populate each result operand.
1784 switch (OpInfo.Kind) {
1785 case MatchableInfo::ResOperand::RenderAsmOperand: {
1786 // This comes from something we parsed.
1787 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1789 // Registers are always converted the same, don't duplicate the
1790 // conversion function based on them.
1793 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1795 Signature += utostr(OpInfo.MINumOperands);
1796 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1798 // Add the conversion kind, if necessary, and get the associated ID
1799 // the index of its entry in the vector).
1800 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1801 Op.Class->RenderMethod);
1802 Name = getEnumNameForToken(Name);
1804 bool IsNewConverter = false;
1805 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1808 // Add the operand entry to the instruction kind conversion row.
1809 ConversionRow.push_back(ID);
1810 ConversionRow.push_back(OpInfo.AsmOperandNum + 1);
1812 if (!IsNewConverter)
1815 // This is a new operand kind. Add a handler for it to the
1816 // converter driver.
1817 CvtOS << " case " << Name << ":\n"
1818 << " static_cast<" << TargetOperandClass
1819 << "*>(Operands[*(p + 1)])->"
1820 << Op.Class->RenderMethod << "(Inst, " << OpInfo.MINumOperands
1824 // Add a handler for the operand number lookup.
1825 OpOS << " case " << Name << ":\n"
1826 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
1828 if (Op.Class->isRegisterClass())
1829 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
1831 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
1832 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
1836 case MatchableInfo::ResOperand::TiedOperand: {
1837 // If this operand is tied to a previous one, just copy the MCInst
1838 // operand from the earlier one.We can only tie single MCOperand values.
1839 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1840 unsigned TiedOp = OpInfo.TiedOperandNum;
1841 assert(i > TiedOp && "Tied operand precedes its target!");
1842 Signature += "__Tie" + utostr(TiedOp);
1843 ConversionRow.push_back(CVT_Tied);
1844 ConversionRow.push_back(TiedOp);
1847 case MatchableInfo::ResOperand::ImmOperand: {
1848 int64_t Val = OpInfo.ImmVal;
1849 std::string Ty = "imm_" + itostr(Val);
1850 Signature += "__" + Ty;
1852 std::string Name = "CVT_" + Ty;
1853 bool IsNewConverter = false;
1854 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1856 // Add the operand entry to the instruction kind conversion row.
1857 ConversionRow.push_back(ID);
1858 ConversionRow.push_back(0);
1860 if (!IsNewConverter)
1863 CvtOS << " case " << Name << ":\n"
1864 << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"
1867 OpOS << " case " << Name << ":\n"
1868 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1869 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
1870 << " ++NumMCOperands;\n"
1874 case MatchableInfo::ResOperand::RegOperand: {
1875 std::string Reg, Name;
1876 if (OpInfo.Register == 0) {
1880 Reg = getQualifiedName(OpInfo.Register);
1881 Name = "reg" + OpInfo.Register->getName();
1883 Signature += "__" + Name;
1884 Name = "CVT_" + Name;
1885 bool IsNewConverter = false;
1886 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1888 // Add the operand entry to the instruction kind conversion row.
1889 ConversionRow.push_back(ID);
1890 ConversionRow.push_back(0);
1892 if (!IsNewConverter)
1894 CvtOS << " case " << Name << ":\n"
1895 << " Inst.addOperand(MCOperand::CreateReg(" << Reg << "));\n"
1898 OpOS << " case " << Name << ":\n"
1899 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1900 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
1901 << " ++NumMCOperands;\n"
1907 // If there were no operands, add to the signature to that effect
1908 if (Signature == "Convert")
1909 Signature += "_NoOperands";
1911 II.ConversionFnKind = Signature;
1913 // Save the signature. If we already have it, don't add a new row
1915 if (!InstructionConversionKinds.insert(Signature))
1918 // Add the row to the table.
1919 ConversionTable.push_back(ConversionRow);
1922 // Finish up the converter driver function.
1923 CvtOS << " }\n }\n}\n\n";
1925 // Finish up the operand number lookup function.
1926 OpOS << " }\n }\n}\n\n";
1928 OS << "namespace {\n";
1930 // Output the operand conversion kind enum.
1931 OS << "enum OperatorConversionKind {\n";
1932 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i)
1933 OS << " " << OperandConversionKinds[i] << ",\n";
1934 OS << " CVT_NUM_CONVERTERS\n";
1937 // Output the instruction conversion kind enum.
1938 OS << "enum InstructionConversionKind {\n";
1939 for (SetVector<std::string>::const_iterator
1940 i = InstructionConversionKinds.begin(),
1941 e = InstructionConversionKinds.end(); i != e; ++i)
1942 OS << " " << *i << ",\n";
1943 OS << " CVT_NUM_SIGNATURES\n";
1947 OS << "} // end anonymous namespace\n\n";
1949 // Output the conversion table.
1950 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
1951 << MaxRowLength << "] = {\n";
1953 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
1954 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
1955 OS << " // " << InstructionConversionKinds[Row] << "\n";
1957 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
1958 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
1959 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
1960 OS << "CVT_Done },\n";
1965 // Spit out the conversion driver function.
1968 // Spit out the operand number lookup function.
1972 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
1973 static void emitMatchClassEnumeration(CodeGenTarget &Target,
1974 std::vector<ClassInfo*> &Infos,
1976 OS << "namespace {\n\n";
1978 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1979 << "/// instruction matching.\n";
1980 OS << "enum MatchClassKind {\n";
1981 OS << " InvalidMatchClass = 0,\n";
1982 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1983 ie = Infos.end(); it != ie; ++it) {
1984 ClassInfo &CI = **it;
1985 OS << " " << CI.Name << ", // ";
1986 if (CI.Kind == ClassInfo::Token) {
1987 OS << "'" << CI.ValueName << "'\n";
1988 } else if (CI.isRegisterClass()) {
1989 if (!CI.ValueName.empty())
1990 OS << "register class '" << CI.ValueName << "'\n";
1992 OS << "derived register class\n";
1994 OS << "user defined class '" << CI.ValueName << "'\n";
1997 OS << " NumMatchClassKinds\n";
2003 /// emitValidateOperandClass - Emit the function to validate an operand class.
2004 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2006 OS << "static unsigned validateOperandClass(MCParsedAsmOperand *GOp, "
2007 << "MatchClassKind Kind) {\n";
2008 OS << " " << Info.Target.getName() << "Operand &Operand = *("
2009 << Info.Target.getName() << "Operand*)GOp;\n";
2011 // The InvalidMatchClass is not to match any operand.
2012 OS << " if (Kind == InvalidMatchClass)\n";
2013 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2015 // Check for Token operands first.
2016 // FIXME: Use a more specific diagnostic type.
2017 OS << " if (Operand.isToken())\n";
2018 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2019 << " MCTargetAsmParser::Match_Success :\n"
2020 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2022 // Check the user classes. We don't care what order since we're only
2023 // actually matching against one of them.
2024 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
2025 ie = Info.Classes.end(); it != ie; ++it) {
2026 ClassInfo &CI = **it;
2028 if (!CI.isUserClass())
2031 OS << " // '" << CI.ClassName << "' class\n";
2032 OS << " if (Kind == " << CI.Name << ") {\n";
2033 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2034 OS << " return MCTargetAsmParser::Match_Success;\n";
2035 if (!CI.DiagnosticType.empty())
2036 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2037 << CI.DiagnosticType << ";\n";
2041 // Check for register operands, including sub-classes.
2042 OS << " if (Operand.isReg()) {\n";
2043 OS << " MatchClassKind OpKind;\n";
2044 OS << " switch (Operand.getReg()) {\n";
2045 OS << " default: OpKind = InvalidMatchClass; break;\n";
2046 for (AsmMatcherInfo::RegisterClassesTy::iterator
2047 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
2049 OS << " case " << Info.Target.getName() << "::"
2050 << it->first->getName() << ": OpKind = " << it->second->Name
2053 OS << " return isSubclass(OpKind, Kind) ? "
2054 << "MCTargetAsmParser::Match_Success :\n "
2055 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2057 // Generic fallthrough match failure case for operands that don't have
2058 // specialized diagnostic types.
2059 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2063 /// emitIsSubclass - Emit the subclass predicate function.
2064 static void emitIsSubclass(CodeGenTarget &Target,
2065 std::vector<ClassInfo*> &Infos,
2067 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2068 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2069 OS << " if (A == B)\n";
2070 OS << " return true;\n\n";
2073 raw_string_ostream SS(OStr);
2075 SS << " switch (A) {\n";
2076 SS << " default:\n";
2077 SS << " return false;\n";
2078 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2079 ie = Infos.end(); it != ie; ++it) {
2080 ClassInfo &A = **it;
2082 std::vector<StringRef> SuperClasses;
2083 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2084 ie = Infos.end(); it != ie; ++it) {
2085 ClassInfo &B = **it;
2087 if (&A != &B && A.isSubsetOf(B))
2088 SuperClasses.push_back(B.Name);
2091 if (SuperClasses.empty())
2095 SS << "\n case " << A.Name << ":\n";
2097 if (SuperClasses.size() == 1) {
2098 SS << " return B == " << SuperClasses.back().str() << ";\n";
2102 if (!SuperClasses.empty()) {
2103 SS << " switch (B) {\n";
2104 SS << " default: return false;\n";
2105 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
2106 SS << " case " << SuperClasses[i].str() << ": return true;\n";
2109 // No case statement to emit
2110 SS << " return false;\n";
2115 // If there were case statements emitted into the string stream, write them
2116 // to the output stream, otherwise write the default.
2120 OS << " return false;\n";
2125 /// emitMatchTokenString - Emit the function to match a token string to the
2126 /// appropriate match class value.
2127 static void emitMatchTokenString(CodeGenTarget &Target,
2128 std::vector<ClassInfo*> &Infos,
2130 // Construct the match list.
2131 std::vector<StringMatcher::StringPair> Matches;
2132 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2133 ie = Infos.end(); it != ie; ++it) {
2134 ClassInfo &CI = **it;
2136 if (CI.Kind == ClassInfo::Token)
2137 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
2138 "return " + CI.Name + ";"));
2141 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2143 StringMatcher("Name", Matches, OS).Emit();
2145 OS << " return InvalidMatchClass;\n";
2149 /// emitMatchRegisterName - Emit the function to match a string to the target
2150 /// specific register enum.
2151 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2153 // Construct the match list.
2154 std::vector<StringMatcher::StringPair> Matches;
2155 const std::vector<CodeGenRegister*> &Regs =
2156 Target.getRegBank().getRegisters();
2157 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2158 const CodeGenRegister *Reg = Regs[i];
2159 if (Reg->TheDef->getValueAsString("AsmName").empty())
2162 Matches.push_back(StringMatcher::StringPair(
2163 Reg->TheDef->getValueAsString("AsmName"),
2164 "return " + utostr(Reg->EnumValue) + ";"));
2167 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2169 StringMatcher("Name", Matches, OS).Emit();
2171 OS << " return 0;\n";
2175 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2177 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2179 OS << "// Flags for subtarget features that participate in "
2180 << "instruction matching.\n";
2181 OS << "enum SubtargetFeatureFlag {\n";
2182 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2183 it = Info.SubtargetFeatures.begin(),
2184 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2185 SubtargetFeatureInfo &SFI = *it->second;
2186 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
2188 OS << " Feature_None = 0\n";
2192 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2193 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2194 // Get the set of diagnostic types from all of the operand classes.
2195 std::set<StringRef> Types;
2196 for (std::map<Record*, ClassInfo*>::const_iterator
2197 I = Info.AsmOperandClasses.begin(),
2198 E = Info.AsmOperandClasses.end(); I != E; ++I) {
2199 if (!I->second->DiagnosticType.empty())
2200 Types.insert(I->second->DiagnosticType);
2203 if (Types.empty()) return;
2205 // Now emit the enum entries.
2206 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end();
2208 OS << " Match_" << *I << ",\n";
2209 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2212 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2213 /// user-level name for a subtarget feature.
2214 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2215 OS << "// User-level names for subtarget features that participate in\n"
2216 << "// instruction matching.\n"
2217 << "static const char *getSubtargetFeatureName(unsigned Val) {\n";
2218 if (!Info.SubtargetFeatures.empty()) {
2219 OS << " switch(Val) {\n";
2220 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2221 it = Info.SubtargetFeatures.begin(),
2222 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2223 SubtargetFeatureInfo &SFI = *it->second;
2224 // FIXME: Totally just a placeholder name to get the algorithm working.
2225 OS << " case " << SFI.getEnumName() << ": return \""
2226 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2228 OS << " default: return \"(unknown)\";\n";
2231 // Nothing to emit, so skip the switch
2232 OS << " return \"(unknown)\";\n";
2237 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2238 /// available features given a subtarget.
2239 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2241 std::string ClassName =
2242 Info.AsmParser->getValueAsString("AsmParserClassName");
2244 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
2245 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
2246 OS << " unsigned Features = 0;\n";
2247 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2248 it = Info.SubtargetFeatures.begin(),
2249 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2250 SubtargetFeatureInfo &SFI = *it->second;
2253 std::string CondStorage =
2254 SFI.TheDef->getValueAsString("AssemblerCondString");
2255 StringRef Conds = CondStorage;
2256 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2263 StringRef Cond = Comma.first;
2264 if (Cond[0] == '!') {
2266 Cond = Cond.substr(1);
2269 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
2276 if (Comma.second.empty())
2280 Comma = Comma.second.split(',');
2284 OS << " Features |= " << SFI.getEnumName() << ";\n";
2286 OS << " return Features;\n";
2290 static std::string GetAliasRequiredFeatures(Record *R,
2291 const AsmMatcherInfo &Info) {
2292 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2294 unsigned NumFeatures = 0;
2295 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2296 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2299 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2300 "' is not marked as an AssemblerPredicate!");
2305 Result += F->getEnumName();
2309 if (NumFeatures > 1)
2310 Result = '(' + Result + ')';
2314 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2315 std::vector<Record*> &Aliases,
2316 unsigned Indent = 0,
2317 StringRef AsmParserVariantName = StringRef()){
2318 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2319 // iteration order of the map is stable.
2320 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2322 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2323 Record *R = Aliases[i];
2324 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2325 std::string AsmVariantName = R->getValueAsString("AsmVariantName");
2326 if (AsmVariantName != AsmParserVariantName)
2328 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2330 if (AliasesFromMnemonic.empty())
2333 // Process each alias a "from" mnemonic at a time, building the code executed
2334 // by the string remapper.
2335 std::vector<StringMatcher::StringPair> Cases;
2336 for (std::map<std::string, std::vector<Record*> >::iterator
2337 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2339 const std::vector<Record*> &ToVec = I->second;
2341 // Loop through each alias and emit code that handles each case. If there
2342 // are two instructions without predicates, emit an error. If there is one,
2344 std::string MatchCode;
2345 int AliasWithNoPredicate = -1;
2347 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2348 Record *R = ToVec[i];
2349 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2351 // If this unconditionally matches, remember it for later and diagnose
2353 if (FeatureMask.empty()) {
2354 if (AliasWithNoPredicate != -1) {
2355 // We can't have two aliases from the same mnemonic with no predicate.
2356 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2357 "two MnemonicAliases with the same 'from' mnemonic!");
2358 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2361 AliasWithNoPredicate = i;
2364 if (R->getValueAsString("ToMnemonic") == I->first)
2365 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2367 if (!MatchCode.empty())
2368 MatchCode += "else ";
2369 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2370 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2373 if (AliasWithNoPredicate != -1) {
2374 Record *R = ToVec[AliasWithNoPredicate];
2375 if (!MatchCode.empty())
2376 MatchCode += "else\n ";
2377 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2380 MatchCode += "return;";
2382 Cases.push_back(std::make_pair(I->first, MatchCode));
2384 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2387 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2388 /// emit a function for them and return true, otherwise return false.
2389 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2390 CodeGenTarget &Target) {
2391 // Ignore aliases when match-prefix is set.
2392 if (!MatchPrefix.empty())
2395 std::vector<Record*> Aliases =
2396 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2397 if (Aliases.empty()) return false;
2399 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2400 "unsigned Features, unsigned VariantID) {\n";
2401 OS << " switch (VariantID) {\n";
2402 unsigned VariantCount = Target.getAsmParserVariantCount();
2403 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2404 Record *AsmVariant = Target.getAsmParserVariant(VC);
2405 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2406 std::string AsmParserVariantName = AsmVariant->getValueAsString("Name");
2407 OS << " case " << AsmParserVariantNo << ":\n";
2408 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2409 AsmParserVariantName);
2414 // Emit aliases that apply to all variants.
2415 emitMnemonicAliasVariant(OS, Info, Aliases);
2422 static const char *getMinimalTypeForRange(uint64_t Range) {
2423 assert(Range < 0xFFFFFFFFULL && "Enum too large");
2431 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2432 const AsmMatcherInfo &Info, StringRef ClassName,
2433 StringToOffsetTable &StringTable,
2434 unsigned MaxMnemonicIndex) {
2435 unsigned MaxMask = 0;
2436 for (std::vector<OperandMatchEntry>::const_iterator it =
2437 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2439 MaxMask |= it->OperandMask;
2442 // Emit the static custom operand parsing table;
2443 OS << "namespace {\n";
2444 OS << " struct OperandMatchEntry {\n";
2445 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2446 << " RequiredFeatures;\n";
2447 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2449 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2451 OS << " " << getMinimalTypeForRange(MaxMask)
2452 << " OperandMask;\n\n";
2453 OS << " StringRef getMnemonic() const {\n";
2454 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2455 OS << " MnemonicTable[Mnemonic]);\n";
2459 OS << " // Predicate for searching for an opcode.\n";
2460 OS << " struct LessOpcodeOperand {\n";
2461 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2462 OS << " return LHS.getMnemonic() < RHS;\n";
2464 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2465 OS << " return LHS < RHS.getMnemonic();\n";
2467 OS << " bool operator()(const OperandMatchEntry &LHS,";
2468 OS << " const OperandMatchEntry &RHS) {\n";
2469 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2473 OS << "} // end anonymous namespace.\n\n";
2475 OS << "static const OperandMatchEntry OperandMatchTable["
2476 << Info.OperandMatchInfo.size() << "] = {\n";
2478 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2479 for (std::vector<OperandMatchEntry>::const_iterator it =
2480 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2482 const OperandMatchEntry &OMI = *it;
2483 const MatchableInfo &II = *OMI.MI;
2487 // Write the required features mask.
2488 if (!II.RequiredFeatures.empty()) {
2489 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2491 OS << II.RequiredFeatures[i]->getEnumName();
2496 // Store a pascal-style length byte in the mnemonic.
2497 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2498 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2499 << " /* " << II.Mnemonic << " */, ";
2503 OS << ", " << OMI.OperandMask;
2505 bool printComma = false;
2506 for (int i = 0, e = 31; i !=e; ++i)
2507 if (OMI.OperandMask & (1 << i)) {
2519 // Emit the operand class switch to call the correct custom parser for
2520 // the found operand class.
2521 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2522 << Target.getName() << ClassName << "::\n"
2523 << "tryCustomParseOperand(SmallVectorImpl<MCParsedAsmOperand*>"
2524 << " &Operands,\n unsigned MCK) {\n\n"
2525 << " switch(MCK) {\n";
2527 for (std::vector<ClassInfo*>::const_iterator it = Info.Classes.begin(),
2528 ie = Info.Classes.end(); it != ie; ++it) {
2529 ClassInfo *CI = *it;
2530 if (CI->ParserMethod.empty())
2532 OS << " case " << CI->Name << ":\n"
2533 << " return " << CI->ParserMethod << "(Operands);\n";
2536 OS << " default:\n";
2537 OS << " return MatchOperand_NoMatch;\n";
2539 OS << " return MatchOperand_NoMatch;\n";
2542 // Emit the static custom operand parser. This code is very similar with
2543 // the other matcher. Also use MatchResultTy here just in case we go for
2544 // a better error handling.
2545 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2546 << Target.getName() << ClassName << "::\n"
2547 << "MatchOperandParserImpl(SmallVectorImpl<MCParsedAsmOperand*>"
2548 << " &Operands,\n StringRef Mnemonic) {\n";
2550 // Emit code to get the available features.
2551 OS << " // Get the current feature set.\n";
2552 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2554 OS << " // Get the next operand index.\n";
2555 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2557 // Emit code to search the table.
2558 OS << " // Search the table.\n";
2559 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2560 OS << " MnemonicRange =\n";
2561 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2562 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2563 << " LessOpcodeOperand());\n\n";
2565 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2566 OS << " return MatchOperand_NoMatch;\n\n";
2568 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2569 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2571 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2572 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2574 // Emit check that the required features are available.
2575 OS << " // check if the available features match\n";
2576 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2577 << "!= it->RequiredFeatures) {\n";
2578 OS << " continue;\n";
2581 // Emit check to ensure the operand number matches.
2582 OS << " // check if the operand in question has a custom parser.\n";
2583 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2584 OS << " continue;\n\n";
2586 // Emit call to the custom parser method
2587 OS << " // call custom parse method to handle the operand\n";
2588 OS << " OperandMatchResultTy Result = ";
2589 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2590 OS << " if (Result != MatchOperand_NoMatch)\n";
2591 OS << " return Result;\n";
2594 OS << " // Okay, we had no match.\n";
2595 OS << " return MatchOperand_NoMatch;\n";
2599 void AsmMatcherEmitter::run(raw_ostream &OS) {
2600 CodeGenTarget Target(Records);
2601 Record *AsmParser = Target.getAsmParser();
2602 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2604 // Compute the information on the instructions to match.
2605 AsmMatcherInfo Info(AsmParser, Target, Records);
2608 // Sort the instruction table using the partial order on classes. We use
2609 // stable_sort to ensure that ambiguous instructions are still
2610 // deterministically ordered.
2611 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2612 less_ptr<MatchableInfo>());
2614 DEBUG_WITH_TYPE("instruction_info", {
2615 for (std::vector<MatchableInfo*>::iterator
2616 it = Info.Matchables.begin(), ie = Info.Matchables.end();
2621 // Check for ambiguous matchables.
2622 DEBUG_WITH_TYPE("ambiguous_instrs", {
2623 unsigned NumAmbiguous = 0;
2624 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
2625 for (unsigned j = i + 1; j != e; ++j) {
2626 MatchableInfo &A = *Info.Matchables[i];
2627 MatchableInfo &B = *Info.Matchables[j];
2629 if (A.couldMatchAmbiguouslyWith(B)) {
2630 errs() << "warning: ambiguous matchables:\n";
2632 errs() << "\nis incomparable with:\n";
2640 errs() << "warning: " << NumAmbiguous
2641 << " ambiguous matchables!\n";
2644 // Compute the information on the custom operand parsing.
2645 Info.buildOperandMatchInfo();
2647 // Write the output.
2649 // Information for the class declaration.
2650 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2651 OS << "#undef GET_ASSEMBLER_HEADER\n";
2652 OS << " // This should be included into the middle of the declaration of\n";
2653 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2654 OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
2655 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2656 << "unsigned Opcode,\n"
2657 << " const SmallVectorImpl<MCParsedAsmOperand*> "
2659 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2660 OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands);\n";
2661 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);\n";
2662 OS << " unsigned MatchInstructionImpl(\n";
2664 OS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n"
2665 << " MCInst &Inst,\n"
2666 << " unsigned &ErrorInfo,"
2667 << " bool matchingInlineAsm,\n"
2668 << " unsigned VariantID = 0);\n";
2670 if (Info.OperandMatchInfo.size()) {
2671 OS << "\n enum OperandMatchResultTy {\n";
2672 OS << " MatchOperand_Success, // operand matched successfully\n";
2673 OS << " MatchOperand_NoMatch, // operand did not match\n";
2674 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2676 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2677 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2678 OS << " StringRef Mnemonic);\n";
2680 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2681 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2682 OS << " unsigned MCK);\n\n";
2685 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2687 // Emit the operand match diagnostic enum names.
2688 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2689 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2690 emitOperandDiagnosticTypes(Info, OS);
2691 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2694 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2695 OS << "#undef GET_REGISTER_MATCHER\n\n";
2697 // Emit the subtarget feature enumeration.
2698 emitSubtargetFeatureFlagEnumeration(Info, OS);
2700 // Emit the function to match a register name to number.
2701 // This should be omitted for Mips target
2702 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2703 emitMatchRegisterName(Target, AsmParser, OS);
2705 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2707 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2708 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2710 // Generate the helper function to get the names for subtarget features.
2711 emitGetSubtargetFeatureName(Info, OS);
2713 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2715 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2716 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2718 // Generate the function that remaps for mnemonic aliases.
2719 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
2721 // Generate the convertToMCInst function to convert operands into an MCInst.
2722 // Also, generate the convertToMapAndConstraints function for MS-style inline
2723 // assembly. The latter doesn't actually generate a MCInst.
2724 emitConvertFuncs(Target, ClassName, Info.Matchables, OS);
2726 // Emit the enumeration for classes which participate in matching.
2727 emitMatchClassEnumeration(Target, Info.Classes, OS);
2729 // Emit the routine to match token strings to their match class.
2730 emitMatchTokenString(Target, Info.Classes, OS);
2732 // Emit the subclass predicate routine.
2733 emitIsSubclass(Target, Info.Classes, OS);
2735 // Emit the routine to validate an operand against a match class.
2736 emitValidateOperandClass(Info, OS);
2738 // Emit the available features compute function.
2739 emitComputeAvailableFeatures(Info, OS);
2742 StringToOffsetTable StringTable;
2744 size_t MaxNumOperands = 0;
2745 unsigned MaxMnemonicIndex = 0;
2746 for (std::vector<MatchableInfo*>::const_iterator it =
2747 Info.Matchables.begin(), ie = Info.Matchables.end();
2749 MatchableInfo &II = **it;
2750 MaxNumOperands = std::max(MaxNumOperands, II.AsmOperands.size());
2752 // Store a pascal-style length byte in the mnemonic.
2753 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2754 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2755 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2758 OS << "static const char *const MnemonicTable =\n";
2759 StringTable.EmitString(OS);
2762 // Emit the static match table; unused classes get initalized to 0 which is
2763 // guaranteed to be InvalidMatchClass.
2765 // FIXME: We can reduce the size of this table very easily. First, we change
2766 // it so that store the kinds in separate bit-fields for each index, which
2767 // only needs to be the max width used for classes at that index (we also need
2768 // to reject based on this during classification). If we then make sure to
2769 // order the match kinds appropriately (putting mnemonics last), then we
2770 // should only end up using a few bits for each class, especially the ones
2771 // following the mnemonic.
2772 OS << "namespace {\n";
2773 OS << " struct MatchEntry {\n";
2774 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2776 OS << " uint16_t Opcode;\n";
2777 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2779 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2780 << " RequiredFeatures;\n";
2781 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2782 << " Classes[" << MaxNumOperands << "];\n";
2783 OS << " StringRef getMnemonic() const {\n";
2784 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2785 OS << " MnemonicTable[Mnemonic]);\n";
2789 OS << " // Predicate for searching for an opcode.\n";
2790 OS << " struct LessOpcode {\n";
2791 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2792 OS << " return LHS.getMnemonic() < RHS;\n";
2794 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2795 OS << " return LHS < RHS.getMnemonic();\n";
2797 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2798 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2802 OS << "} // end anonymous namespace.\n\n";
2804 unsigned VariantCount = Target.getAsmParserVariantCount();
2805 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2806 Record *AsmVariant = Target.getAsmParserVariant(VC);
2807 std::string CommentDelimiter =
2808 AsmVariant->getValueAsString("CommentDelimiter");
2809 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
2810 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2812 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
2814 for (std::vector<MatchableInfo*>::const_iterator it =
2815 Info.Matchables.begin(), ie = Info.Matchables.end();
2817 MatchableInfo &II = **it;
2818 if (II.AsmVariantID != AsmVariantNo)
2821 // Store a pascal-style length byte in the mnemonic.
2822 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2823 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2824 << " /* " << II.Mnemonic << " */, "
2825 << Target.getName() << "::"
2826 << II.getResultInst()->TheDef->getName() << ", "
2827 << II.ConversionFnKind << ", ";
2829 // Write the required features mask.
2830 if (!II.RequiredFeatures.empty()) {
2831 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2833 OS << II.RequiredFeatures[i]->getEnumName();
2839 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
2840 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
2843 OS << Op.Class->Name;
2851 // A method to determine if a mnemonic is in the list.
2852 OS << "bool " << Target.getName() << ClassName << "::\n"
2853 << "mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {\n";
2854 OS << " // Find the appropriate table for this asm variant.\n";
2855 OS << " const MatchEntry *Start, *End;\n";
2856 OS << " switch (VariantID) {\n";
2857 OS << " default: // unreachable\n";
2858 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2859 Record *AsmVariant = Target.getAsmParserVariant(VC);
2860 std::string CommentDelimiter =
2861 AsmVariant->getValueAsString("CommentDelimiter");
2862 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
2863 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2864 OS << " case " << AsmVariantNo << ": Start = MatchTable" << VC
2865 << "; End = array_endof(MatchTable" << VC << "); break;\n";
2868 OS << " // Search the table.\n";
2869 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2870 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n";
2871 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2874 // Finally, build the match function.
2876 << Target.getName() << ClassName << "::\n"
2877 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
2879 OS << " MCInst &Inst,\n"
2880 << "unsigned &ErrorInfo, bool matchingInlineAsm, unsigned VariantID) {\n";
2882 OS << " // Eliminate obvious mismatches.\n";
2883 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2884 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2885 OS << " return Match_InvalidOperand;\n";
2888 // Emit code to get the available features.
2889 OS << " // Get the current feature set.\n";
2890 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2892 OS << " // Get the instruction mnemonic, which is the first token.\n";
2893 OS << " StringRef Mnemonic = ((" << Target.getName()
2894 << "Operand*)Operands[0])->getToken();\n\n";
2896 if (HasMnemonicAliases) {
2897 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2898 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
2901 // Emit code to compute the class list for this operand vector.
2902 OS << " // Some state to try to produce better error messages.\n";
2903 OS << " bool HadMatchOtherThanFeatures = false;\n";
2904 OS << " bool HadMatchOtherThanPredicate = false;\n";
2905 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2906 OS << " unsigned MissingFeatures = ~0U;\n";
2907 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2908 OS << " // wrong for all instances of the instruction.\n";
2909 OS << " ErrorInfo = ~0U;\n";
2911 // Emit code to search the table.
2912 OS << " // Find the appropriate table for this asm variant.\n";
2913 OS << " const MatchEntry *Start, *End;\n";
2914 OS << " switch (VariantID) {\n";
2915 OS << " default: // unreachable\n";
2916 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2917 Record *AsmVariant = Target.getAsmParserVariant(VC);
2918 std::string CommentDelimiter =
2919 AsmVariant->getValueAsString("CommentDelimiter");
2920 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
2921 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2922 OS << " case " << AsmVariantNo << ": Start = MatchTable" << VC
2923 << "; End = array_endof(MatchTable" << VC << "); break;\n";
2926 OS << " // Search the table.\n";
2927 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2928 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
2930 OS << " // Return a more specific error code if no mnemonics match.\n";
2931 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2932 OS << " return Match_MnemonicFail;\n\n";
2934 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2935 << "*ie = MnemonicRange.second;\n";
2936 OS << " it != ie; ++it) {\n";
2938 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2939 OS << " assert(Mnemonic == it->getMnemonic());\n";
2941 // Emit check that the subclasses match.
2942 OS << " bool OperandsValid = true;\n";
2943 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2944 OS << " if (i + 1 >= Operands.size()) {\n";
2945 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2946 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n";
2949 OS << " unsigned Diag = validateOperandClass(Operands[i+1],\n";
2951 OS << "(MatchClassKind)it->Classes[i]);\n";
2952 OS << " if (Diag == Match_Success)\n";
2953 OS << " continue;\n";
2954 OS << " // If the generic handler indicates an invalid operand\n";
2955 OS << " // failure, check for a special case.\n";
2956 OS << " if (Diag == Match_InvalidOperand) {\n";
2957 OS << " Diag = validateTargetOperandClass(Operands[i+1],\n";
2959 OS << "(MatchClassKind)it->Classes[i]);\n";
2960 OS << " if (Diag == Match_Success)\n";
2961 OS << " continue;\n";
2963 OS << " // If this operand is broken for all of the instances of this\n";
2964 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2965 OS << " // If we already had a match that only failed due to a\n";
2966 OS << " // target predicate, that diagnostic is preferred.\n";
2967 OS << " if (!HadMatchOtherThanPredicate &&\n";
2968 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n";
2969 OS << " ErrorInfo = i+1;\n";
2970 OS << " // InvalidOperand is the default. Prefer specificity.\n";
2971 OS << " if (Diag != Match_InvalidOperand)\n";
2972 OS << " RetCode = Diag;\n";
2974 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2975 OS << " OperandsValid = false;\n";
2979 OS << " if (!OperandsValid) continue;\n";
2981 // Emit check that the required features are available.
2982 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2983 << "!= it->RequiredFeatures) {\n";
2984 OS << " HadMatchOtherThanFeatures = true;\n";
2985 OS << " unsigned NewMissingFeatures = it->RequiredFeatures & "
2986 "~AvailableFeatures;\n";
2987 OS << " if (CountPopulation_32(NewMissingFeatures) <=\n"
2988 " CountPopulation_32(MissingFeatures))\n";
2989 OS << " MissingFeatures = NewMissingFeatures;\n";
2990 OS << " continue;\n";
2993 OS << " if (matchingInlineAsm) {\n";
2994 OS << " Inst.setOpcode(it->Opcode);\n";
2995 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
2996 OS << " return Match_Success;\n";
2998 OS << " // We have selected a definite instruction, convert the parsed\n"
2999 << " // operands into the appropriate MCInst.\n";
3000 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
3003 // Verify the instruction with the target-specific match predicate function.
3004 OS << " // We have a potential match. Check the target predicate to\n"
3005 << " // handle any context sensitive constraints.\n"
3006 << " unsigned MatchResult;\n"
3007 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
3008 << " Match_Success) {\n"
3009 << " Inst.clear();\n"
3010 << " RetCode = MatchResult;\n"
3011 << " HadMatchOtherThanPredicate = true;\n"
3015 // Call the post-processing function, if used.
3016 std::string InsnCleanupFn =
3017 AsmParser->getValueAsString("AsmParserInstCleanup");
3018 if (!InsnCleanupFn.empty())
3019 OS << " " << InsnCleanupFn << "(Inst);\n";
3021 OS << " return Match_Success;\n";
3024 OS << " // Okay, we had no match. Try to return a useful error code.\n";
3025 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
3026 OS << " return RetCode;\n\n";
3027 OS << " // Missing feature matches return which features were missing\n";
3028 OS << " ErrorInfo = MissingFeatures;\n";
3029 OS << " return Match_MissingFeature;\n";
3032 if (Info.OperandMatchInfo.size())
3033 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
3036 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
3041 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
3042 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
3043 AsmMatcherEmitter(RK).run(OS);
3046 } // End llvm namespace