1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "StringToOffsetTable.h"
101 #include "llvm/ADT/OwningPtr.h"
102 #include "llvm/ADT/PointerUnion.h"
103 #include "llvm/ADT/STLExtras.h"
104 #include "llvm/ADT/SmallPtrSet.h"
105 #include "llvm/ADT/SmallVector.h"
106 #include "llvm/ADT/StringExtras.h"
107 #include "llvm/Support/CommandLine.h"
108 #include "llvm/Support/Debug.h"
109 #include "llvm/Support/ErrorHandling.h"
110 #include "llvm/TableGen/Error.h"
111 #include "llvm/TableGen/Record.h"
112 #include "llvm/TableGen/StringMatcher.h"
113 #include "llvm/TableGen/TableGenBackend.h"
118 using namespace llvm;
120 static cl::opt<std::string>
121 MatchPrefix("match-prefix", cl::init(""),
122 cl::desc("Only match instructions with the given prefix"));
125 class AsmMatcherInfo;
126 struct SubtargetFeatureInfo;
128 typedef std::set<Record *, LessRecordByID> RegisterSet;
130 class AsmMatcherEmitter {
131 RecordKeeper &Records;
133 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
135 void run(raw_ostream &o);
138 /// ClassInfo - Helper class for storing the information about a particular
139 /// class of operands which can be matched.
142 /// Invalid kind, for use as a sentinel value.
145 /// The class for a particular token.
148 /// The (first) register class, subsequent register classes are
149 /// RegisterClass0+1, and so on.
152 /// The (first) user defined class, subsequent user defined classes are
153 /// UserClass0+1, and so on.
157 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
158 /// N) for the Nth user defined class.
161 /// SuperClasses - The super classes of this class. Note that for simplicities
162 /// sake user operands only record their immediate super class, while register
163 /// operands include all superclasses.
164 std::vector<ClassInfo*> SuperClasses;
166 /// Name - The full class name, suitable for use in an enum.
169 /// ClassName - The unadorned generic name for this class (e.g., Token).
170 std::string ClassName;
172 /// ValueName - The name of the value this class represents; for a token this
173 /// is the literal token string, for an operand it is the TableGen class (or
174 /// empty if this is a derived class).
175 std::string ValueName;
177 /// PredicateMethod - The name of the operand method to test whether the
178 /// operand matches this class; this is not valid for Token or register kinds.
179 std::string PredicateMethod;
181 /// RenderMethod - The name of the operand method to add this operand to an
182 /// MCInst; this is not valid for Token or register kinds.
183 std::string RenderMethod;
185 /// ParserMethod - The name of the operand method to do a target specific
186 /// parsing on the operand.
187 std::string ParserMethod;
189 /// For register classes, the records for all the registers in this class.
190 RegisterSet Registers;
192 /// For custom match classes, he diagnostic kind for when the predicate fails.
193 std::string DiagnosticType;
195 /// isRegisterClass() - Check if this is a register class.
196 bool isRegisterClass() const {
197 return Kind >= RegisterClass0 && Kind < UserClass0;
200 /// isUserClass() - Check if this is a user defined class.
201 bool isUserClass() const {
202 return Kind >= UserClass0;
205 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
206 /// are related if they are in the same class hierarchy.
207 bool isRelatedTo(const ClassInfo &RHS) const {
208 // Tokens are only related to tokens.
209 if (Kind == Token || RHS.Kind == Token)
210 return Kind == Token && RHS.Kind == Token;
212 // Registers classes are only related to registers classes, and only if
213 // their intersection is non-empty.
214 if (isRegisterClass() || RHS.isRegisterClass()) {
215 if (!isRegisterClass() || !RHS.isRegisterClass())
219 std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin());
220 std::set_intersection(Registers.begin(), Registers.end(),
221 RHS.Registers.begin(), RHS.Registers.end(),
227 // Otherwise we have two users operands; they are related if they are in the
228 // same class hierarchy.
230 // FIXME: This is an oversimplification, they should only be related if they
231 // intersect, however we don't have that information.
232 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
233 const ClassInfo *Root = this;
234 while (!Root->SuperClasses.empty())
235 Root = Root->SuperClasses.front();
237 const ClassInfo *RHSRoot = &RHS;
238 while (!RHSRoot->SuperClasses.empty())
239 RHSRoot = RHSRoot->SuperClasses.front();
241 return Root == RHSRoot;
244 /// isSubsetOf - Test whether this class is a subset of \p RHS.
245 bool isSubsetOf(const ClassInfo &RHS) const {
246 // This is a subset of RHS if it is the same class...
250 // ... or if any of its super classes are a subset of RHS.
251 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
252 ie = SuperClasses.end(); it != ie; ++it)
253 if ((*it)->isSubsetOf(RHS))
259 /// operator< - Compare two classes.
260 bool operator<(const ClassInfo &RHS) const {
264 // Unrelated classes can be ordered by kind.
265 if (!isRelatedTo(RHS))
266 return Kind < RHS.Kind;
270 llvm_unreachable("Invalid kind!");
273 // This class precedes the RHS if it is a proper subset of the RHS.
276 if (RHS.isSubsetOf(*this))
279 // Otherwise, order by name to ensure we have a total ordering.
280 return ValueName < RHS.ValueName;
286 /// Sort ClassInfo pointers independently of pointer value.
287 struct LessClassInfoPtr {
288 bool operator()(const ClassInfo *LHS, const ClassInfo *RHS) const {
294 /// MatchableInfo - Helper class for storing the necessary information for an
295 /// instruction or alias which is capable of being matched.
296 struct MatchableInfo {
298 /// Token - This is the token that the operand came from.
301 /// The unique class instance this operand should match.
304 /// The operand name this is, if anything.
307 /// The suboperand index within SrcOpName, or -1 for the entire operand.
310 /// Register record if this token is singleton register.
311 Record *SingletonReg;
313 explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1),
317 /// ResOperand - This represents a single operand in the result instruction
318 /// generated by the match. In cases (like addressing modes) where a single
319 /// assembler operand expands to multiple MCOperands, this represents the
320 /// single assembler operand, not the MCOperand.
323 /// RenderAsmOperand - This represents an operand result that is
324 /// generated by calling the render method on the assembly operand. The
325 /// corresponding AsmOperand is specified by AsmOperandNum.
328 /// TiedOperand - This represents a result operand that is a duplicate of
329 /// a previous result operand.
332 /// ImmOperand - This represents an immediate value that is dumped into
336 /// RegOperand - This represents a fixed register that is dumped in.
341 /// This is the operand # in the AsmOperands list that this should be
343 unsigned AsmOperandNum;
345 /// TiedOperandNum - This is the (earlier) result operand that should be
347 unsigned TiedOperandNum;
349 /// ImmVal - This is the immediate value added to the instruction.
352 /// Register - This is the register record.
356 /// MINumOperands - The number of MCInst operands populated by this
358 unsigned MINumOperands;
360 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
362 X.Kind = RenderAsmOperand;
363 X.AsmOperandNum = AsmOpNum;
364 X.MINumOperands = NumOperands;
368 static ResOperand getTiedOp(unsigned TiedOperandNum) {
370 X.Kind = TiedOperand;
371 X.TiedOperandNum = TiedOperandNum;
376 static ResOperand getImmOp(int64_t Val) {
384 static ResOperand getRegOp(Record *Reg) {
393 /// AsmVariantID - Target's assembly syntax variant no.
396 /// TheDef - This is the definition of the instruction or InstAlias that this
397 /// matchable came from.
398 Record *const TheDef;
400 /// DefRec - This is the definition that it came from.
401 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
403 const CodeGenInstruction *getResultInst() const {
404 if (DefRec.is<const CodeGenInstruction*>())
405 return DefRec.get<const CodeGenInstruction*>();
406 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
409 /// ResOperands - This is the operand list that should be built for the result
411 SmallVector<ResOperand, 8> ResOperands;
413 /// AsmString - The assembly string for this instruction (with variants
414 /// removed), e.g. "movsx $src, $dst".
415 std::string AsmString;
417 /// Mnemonic - This is the first token of the matched instruction, its
421 /// AsmOperands - The textual operands that this instruction matches,
422 /// annotated with a class and where in the OperandList they were defined.
423 /// This directly corresponds to the tokenized AsmString after the mnemonic is
425 SmallVector<AsmOperand, 8> AsmOperands;
427 /// Predicates - The required subtarget features to match this instruction.
428 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
430 /// ConversionFnKind - The enum value which is passed to the generated
431 /// convertToMCInst to convert parsed operands into an MCInst for this
433 std::string ConversionFnKind;
435 MatchableInfo(const CodeGenInstruction &CGI)
436 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI),
437 AsmString(CGI.AsmString) {
440 MatchableInfo(const CodeGenInstAlias *Alias)
441 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias),
442 AsmString(Alias->AsmString) {
445 // Two-operand aliases clone from the main matchable, but mark the second
446 // operand as a tied operand of the first for purposes of the assembler.
447 void formTwoOperandAlias(StringRef Constraint);
449 void initialize(const AsmMatcherInfo &Info,
450 SmallPtrSet<Record*, 16> &SingletonRegisters,
451 int AsmVariantNo, std::string &RegisterPrefix);
453 /// validate - Return true if this matchable is a valid thing to match against
454 /// and perform a bunch of validity checking.
455 bool validate(StringRef CommentDelimiter, bool Hack) const;
457 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
458 /// if present, from specified token.
460 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info,
461 std::string &RegisterPrefix);
463 /// findAsmOperand - Find the AsmOperand with the specified name and
464 /// suboperand index.
465 int findAsmOperand(StringRef N, int SubOpIdx) const {
466 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
467 if (N == AsmOperands[i].SrcOpName &&
468 SubOpIdx == AsmOperands[i].SubOpIdx)
473 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
474 /// This does not check the suboperand index.
475 int findAsmOperandNamed(StringRef N) const {
476 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
477 if (N == AsmOperands[i].SrcOpName)
482 void buildInstructionResultOperands();
483 void buildAliasResultOperands();
485 /// operator< - Compare two matchables.
486 bool operator<(const MatchableInfo &RHS) const {
487 // The primary comparator is the instruction mnemonic.
488 if (Mnemonic != RHS.Mnemonic)
489 return Mnemonic < RHS.Mnemonic;
491 if (AsmOperands.size() != RHS.AsmOperands.size())
492 return AsmOperands.size() < RHS.AsmOperands.size();
494 // Compare lexicographically by operand. The matcher validates that other
495 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
496 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
497 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
499 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
503 // Give matches that require more features higher precedence. This is useful
504 // because we cannot define AssemblerPredicates with the negation of
505 // processor features. For example, ARM v6 "nop" may be either a HINT or
506 // MOV. With v6, we want to match HINT. The assembler has no way to
507 // predicate MOV under "NoV6", but HINT will always match first because it
508 // requires V6 while MOV does not.
509 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
510 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
515 /// couldMatchAmbiguouslyWith - Check whether this matchable could
516 /// ambiguously match the same set of operands as \p RHS (without being a
517 /// strictly superior match).
518 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) {
519 // The primary comparator is the instruction mnemonic.
520 if (Mnemonic != RHS.Mnemonic)
523 // The number of operands is unambiguous.
524 if (AsmOperands.size() != RHS.AsmOperands.size())
527 // Otherwise, make sure the ordering of the two instructions is unambiguous
528 // by checking that either (a) a token or operand kind discriminates them,
529 // or (b) the ordering among equivalent kinds is consistent.
531 // Tokens and operand kinds are unambiguous (assuming a correct target
533 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
534 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
535 AsmOperands[i].Class->Kind == ClassInfo::Token)
536 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
537 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
540 // Otherwise, this operand could commute if all operands are equivalent, or
541 // there is a pair of operands that compare less than and a pair that
542 // compare greater than.
543 bool HasLT = false, HasGT = false;
544 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
545 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
547 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
551 return !(HasLT ^ HasGT);
557 void tokenizeAsmString(const AsmMatcherInfo &Info);
560 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
561 /// feature which participates in instruction matching.
562 struct SubtargetFeatureInfo {
563 /// \brief The predicate record for this feature.
566 /// \brief An unique index assigned to represent this feature.
569 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
571 /// \brief The name of the enumerated constant identifying this feature.
572 std::string getEnumName() const {
573 return "Feature_" + TheDef->getName();
577 struct OperandMatchEntry {
578 unsigned OperandMask;
582 static OperandMatchEntry create(MatchableInfo* mi, ClassInfo *ci,
585 X.OperandMask = opMask;
593 class AsmMatcherInfo {
596 RecordKeeper &Records;
598 /// The tablegen AsmParser record.
601 /// Target - The target information.
602 CodeGenTarget &Target;
604 /// The classes which are needed for matching.
605 std::vector<ClassInfo*> Classes;
607 /// The information on the matchables to match.
608 std::vector<MatchableInfo*> Matchables;
610 /// Info for custom matching operands by user defined methods.
611 std::vector<OperandMatchEntry> OperandMatchInfo;
613 /// Map of Register records to their class information.
614 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
615 RegisterClassesTy RegisterClasses;
617 /// Map of Predicate records to their subtarget information.
618 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
620 /// Map of AsmOperandClass records to their class information.
621 std::map<Record*, ClassInfo*> AsmOperandClasses;
624 /// Map of token to class information which has already been constructed.
625 std::map<std::string, ClassInfo*> TokenClasses;
627 /// Map of RegisterClass records to their class information.
628 std::map<Record*, ClassInfo*> RegisterClassClasses;
631 /// getTokenClass - Lookup or create the class for the given token.
632 ClassInfo *getTokenClass(StringRef Token);
634 /// getOperandClass - Lookup or create the class for the given operand.
635 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
637 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
639 /// buildRegisterClasses - Build the ClassInfo* instances for register
641 void buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
643 /// buildOperandClasses - Build the ClassInfo* instances for user defined
645 void buildOperandClasses();
647 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
649 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
650 MatchableInfo::AsmOperand &Op);
653 AsmMatcherInfo(Record *AsmParser,
654 CodeGenTarget &Target,
655 RecordKeeper &Records);
657 /// buildInfo - Construct the various tables used during matching.
660 /// buildOperandMatchInfo - Build the necessary information to handle user
661 /// defined operand parsing methods.
662 void buildOperandMatchInfo();
664 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
666 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
667 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
668 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
669 SubtargetFeatures.find(Def);
670 return I == SubtargetFeatures.end() ? 0 : I->second;
673 RecordKeeper &getRecords() const {
678 } // End anonymous namespace
680 void MatchableInfo::dump() {
681 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
683 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
684 AsmOperand &Op = AsmOperands[i];
685 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
686 errs() << '\"' << Op.Token << "\"\n";
690 static std::pair<StringRef, StringRef>
691 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
692 // Split via the '='.
693 std::pair<StringRef, StringRef> Ops = S.split('=');
694 if (Ops.second == "")
695 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
696 // Trim whitespace and the leading '$' on the operand names.
697 size_t start = Ops.first.find_first_of('$');
698 if (start == std::string::npos)
699 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
700 Ops.first = Ops.first.slice(start + 1, std::string::npos);
701 size_t end = Ops.first.find_last_of(" \t");
702 Ops.first = Ops.first.slice(0, end);
703 // Now the second operand.
704 start = Ops.second.find_first_of('$');
705 if (start == std::string::npos)
706 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
707 Ops.second = Ops.second.slice(start + 1, std::string::npos);
708 end = Ops.second.find_last_of(" \t");
709 Ops.first = Ops.first.slice(0, end);
713 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
714 // Figure out which operands are aliased and mark them as tied.
715 std::pair<StringRef, StringRef> Ops =
716 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
718 // Find the AsmOperands that refer to the operands we're aliasing.
719 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
720 int DstAsmOperand = findAsmOperandNamed(Ops.second);
721 if (SrcAsmOperand == -1)
722 PrintFatalError(TheDef->getLoc(),
723 "unknown source two-operand alias operand '" +
724 Ops.first.str() + "'.");
725 if (DstAsmOperand == -1)
726 PrintFatalError(TheDef->getLoc(),
727 "unknown destination two-operand alias operand '" +
728 Ops.second.str() + "'.");
730 // Find the ResOperand that refers to the operand we're aliasing away
731 // and update it to refer to the combined operand instead.
732 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
733 ResOperand &Op = ResOperands[i];
734 if (Op.Kind == ResOperand::RenderAsmOperand &&
735 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
736 Op.AsmOperandNum = DstAsmOperand;
740 // Remove the AsmOperand for the alias operand.
741 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
742 // Adjust the ResOperand references to any AsmOperands that followed
743 // the one we just deleted.
744 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
745 ResOperand &Op = ResOperands[i];
748 // Nothing to do for operands that don't reference AsmOperands.
750 case ResOperand::RenderAsmOperand:
751 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
754 case ResOperand::TiedOperand:
755 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
762 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
763 SmallPtrSet<Record*, 16> &SingletonRegisters,
764 int AsmVariantNo, std::string &RegisterPrefix) {
765 AsmVariantID = AsmVariantNo;
767 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
769 tokenizeAsmString(Info);
771 // Compute the require features.
772 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
773 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
774 if (SubtargetFeatureInfo *Feature =
775 Info.getSubtargetFeature(Predicates[i]))
776 RequiredFeatures.push_back(Feature);
778 // Collect singleton registers, if used.
779 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
780 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix);
781 if (Record *Reg = AsmOperands[i].SingletonReg)
782 SingletonRegisters.insert(Reg);
786 /// tokenizeAsmString - Tokenize a simplified assembly string.
787 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
788 StringRef String = AsmString;
791 for (unsigned i = 0, e = String.size(); i != e; ++i) {
801 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
804 if (!isspace(String[i]) && String[i] != ',')
805 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
811 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
815 assert(i != String.size() && "Invalid quoted character");
816 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
822 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
826 // If this isn't "${", treat like a normal token.
827 if (i + 1 == String.size() || String[i + 1] != '{') {
832 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
833 assert(End != String.end() && "Missing brace in operand reference!");
834 size_t EndPos = End - String.begin();
835 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
842 if (!Info.AsmParser->getValueAsBit("MnemonicContainsDot")) {
844 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
854 if (InTok && Prev != String.size())
855 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
857 // The first token of the instruction is the mnemonic, which must be a
858 // simple string, not a $foo variable or a singleton register.
859 if (AsmOperands.empty())
860 PrintFatalError(TheDef->getLoc(),
861 "Instruction '" + TheDef->getName() + "' has no tokens");
862 Mnemonic = AsmOperands[0].Token;
863 if (Mnemonic.empty())
864 PrintFatalError(TheDef->getLoc(),
865 "Missing instruction mnemonic");
866 // FIXME : Check and raise an error if it is a register.
867 if (Mnemonic[0] == '$')
868 PrintFatalError(TheDef->getLoc(),
869 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
871 // Remove the first operand, it is tracked in the mnemonic field.
872 AsmOperands.erase(AsmOperands.begin());
875 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
876 // Reject matchables with no .s string.
877 if (AsmString.empty())
878 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
880 // Reject any matchables with a newline in them, they should be marked
881 // isCodeGenOnly if they are pseudo instructions.
882 if (AsmString.find('\n') != std::string::npos)
883 PrintFatalError(TheDef->getLoc(),
884 "multiline instruction is not valid for the asmparser, "
885 "mark it isCodeGenOnly");
887 // Remove comments from the asm string. We know that the asmstring only
889 if (!CommentDelimiter.empty() &&
890 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
891 PrintFatalError(TheDef->getLoc(),
892 "asmstring for instruction has comment character in it, "
893 "mark it isCodeGenOnly");
895 // Reject matchables with operand modifiers, these aren't something we can
896 // handle, the target should be refactored to use operands instead of
899 // Also, check for instructions which reference the operand multiple times;
900 // this implies a constraint we would not honor.
901 std::set<std::string> OperandNames;
902 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
903 StringRef Tok = AsmOperands[i].Token;
904 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
905 PrintFatalError(TheDef->getLoc(),
906 "matchable with operand modifier '" + Tok.str() +
907 "' not supported by asm matcher. Mark isCodeGenOnly!");
909 // Verify that any operand is only mentioned once.
910 // We reject aliases and ignore instructions for now.
911 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
913 PrintFatalError(TheDef->getLoc(),
914 "ERROR: matchable with tied operand '" + Tok.str() +
915 "' can never be matched!");
916 // FIXME: Should reject these. The ARM backend hits this with $lane in a
917 // bunch of instructions. It is unclear what the right answer is.
919 errs() << "warning: '" << TheDef->getName() << "': "
920 << "ignoring instruction with tied operand '"
921 << Tok.str() << "'\n";
930 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
931 /// if present, from specified token.
933 extractSingletonRegisterForAsmOperand(unsigned OperandNo,
934 const AsmMatcherInfo &Info,
935 std::string &RegisterPrefix) {
936 StringRef Tok = AsmOperands[OperandNo].Token;
937 if (RegisterPrefix.empty()) {
938 std::string LoweredTok = Tok.lower();
939 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
940 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
944 if (!Tok.startswith(RegisterPrefix))
947 StringRef RegName = Tok.substr(RegisterPrefix.size());
948 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
949 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
951 // If there is no register prefix (i.e. "%" in "%eax"), then this may
952 // be some random non-register token, just ignore it.
956 static std::string getEnumNameForToken(StringRef Str) {
959 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
961 case '*': Res += "_STAR_"; break;
962 case '%': Res += "_PCT_"; break;
963 case ':': Res += "_COLON_"; break;
964 case '!': Res += "_EXCLAIM_"; break;
965 case '.': Res += "_DOT_"; break;
966 case '<': Res += "_LT_"; break;
967 case '>': Res += "_GT_"; break;
969 if ((*it >= 'A' && *it <= 'Z') ||
970 (*it >= 'a' && *it <= 'z') ||
971 (*it >= '0' && *it <= '9'))
974 Res += "_" + utostr((unsigned) *it) + "_";
981 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
982 ClassInfo *&Entry = TokenClasses[Token];
985 Entry = new ClassInfo();
986 Entry->Kind = ClassInfo::Token;
987 Entry->ClassName = "Token";
988 Entry->Name = "MCK_" + getEnumNameForToken(Token);
989 Entry->ValueName = Token;
990 Entry->PredicateMethod = "<invalid>";
991 Entry->RenderMethod = "<invalid>";
992 Entry->ParserMethod = "";
993 Entry->DiagnosticType = "";
994 Classes.push_back(Entry);
1001 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1003 Record *Rec = OI.Rec;
1005 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1006 return getOperandClass(Rec, SubOpIdx);
1010 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1011 if (Rec->isSubClassOf("RegisterOperand")) {
1012 // RegisterOperand may have an associated ParserMatchClass. If it does,
1013 // use it, else just fall back to the underlying register class.
1014 const RecordVal *R = Rec->getValue("ParserMatchClass");
1015 if (R == 0 || R->getValue() == 0)
1016 PrintFatalError("Record `" + Rec->getName() +
1017 "' does not have a ParserMatchClass!\n");
1019 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1020 Record *MatchClass = DI->getDef();
1021 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1025 // No custom match class. Just use the register class.
1026 Record *ClassRec = Rec->getValueAsDef("RegClass");
1028 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1029 "' has no associated register class!\n");
1030 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1032 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1036 if (Rec->isSubClassOf("RegisterClass")) {
1037 if (ClassInfo *CI = RegisterClassClasses[Rec])
1039 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1042 if (!Rec->isSubClassOf("Operand"))
1043 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1044 "' does not derive from class Operand!\n");
1045 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1046 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1049 PrintFatalError(Rec->getLoc(), "operand has no match class!");
1052 void AsmMatcherInfo::
1053 buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
1054 const std::vector<CodeGenRegister*> &Registers =
1055 Target.getRegBank().getRegisters();
1056 ArrayRef<CodeGenRegisterClass*> RegClassList =
1057 Target.getRegBank().getRegClasses();
1059 // The register sets used for matching.
1060 std::set<RegisterSet> RegisterSets;
1062 // Gather the defined sets.
1063 for (ArrayRef<CodeGenRegisterClass*>::const_iterator it =
1064 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
1065 RegisterSets.insert(RegisterSet(
1066 (*it)->getOrder().begin(), (*it)->getOrder().end()));
1068 // Add any required singleton sets.
1069 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1070 ie = SingletonRegisters.end(); it != ie; ++it) {
1072 RegisterSets.insert(RegisterSet(&Rec, &Rec + 1));
1075 // Introduce derived sets where necessary (when a register does not determine
1076 // a unique register set class), and build the mapping of registers to the set
1077 // they should classify to.
1078 std::map<Record*, RegisterSet> RegisterMap;
1079 for (std::vector<CodeGenRegister*>::const_iterator it = Registers.begin(),
1080 ie = Registers.end(); it != ie; ++it) {
1081 const CodeGenRegister &CGR = **it;
1082 // Compute the intersection of all sets containing this register.
1083 RegisterSet ContainingSet;
1085 for (std::set<RegisterSet>::iterator it = RegisterSets.begin(),
1086 ie = RegisterSets.end(); it != ie; ++it) {
1087 if (!it->count(CGR.TheDef))
1090 if (ContainingSet.empty()) {
1091 ContainingSet = *it;
1096 std::swap(Tmp, ContainingSet);
1097 std::insert_iterator<RegisterSet> II(ContainingSet,
1098 ContainingSet.begin());
1099 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
1102 if (!ContainingSet.empty()) {
1103 RegisterSets.insert(ContainingSet);
1104 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1108 // Construct the register classes.
1109 std::map<RegisterSet, ClassInfo*> RegisterSetClasses;
1111 for (std::set<RegisterSet>::iterator it = RegisterSets.begin(),
1112 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
1113 ClassInfo *CI = new ClassInfo();
1114 CI->Kind = ClassInfo::RegisterClass0 + Index;
1115 CI->ClassName = "Reg" + utostr(Index);
1116 CI->Name = "MCK_Reg" + utostr(Index);
1118 CI->PredicateMethod = ""; // unused
1119 CI->RenderMethod = "addRegOperands";
1120 CI->Registers = *it;
1121 // FIXME: diagnostic type.
1122 CI->DiagnosticType = "";
1123 Classes.push_back(CI);
1124 RegisterSetClasses.insert(std::make_pair(*it, CI));
1127 // Find the superclasses; we could compute only the subgroup lattice edges,
1128 // but there isn't really a point.
1129 for (std::set<RegisterSet>::iterator it = RegisterSets.begin(),
1130 ie = RegisterSets.end(); it != ie; ++it) {
1131 ClassInfo *CI = RegisterSetClasses[*it];
1132 for (std::set<RegisterSet>::iterator it2 = RegisterSets.begin(),
1133 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
1135 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
1136 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
1139 // Name the register classes which correspond to a user defined RegisterClass.
1140 for (ArrayRef<CodeGenRegisterClass*>::const_iterator
1141 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
1142 const CodeGenRegisterClass &RC = **it;
1143 // Def will be NULL for non-user defined register classes.
1144 Record *Def = RC.getDef();
1147 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(),
1148 RC.getOrder().end())];
1149 if (CI->ValueName.empty()) {
1150 CI->ClassName = RC.getName();
1151 CI->Name = "MCK_" + RC.getName();
1152 CI->ValueName = RC.getName();
1154 CI->ValueName = CI->ValueName + "," + RC.getName();
1156 RegisterClassClasses.insert(std::make_pair(Def, CI));
1159 // Populate the map for individual registers.
1160 for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(),
1161 ie = RegisterMap.end(); it != ie; ++it)
1162 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1164 // Name the register classes which correspond to singleton registers.
1165 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1166 ie = SingletonRegisters.end(); it != ie; ++it) {
1168 ClassInfo *CI = RegisterClasses[Rec];
1169 assert(CI && "Missing singleton register class info!");
1171 if (CI->ValueName.empty()) {
1172 CI->ClassName = Rec->getName();
1173 CI->Name = "MCK_" + Rec->getName();
1174 CI->ValueName = Rec->getName();
1176 CI->ValueName = CI->ValueName + "," + Rec->getName();
1180 void AsmMatcherInfo::buildOperandClasses() {
1181 std::vector<Record*> AsmOperands =
1182 Records.getAllDerivedDefinitions("AsmOperandClass");
1184 // Pre-populate AsmOperandClasses map.
1185 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1186 ie = AsmOperands.end(); it != ie; ++it)
1187 AsmOperandClasses[*it] = new ClassInfo();
1190 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1191 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
1192 ClassInfo *CI = AsmOperandClasses[*it];
1193 CI->Kind = ClassInfo::UserClass0 + Index;
1195 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
1196 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
1197 DefInit *DI = dyn_cast<DefInit>(Supers->getElement(i));
1199 PrintError((*it)->getLoc(), "Invalid super class reference!");
1203 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1205 PrintError((*it)->getLoc(), "Invalid super class reference!");
1207 CI->SuperClasses.push_back(SC);
1209 CI->ClassName = (*it)->getValueAsString("Name");
1210 CI->Name = "MCK_" + CI->ClassName;
1211 CI->ValueName = (*it)->getName();
1213 // Get or construct the predicate method name.
1214 Init *PMName = (*it)->getValueInit("PredicateMethod");
1215 if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1216 CI->PredicateMethod = SI->getValue();
1218 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1219 CI->PredicateMethod = "is" + CI->ClassName;
1222 // Get or construct the render method name.
1223 Init *RMName = (*it)->getValueInit("RenderMethod");
1224 if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1225 CI->RenderMethod = SI->getValue();
1227 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1228 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1231 // Get the parse method name or leave it as empty.
1232 Init *PRMName = (*it)->getValueInit("ParserMethod");
1233 if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1234 CI->ParserMethod = SI->getValue();
1236 // Get the diagnostic type or leave it as empty.
1237 // Get the parse method name or leave it as empty.
1238 Init *DiagnosticType = (*it)->getValueInit("DiagnosticType");
1239 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1240 CI->DiagnosticType = SI->getValue();
1242 AsmOperandClasses[*it] = CI;
1243 Classes.push_back(CI);
1247 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1248 CodeGenTarget &target,
1249 RecordKeeper &records)
1250 : Records(records), AsmParser(asmParser), Target(target) {
1253 /// buildOperandMatchInfo - Build the necessary information to handle user
1254 /// defined operand parsing methods.
1255 void AsmMatcherInfo::buildOperandMatchInfo() {
1257 /// Map containing a mask with all operands indices that can be found for
1258 /// that class inside a instruction.
1259 typedef std::map<ClassInfo*, unsigned, LessClassInfoPtr> OpClassMaskTy;
1260 OpClassMaskTy OpClassMask;
1262 for (std::vector<MatchableInfo*>::const_iterator it =
1263 Matchables.begin(), ie = Matchables.end();
1265 MatchableInfo &II = **it;
1266 OpClassMask.clear();
1268 // Keep track of all operands of this instructions which belong to the
1270 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1271 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1272 if (Op.Class->ParserMethod.empty())
1274 unsigned &OperandMask = OpClassMask[Op.Class];
1275 OperandMask |= (1 << i);
1278 // Generate operand match info for each mnemonic/operand class pair.
1279 for (OpClassMaskTy::iterator iit = OpClassMask.begin(),
1280 iie = OpClassMask.end(); iit != iie; ++iit) {
1281 unsigned OpMask = iit->second;
1282 ClassInfo *CI = iit->first;
1283 OperandMatchInfo.push_back(OperandMatchEntry::create(&II, CI, OpMask));
1288 void AsmMatcherInfo::buildInfo() {
1289 // Build information about all of the AssemblerPredicates.
1290 std::vector<Record*> AllPredicates =
1291 Records.getAllDerivedDefinitions("Predicate");
1292 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1293 Record *Pred = AllPredicates[i];
1294 // Ignore predicates that are not intended for the assembler.
1295 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1298 if (Pred->getName().empty())
1299 PrintFatalError(Pred->getLoc(), "Predicate has no name!");
1301 unsigned FeatureNo = SubtargetFeatures.size();
1302 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1303 assert(FeatureNo < 32 && "Too many subtarget features!");
1306 // Parse the instructions; we need to do this first so that we can gather the
1307 // singleton register classes.
1308 SmallPtrSet<Record*, 16> SingletonRegisters;
1309 unsigned VariantCount = Target.getAsmParserVariantCount();
1310 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1311 Record *AsmVariant = Target.getAsmParserVariant(VC);
1312 std::string CommentDelimiter =
1313 AsmVariant->getValueAsString("CommentDelimiter");
1314 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1315 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1317 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1318 E = Target.inst_end(); I != E; ++I) {
1319 const CodeGenInstruction &CGI = **I;
1321 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1322 // filter the set of instructions we consider.
1323 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1326 // Ignore "codegen only" instructions.
1327 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1330 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1332 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1334 // Ignore instructions which shouldn't be matched and diagnose invalid
1335 // instruction definitions with an error.
1336 if (!II->validate(CommentDelimiter, true))
1339 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1341 // FIXME: This is a total hack.
1342 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1343 StringRef(II->TheDef->getName()).endswith("_Int"))
1346 Matchables.push_back(II.take());
1349 // Parse all of the InstAlias definitions and stick them in the list of
1351 std::vector<Record*> AllInstAliases =
1352 Records.getAllDerivedDefinitions("InstAlias");
1353 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1354 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1356 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1357 // filter the set of instruction aliases we consider, based on the target
1359 if (!StringRef(Alias->ResultInst->TheDef->getName())
1360 .startswith( MatchPrefix))
1363 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1365 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1367 // Validate the alias definitions.
1368 II->validate(CommentDelimiter, false);
1370 Matchables.push_back(II.take());
1374 // Build info for the register classes.
1375 buildRegisterClasses(SingletonRegisters);
1377 // Build info for the user defined assembly operand classes.
1378 buildOperandClasses();
1380 // Build the information about matchables, now that we have fully formed
1382 std::vector<MatchableInfo*> NewMatchables;
1383 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1384 ie = Matchables.end(); it != ie; ++it) {
1385 MatchableInfo *II = *it;
1387 // Parse the tokens after the mnemonic.
1388 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1389 // don't precompute the loop bound.
1390 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1391 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1392 StringRef Token = Op.Token;
1394 // Check for singleton registers.
1395 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1396 Op.Class = RegisterClasses[RegRecord];
1397 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1398 "Unexpected class for singleton register");
1402 // Check for simple tokens.
1403 if (Token[0] != '$') {
1404 Op.Class = getTokenClass(Token);
1408 if (Token.size() > 1 && isdigit(Token[1])) {
1409 Op.Class = getTokenClass(Token);
1413 // Otherwise this is an operand reference.
1414 StringRef OperandName;
1415 if (Token[1] == '{')
1416 OperandName = Token.substr(2, Token.size() - 3);
1418 OperandName = Token.substr(1);
1420 if (II->DefRec.is<const CodeGenInstruction*>())
1421 buildInstructionOperandReference(II, OperandName, i);
1423 buildAliasOperandReference(II, OperandName, Op);
1426 if (II->DefRec.is<const CodeGenInstruction*>()) {
1427 II->buildInstructionResultOperands();
1428 // If the instruction has a two-operand alias, build up the
1429 // matchable here. We'll add them in bulk at the end to avoid
1430 // confusing this loop.
1431 std::string Constraint =
1432 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1433 if (Constraint != "") {
1434 // Start by making a copy of the original matchable.
1435 OwningPtr<MatchableInfo> AliasII(new MatchableInfo(*II));
1437 // Adjust it to be a two-operand alias.
1438 AliasII->formTwoOperandAlias(Constraint);
1440 // Add the alias to the matchables list.
1441 NewMatchables.push_back(AliasII.take());
1444 II->buildAliasResultOperands();
1446 if (!NewMatchables.empty())
1447 Matchables.insert(Matchables.end(), NewMatchables.begin(),
1448 NewMatchables.end());
1450 // Process token alias definitions and set up the associated superclass
1452 std::vector<Record*> AllTokenAliases =
1453 Records.getAllDerivedDefinitions("TokenAlias");
1454 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1455 Record *Rec = AllTokenAliases[i];
1456 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1457 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1458 if (FromClass == ToClass)
1459 PrintFatalError(Rec->getLoc(),
1460 "error: Destination value identical to source value.");
1461 FromClass->SuperClasses.push_back(ToClass);
1464 // Reorder classes so that classes precede super classes.
1465 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1468 /// buildInstructionOperandReference - The specified operand is a reference to a
1469 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1470 void AsmMatcherInfo::
1471 buildInstructionOperandReference(MatchableInfo *II,
1472 StringRef OperandName,
1473 unsigned AsmOpIdx) {
1474 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1475 const CGIOperandList &Operands = CGI.Operands;
1476 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1478 // Map this token to an operand.
1480 if (!Operands.hasOperandNamed(OperandName, Idx))
1481 PrintFatalError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1482 OperandName.str() + "'");
1484 // If the instruction operand has multiple suboperands, but the parser
1485 // match class for the asm operand is still the default "ImmAsmOperand",
1486 // then handle each suboperand separately.
1487 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1488 Record *Rec = Operands[Idx].Rec;
1489 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1490 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1491 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1492 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1493 StringRef Token = Op->Token; // save this in case Op gets moved
1494 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1495 MatchableInfo::AsmOperand NewAsmOp(Token);
1496 NewAsmOp.SubOpIdx = SI;
1497 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1499 // Replace Op with first suboperand.
1500 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1505 // Set up the operand class.
1506 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1508 // If the named operand is tied, canonicalize it to the untied operand.
1509 // For example, something like:
1510 // (outs GPR:$dst), (ins GPR:$src)
1511 // with an asmstring of
1513 // we want to canonicalize to:
1515 // so that we know how to provide the $dst operand when filling in the result.
1517 if (Operands[Idx].MINumOperands == 1)
1518 OITied = Operands[Idx].getTiedRegister();
1520 // The tied operand index is an MIOperand index, find the operand that
1522 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1523 OperandName = Operands[Idx.first].Name;
1524 Op->SubOpIdx = Idx.second;
1527 Op->SrcOpName = OperandName;
1530 /// buildAliasOperandReference - When parsing an operand reference out of the
1531 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1532 /// operand reference is by looking it up in the result pattern definition.
1533 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1534 StringRef OperandName,
1535 MatchableInfo::AsmOperand &Op) {
1536 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1538 // Set up the operand class.
1539 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1540 if (CGA.ResultOperands[i].isRecord() &&
1541 CGA.ResultOperands[i].getName() == OperandName) {
1542 // It's safe to go with the first one we find, because CodeGenInstAlias
1543 // validates that all operands with the same name have the same record.
1544 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1545 // Use the match class from the Alias definition, not the
1546 // destination instruction, as we may have an immediate that's
1547 // being munged by the match class.
1548 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1550 Op.SrcOpName = OperandName;
1554 PrintFatalError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1555 OperandName.str() + "'");
1558 void MatchableInfo::buildInstructionResultOperands() {
1559 const CodeGenInstruction *ResultInst = getResultInst();
1561 // Loop over all operands of the result instruction, determining how to
1563 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1564 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1566 // If this is a tied operand, just copy from the previously handled operand.
1568 if (OpInfo.MINumOperands == 1)
1569 TiedOp = OpInfo.getTiedRegister();
1571 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1575 // Find out what operand from the asmparser this MCInst operand comes from.
1576 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1577 if (OpInfo.Name.empty() || SrcOperand == -1) {
1578 // This may happen for operands that are tied to a suboperand of a
1579 // complex operand. Simply use a dummy value here; nobody should
1580 // use this operand slot.
1581 // FIXME: The long term goal is for the MCOperand list to not contain
1582 // tied operands at all.
1583 ResOperands.push_back(ResOperand::getImmOp(0));
1587 // Check if the one AsmOperand populates the entire operand.
1588 unsigned NumOperands = OpInfo.MINumOperands;
1589 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1590 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1594 // Add a separate ResOperand for each suboperand.
1595 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1596 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1597 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1598 "unexpected AsmOperands for suboperands");
1599 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1604 void MatchableInfo::buildAliasResultOperands() {
1605 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1606 const CodeGenInstruction *ResultInst = getResultInst();
1608 // Loop over all operands of the result instruction, determining how to
1610 unsigned AliasOpNo = 0;
1611 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1612 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1613 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1615 // If this is a tied operand, just copy from the previously handled operand.
1617 if (OpInfo->MINumOperands == 1)
1618 TiedOp = OpInfo->getTiedRegister();
1620 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1624 // Handle all the suboperands for this operand.
1625 const std::string &OpName = OpInfo->Name;
1626 for ( ; AliasOpNo < LastOpNo &&
1627 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1628 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1630 // Find out what operand from the asmparser that this MCInst operand
1632 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1633 case CodeGenInstAlias::ResultOperand::K_Record: {
1634 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1635 int SrcOperand = findAsmOperand(Name, SubIdx);
1636 if (SrcOperand == -1)
1637 PrintFatalError(TheDef->getLoc(), "Instruction '" +
1638 TheDef->getName() + "' has operand '" + OpName +
1639 "' that doesn't appear in asm string!");
1640 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1641 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1645 case CodeGenInstAlias::ResultOperand::K_Imm: {
1646 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1647 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1650 case CodeGenInstAlias::ResultOperand::K_Reg: {
1651 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1652 ResOperands.push_back(ResOperand::getRegOp(Reg));
1660 static unsigned getConverterOperandID(const std::string &Name,
1661 SetVector<std::string> &Table,
1663 IsNew = Table.insert(Name);
1665 unsigned ID = IsNew ? Table.size() - 1 :
1666 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1668 assert(ID < Table.size());
1674 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1675 std::vector<MatchableInfo*> &Infos,
1677 SetVector<std::string> OperandConversionKinds;
1678 SetVector<std::string> InstructionConversionKinds;
1679 std::vector<std::vector<uint8_t> > ConversionTable;
1680 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1682 // TargetOperandClass - This is the target's operand class, like X86Operand.
1683 std::string TargetOperandClass = Target.getName() + "Operand";
1685 // Write the convert function to a separate stream, so we can drop it after
1686 // the enum. We'll build up the conversion handlers for the individual
1687 // operand types opportunistically as we encounter them.
1688 std::string ConvertFnBody;
1689 raw_string_ostream CvtOS(ConvertFnBody);
1690 // Start the unified conversion function.
1691 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1692 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1693 << "unsigned Opcode,\n"
1694 << " const SmallVectorImpl<MCParsedAsmOperand*"
1695 << "> &Operands) {\n"
1696 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1697 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1698 << " Inst.setOpcode(Opcode);\n"
1699 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1700 << " switch (*p) {\n"
1701 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1702 << " case CVT_Reg:\n"
1703 << " static_cast<" << TargetOperandClass
1704 << "*>(Operands[*(p + 1)])->addRegOperands(Inst, 1);\n"
1706 << " case CVT_Tied:\n"
1707 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1710 std::string OperandFnBody;
1711 raw_string_ostream OpOS(OperandFnBody);
1712 // Start the operand number lookup function.
1713 OpOS << "void " << Target.getName() << ClassName << "::\n"
1714 << "convertToMapAndConstraints(unsigned Kind,\n";
1716 OpOS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {\n"
1717 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1718 << " unsigned NumMCOperands = 0;\n"
1719 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1720 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1721 << " switch (*p) {\n"
1722 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1723 << " case CVT_Reg:\n"
1724 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1725 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
1726 << " ++NumMCOperands;\n"
1728 << " case CVT_Tied:\n"
1729 << " ++NumMCOperands;\n"
1732 // Pre-populate the operand conversion kinds with the standard always
1733 // available entries.
1734 OperandConversionKinds.insert("CVT_Done");
1735 OperandConversionKinds.insert("CVT_Reg");
1736 OperandConversionKinds.insert("CVT_Tied");
1737 enum { CVT_Done, CVT_Reg, CVT_Tied };
1739 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1740 ie = Infos.end(); it != ie; ++it) {
1741 MatchableInfo &II = **it;
1743 // Check if we have a custom match function.
1744 std::string AsmMatchConverter =
1745 II.getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1746 if (!AsmMatchConverter.empty()) {
1747 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1748 II.ConversionFnKind = Signature;
1750 // Check if we have already generated this signature.
1751 if (!InstructionConversionKinds.insert(Signature))
1754 // Remember this converter for the kind enum.
1755 unsigned KindID = OperandConversionKinds.size();
1756 OperandConversionKinds.insert("CVT_" +
1757 getEnumNameForToken(AsmMatchConverter));
1759 // Add the converter row for this instruction.
1760 ConversionTable.push_back(std::vector<uint8_t>());
1761 ConversionTable.back().push_back(KindID);
1762 ConversionTable.back().push_back(CVT_Done);
1764 // Add the handler to the conversion driver function.
1765 CvtOS << " case CVT_"
1766 << getEnumNameForToken(AsmMatchConverter) << ":\n"
1767 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1770 // FIXME: Handle the operand number lookup for custom match functions.
1774 // Build the conversion function signature.
1775 std::string Signature = "Convert";
1777 std::vector<uint8_t> ConversionRow;
1779 // Compute the convert enum and the case body.
1780 MaxRowLength = std::max(MaxRowLength, II.ResOperands.size()*2 + 1 );
1782 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1783 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1785 // Generate code to populate each result operand.
1786 switch (OpInfo.Kind) {
1787 case MatchableInfo::ResOperand::RenderAsmOperand: {
1788 // This comes from something we parsed.
1789 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1791 // Registers are always converted the same, don't duplicate the
1792 // conversion function based on them.
1795 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1797 Signature += utostr(OpInfo.MINumOperands);
1798 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1800 // Add the conversion kind, if necessary, and get the associated ID
1801 // the index of its entry in the vector).
1802 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1803 Op.Class->RenderMethod);
1804 Name = getEnumNameForToken(Name);
1806 bool IsNewConverter = false;
1807 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1810 // Add the operand entry to the instruction kind conversion row.
1811 ConversionRow.push_back(ID);
1812 ConversionRow.push_back(OpInfo.AsmOperandNum + 1);
1814 if (!IsNewConverter)
1817 // This is a new operand kind. Add a handler for it to the
1818 // converter driver.
1819 CvtOS << " case " << Name << ":\n"
1820 << " static_cast<" << TargetOperandClass
1821 << "*>(Operands[*(p + 1)])->"
1822 << Op.Class->RenderMethod << "(Inst, " << OpInfo.MINumOperands
1826 // Add a handler for the operand number lookup.
1827 OpOS << " case " << Name << ":\n"
1828 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
1830 if (Op.Class->isRegisterClass())
1831 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
1833 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
1834 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
1838 case MatchableInfo::ResOperand::TiedOperand: {
1839 // If this operand is tied to a previous one, just copy the MCInst
1840 // operand from the earlier one.We can only tie single MCOperand values.
1841 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1842 unsigned TiedOp = OpInfo.TiedOperandNum;
1843 assert(i > TiedOp && "Tied operand precedes its target!");
1844 Signature += "__Tie" + utostr(TiedOp);
1845 ConversionRow.push_back(CVT_Tied);
1846 ConversionRow.push_back(TiedOp);
1849 case MatchableInfo::ResOperand::ImmOperand: {
1850 int64_t Val = OpInfo.ImmVal;
1851 std::string Ty = "imm_" + itostr(Val);
1852 Signature += "__" + Ty;
1854 std::string Name = "CVT_" + Ty;
1855 bool IsNewConverter = false;
1856 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1858 // Add the operand entry to the instruction kind conversion row.
1859 ConversionRow.push_back(ID);
1860 ConversionRow.push_back(0);
1862 if (!IsNewConverter)
1865 CvtOS << " case " << Name << ":\n"
1866 << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"
1869 OpOS << " case " << Name << ":\n"
1870 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1871 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
1872 << " ++NumMCOperands;\n"
1876 case MatchableInfo::ResOperand::RegOperand: {
1877 std::string Reg, Name;
1878 if (OpInfo.Register == 0) {
1882 Reg = getQualifiedName(OpInfo.Register);
1883 Name = "reg" + OpInfo.Register->getName();
1885 Signature += "__" + Name;
1886 Name = "CVT_" + Name;
1887 bool IsNewConverter = false;
1888 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1890 // Add the operand entry to the instruction kind conversion row.
1891 ConversionRow.push_back(ID);
1892 ConversionRow.push_back(0);
1894 if (!IsNewConverter)
1896 CvtOS << " case " << Name << ":\n"
1897 << " Inst.addOperand(MCOperand::CreateReg(" << Reg << "));\n"
1900 OpOS << " case " << Name << ":\n"
1901 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1902 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
1903 << " ++NumMCOperands;\n"
1909 // If there were no operands, add to the signature to that effect
1910 if (Signature == "Convert")
1911 Signature += "_NoOperands";
1913 II.ConversionFnKind = Signature;
1915 // Save the signature. If we already have it, don't add a new row
1917 if (!InstructionConversionKinds.insert(Signature))
1920 // Add the row to the table.
1921 ConversionTable.push_back(ConversionRow);
1924 // Finish up the converter driver function.
1925 CvtOS << " }\n }\n}\n\n";
1927 // Finish up the operand number lookup function.
1928 OpOS << " }\n }\n}\n\n";
1930 OS << "namespace {\n";
1932 // Output the operand conversion kind enum.
1933 OS << "enum OperatorConversionKind {\n";
1934 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i)
1935 OS << " " << OperandConversionKinds[i] << ",\n";
1936 OS << " CVT_NUM_CONVERTERS\n";
1939 // Output the instruction conversion kind enum.
1940 OS << "enum InstructionConversionKind {\n";
1941 for (SetVector<std::string>::const_iterator
1942 i = InstructionConversionKinds.begin(),
1943 e = InstructionConversionKinds.end(); i != e; ++i)
1944 OS << " " << *i << ",\n";
1945 OS << " CVT_NUM_SIGNATURES\n";
1949 OS << "} // end anonymous namespace\n\n";
1951 // Output the conversion table.
1952 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
1953 << MaxRowLength << "] = {\n";
1955 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
1956 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
1957 OS << " // " << InstructionConversionKinds[Row] << "\n";
1959 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
1960 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
1961 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
1962 OS << "CVT_Done },\n";
1967 // Spit out the conversion driver function.
1970 // Spit out the operand number lookup function.
1974 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
1975 static void emitMatchClassEnumeration(CodeGenTarget &Target,
1976 std::vector<ClassInfo*> &Infos,
1978 OS << "namespace {\n\n";
1980 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1981 << "/// instruction matching.\n";
1982 OS << "enum MatchClassKind {\n";
1983 OS << " InvalidMatchClass = 0,\n";
1984 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1985 ie = Infos.end(); it != ie; ++it) {
1986 ClassInfo &CI = **it;
1987 OS << " " << CI.Name << ", // ";
1988 if (CI.Kind == ClassInfo::Token) {
1989 OS << "'" << CI.ValueName << "'\n";
1990 } else if (CI.isRegisterClass()) {
1991 if (!CI.ValueName.empty())
1992 OS << "register class '" << CI.ValueName << "'\n";
1994 OS << "derived register class\n";
1996 OS << "user defined class '" << CI.ValueName << "'\n";
1999 OS << " NumMatchClassKinds\n";
2005 /// emitValidateOperandClass - Emit the function to validate an operand class.
2006 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2008 OS << "static unsigned validateOperandClass(MCParsedAsmOperand *GOp, "
2009 << "MatchClassKind Kind) {\n";
2010 OS << " " << Info.Target.getName() << "Operand &Operand = *("
2011 << Info.Target.getName() << "Operand*)GOp;\n";
2013 // The InvalidMatchClass is not to match any operand.
2014 OS << " if (Kind == InvalidMatchClass)\n";
2015 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2017 // Check for Token operands first.
2018 // FIXME: Use a more specific diagnostic type.
2019 OS << " if (Operand.isToken())\n";
2020 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2021 << " MCTargetAsmParser::Match_Success :\n"
2022 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2024 // Check the user classes. We don't care what order since we're only
2025 // actually matching against one of them.
2026 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
2027 ie = Info.Classes.end(); it != ie; ++it) {
2028 ClassInfo &CI = **it;
2030 if (!CI.isUserClass())
2033 OS << " // '" << CI.ClassName << "' class\n";
2034 OS << " if (Kind == " << CI.Name << ") {\n";
2035 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2036 OS << " return MCTargetAsmParser::Match_Success;\n";
2037 if (!CI.DiagnosticType.empty())
2038 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2039 << CI.DiagnosticType << ";\n";
2043 // Check for register operands, including sub-classes.
2044 OS << " if (Operand.isReg()) {\n";
2045 OS << " MatchClassKind OpKind;\n";
2046 OS << " switch (Operand.getReg()) {\n";
2047 OS << " default: OpKind = InvalidMatchClass; break;\n";
2048 for (AsmMatcherInfo::RegisterClassesTy::iterator
2049 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
2051 OS << " case " << Info.Target.getName() << "::"
2052 << it->first->getName() << ": OpKind = " << it->second->Name
2055 OS << " return isSubclass(OpKind, Kind) ? "
2056 << "MCTargetAsmParser::Match_Success :\n "
2057 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2059 // Generic fallthrough match failure case for operands that don't have
2060 // specialized diagnostic types.
2061 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2065 /// emitIsSubclass - Emit the subclass predicate function.
2066 static void emitIsSubclass(CodeGenTarget &Target,
2067 std::vector<ClassInfo*> &Infos,
2069 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2070 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2071 OS << " if (A == B)\n";
2072 OS << " return true;\n\n";
2075 raw_string_ostream SS(OStr);
2077 SS << " switch (A) {\n";
2078 SS << " default:\n";
2079 SS << " return false;\n";
2080 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2081 ie = Infos.end(); it != ie; ++it) {
2082 ClassInfo &A = **it;
2084 std::vector<StringRef> SuperClasses;
2085 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2086 ie = Infos.end(); it != ie; ++it) {
2087 ClassInfo &B = **it;
2089 if (&A != &B && A.isSubsetOf(B))
2090 SuperClasses.push_back(B.Name);
2093 if (SuperClasses.empty())
2097 SS << "\n case " << A.Name << ":\n";
2099 if (SuperClasses.size() == 1) {
2100 SS << " return B == " << SuperClasses.back().str() << ";\n";
2104 if (!SuperClasses.empty()) {
2105 SS << " switch (B) {\n";
2106 SS << " default: return false;\n";
2107 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
2108 SS << " case " << SuperClasses[i].str() << ": return true;\n";
2111 // No case statement to emit
2112 SS << " return false;\n";
2117 // If there were case statements emitted into the string stream, write them
2118 // to the output stream, otherwise write the default.
2122 OS << " return false;\n";
2127 /// emitMatchTokenString - Emit the function to match a token string to the
2128 /// appropriate match class value.
2129 static void emitMatchTokenString(CodeGenTarget &Target,
2130 std::vector<ClassInfo*> &Infos,
2132 // Construct the match list.
2133 std::vector<StringMatcher::StringPair> Matches;
2134 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2135 ie = Infos.end(); it != ie; ++it) {
2136 ClassInfo &CI = **it;
2138 if (CI.Kind == ClassInfo::Token)
2139 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
2140 "return " + CI.Name + ";"));
2143 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2145 StringMatcher("Name", Matches, OS).Emit();
2147 OS << " return InvalidMatchClass;\n";
2151 /// emitMatchRegisterName - Emit the function to match a string to the target
2152 /// specific register enum.
2153 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2155 // Construct the match list.
2156 std::vector<StringMatcher::StringPair> Matches;
2157 const std::vector<CodeGenRegister*> &Regs =
2158 Target.getRegBank().getRegisters();
2159 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2160 const CodeGenRegister *Reg = Regs[i];
2161 if (Reg->TheDef->getValueAsString("AsmName").empty())
2164 Matches.push_back(StringMatcher::StringPair(
2165 Reg->TheDef->getValueAsString("AsmName"),
2166 "return " + utostr(Reg->EnumValue) + ";"));
2169 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2171 StringMatcher("Name", Matches, OS).Emit();
2173 OS << " return 0;\n";
2177 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2179 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2181 OS << "// Flags for subtarget features that participate in "
2182 << "instruction matching.\n";
2183 OS << "enum SubtargetFeatureFlag {\n";
2184 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2185 it = Info.SubtargetFeatures.begin(),
2186 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2187 SubtargetFeatureInfo &SFI = *it->second;
2188 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
2190 OS << " Feature_None = 0\n";
2194 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2195 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2196 // Get the set of diagnostic types from all of the operand classes.
2197 std::set<StringRef> Types;
2198 for (std::map<Record*, ClassInfo*>::const_iterator
2199 I = Info.AsmOperandClasses.begin(),
2200 E = Info.AsmOperandClasses.end(); I != E; ++I) {
2201 if (!I->second->DiagnosticType.empty())
2202 Types.insert(I->second->DiagnosticType);
2205 if (Types.empty()) return;
2207 // Now emit the enum entries.
2208 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end();
2210 OS << " Match_" << *I << ",\n";
2211 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2214 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2215 /// user-level name for a subtarget feature.
2216 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2217 OS << "// User-level names for subtarget features that participate in\n"
2218 << "// instruction matching.\n"
2219 << "static const char *getSubtargetFeatureName(unsigned Val) {\n";
2220 if (!Info.SubtargetFeatures.empty()) {
2221 OS << " switch(Val) {\n";
2222 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2223 it = Info.SubtargetFeatures.begin(),
2224 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2225 SubtargetFeatureInfo &SFI = *it->second;
2226 // FIXME: Totally just a placeholder name to get the algorithm working.
2227 OS << " case " << SFI.getEnumName() << ": return \""
2228 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2230 OS << " default: return \"(unknown)\";\n";
2233 // Nothing to emit, so skip the switch
2234 OS << " return \"(unknown)\";\n";
2239 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2240 /// available features given a subtarget.
2241 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2243 std::string ClassName =
2244 Info.AsmParser->getValueAsString("AsmParserClassName");
2246 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
2247 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
2248 OS << " unsigned Features = 0;\n";
2249 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2250 it = Info.SubtargetFeatures.begin(),
2251 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2252 SubtargetFeatureInfo &SFI = *it->second;
2255 std::string CondStorage =
2256 SFI.TheDef->getValueAsString("AssemblerCondString");
2257 StringRef Conds = CondStorage;
2258 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2265 StringRef Cond = Comma.first;
2266 if (Cond[0] == '!') {
2268 Cond = Cond.substr(1);
2271 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
2278 if (Comma.second.empty())
2282 Comma = Comma.second.split(',');
2286 OS << " Features |= " << SFI.getEnumName() << ";\n";
2288 OS << " return Features;\n";
2292 static std::string GetAliasRequiredFeatures(Record *R,
2293 const AsmMatcherInfo &Info) {
2294 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2296 unsigned NumFeatures = 0;
2297 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2298 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2301 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2302 "' is not marked as an AssemblerPredicate!");
2307 Result += F->getEnumName();
2311 if (NumFeatures > 1)
2312 Result = '(' + Result + ')';
2316 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2317 std::vector<Record*> &Aliases,
2318 unsigned Indent = 0,
2319 StringRef AsmParserVariantName = StringRef()){
2320 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2321 // iteration order of the map is stable.
2322 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2324 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2325 Record *R = Aliases[i];
2326 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2327 std::string AsmVariantName = R->getValueAsString("AsmVariantName");
2328 if (AsmVariantName != AsmParserVariantName)
2330 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2332 if (AliasesFromMnemonic.empty())
2335 // Process each alias a "from" mnemonic at a time, building the code executed
2336 // by the string remapper.
2337 std::vector<StringMatcher::StringPair> Cases;
2338 for (std::map<std::string, std::vector<Record*> >::iterator
2339 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2341 const std::vector<Record*> &ToVec = I->second;
2343 // Loop through each alias and emit code that handles each case. If there
2344 // are two instructions without predicates, emit an error. If there is one,
2346 std::string MatchCode;
2347 int AliasWithNoPredicate = -1;
2349 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2350 Record *R = ToVec[i];
2351 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2353 // If this unconditionally matches, remember it for later and diagnose
2355 if (FeatureMask.empty()) {
2356 if (AliasWithNoPredicate != -1) {
2357 // We can't have two aliases from the same mnemonic with no predicate.
2358 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2359 "two MnemonicAliases with the same 'from' mnemonic!");
2360 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2363 AliasWithNoPredicate = i;
2366 if (R->getValueAsString("ToMnemonic") == I->first)
2367 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2369 if (!MatchCode.empty())
2370 MatchCode += "else ";
2371 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2372 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2375 if (AliasWithNoPredicate != -1) {
2376 Record *R = ToVec[AliasWithNoPredicate];
2377 if (!MatchCode.empty())
2378 MatchCode += "else\n ";
2379 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2382 MatchCode += "return;";
2384 Cases.push_back(std::make_pair(I->first, MatchCode));
2386 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2389 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2390 /// emit a function for them and return true, otherwise return false.
2391 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2392 CodeGenTarget &Target) {
2393 // Ignore aliases when match-prefix is set.
2394 if (!MatchPrefix.empty())
2397 std::vector<Record*> Aliases =
2398 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2399 if (Aliases.empty()) return false;
2401 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2402 "unsigned Features, unsigned VariantID) {\n";
2403 OS << " switch (VariantID) {\n";
2404 unsigned VariantCount = Target.getAsmParserVariantCount();
2405 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2406 Record *AsmVariant = Target.getAsmParserVariant(VC);
2407 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2408 std::string AsmParserVariantName = AsmVariant->getValueAsString("Name");
2409 OS << " case " << AsmParserVariantNo << ":\n";
2410 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2411 AsmParserVariantName);
2416 // Emit aliases that apply to all variants.
2417 emitMnemonicAliasVariant(OS, Info, Aliases);
2424 static const char *getMinimalTypeForRange(uint64_t Range) {
2425 assert(Range < 0xFFFFFFFFULL && "Enum too large");
2433 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2434 const AsmMatcherInfo &Info, StringRef ClassName,
2435 StringToOffsetTable &StringTable,
2436 unsigned MaxMnemonicIndex) {
2437 unsigned MaxMask = 0;
2438 for (std::vector<OperandMatchEntry>::const_iterator it =
2439 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2441 MaxMask |= it->OperandMask;
2444 // Emit the static custom operand parsing table;
2445 OS << "namespace {\n";
2446 OS << " struct OperandMatchEntry {\n";
2447 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2448 << " RequiredFeatures;\n";
2449 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2451 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2453 OS << " " << getMinimalTypeForRange(MaxMask)
2454 << " OperandMask;\n\n";
2455 OS << " StringRef getMnemonic() const {\n";
2456 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2457 OS << " MnemonicTable[Mnemonic]);\n";
2461 OS << " // Predicate for searching for an opcode.\n";
2462 OS << " struct LessOpcodeOperand {\n";
2463 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2464 OS << " return LHS.getMnemonic() < RHS;\n";
2466 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2467 OS << " return LHS < RHS.getMnemonic();\n";
2469 OS << " bool operator()(const OperandMatchEntry &LHS,";
2470 OS << " const OperandMatchEntry &RHS) {\n";
2471 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2475 OS << "} // end anonymous namespace.\n\n";
2477 OS << "static const OperandMatchEntry OperandMatchTable["
2478 << Info.OperandMatchInfo.size() << "] = {\n";
2480 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2481 for (std::vector<OperandMatchEntry>::const_iterator it =
2482 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2484 const OperandMatchEntry &OMI = *it;
2485 const MatchableInfo &II = *OMI.MI;
2489 // Write the required features mask.
2490 if (!II.RequiredFeatures.empty()) {
2491 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2493 OS << II.RequiredFeatures[i]->getEnumName();
2498 // Store a pascal-style length byte in the mnemonic.
2499 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2500 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2501 << " /* " << II.Mnemonic << " */, ";
2505 OS << ", " << OMI.OperandMask;
2507 bool printComma = false;
2508 for (int i = 0, e = 31; i !=e; ++i)
2509 if (OMI.OperandMask & (1 << i)) {
2521 // Emit the operand class switch to call the correct custom parser for
2522 // the found operand class.
2523 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2524 << Target.getName() << ClassName << "::\n"
2525 << "tryCustomParseOperand(SmallVectorImpl<MCParsedAsmOperand*>"
2526 << " &Operands,\n unsigned MCK) {\n\n"
2527 << " switch(MCK) {\n";
2529 for (std::vector<ClassInfo*>::const_iterator it = Info.Classes.begin(),
2530 ie = Info.Classes.end(); it != ie; ++it) {
2531 ClassInfo *CI = *it;
2532 if (CI->ParserMethod.empty())
2534 OS << " case " << CI->Name << ":\n"
2535 << " return " << CI->ParserMethod << "(Operands);\n";
2538 OS << " default:\n";
2539 OS << " return MatchOperand_NoMatch;\n";
2541 OS << " return MatchOperand_NoMatch;\n";
2544 // Emit the static custom operand parser. This code is very similar with
2545 // the other matcher. Also use MatchResultTy here just in case we go for
2546 // a better error handling.
2547 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2548 << Target.getName() << ClassName << "::\n"
2549 << "MatchOperandParserImpl(SmallVectorImpl<MCParsedAsmOperand*>"
2550 << " &Operands,\n StringRef Mnemonic) {\n";
2552 // Emit code to get the available features.
2553 OS << " // Get the current feature set.\n";
2554 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2556 OS << " // Get the next operand index.\n";
2557 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2559 // Emit code to search the table.
2560 OS << " // Search the table.\n";
2561 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2562 OS << " MnemonicRange =\n";
2563 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2564 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2565 << " LessOpcodeOperand());\n\n";
2567 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2568 OS << " return MatchOperand_NoMatch;\n\n";
2570 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2571 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2573 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2574 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2576 // Emit check that the required features are available.
2577 OS << " // check if the available features match\n";
2578 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2579 << "!= it->RequiredFeatures) {\n";
2580 OS << " continue;\n";
2583 // Emit check to ensure the operand number matches.
2584 OS << " // check if the operand in question has a custom parser.\n";
2585 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2586 OS << " continue;\n\n";
2588 // Emit call to the custom parser method
2589 OS << " // call custom parse method to handle the operand\n";
2590 OS << " OperandMatchResultTy Result = ";
2591 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2592 OS << " if (Result != MatchOperand_NoMatch)\n";
2593 OS << " return Result;\n";
2596 OS << " // Okay, we had no match.\n";
2597 OS << " return MatchOperand_NoMatch;\n";
2601 void AsmMatcherEmitter::run(raw_ostream &OS) {
2602 CodeGenTarget Target(Records);
2603 Record *AsmParser = Target.getAsmParser();
2604 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2606 // Compute the information on the instructions to match.
2607 AsmMatcherInfo Info(AsmParser, Target, Records);
2610 // Sort the instruction table using the partial order on classes. We use
2611 // stable_sort to ensure that ambiguous instructions are still
2612 // deterministically ordered.
2613 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2614 less_ptr<MatchableInfo>());
2616 DEBUG_WITH_TYPE("instruction_info", {
2617 for (std::vector<MatchableInfo*>::iterator
2618 it = Info.Matchables.begin(), ie = Info.Matchables.end();
2623 // Check for ambiguous matchables.
2624 DEBUG_WITH_TYPE("ambiguous_instrs", {
2625 unsigned NumAmbiguous = 0;
2626 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
2627 for (unsigned j = i + 1; j != e; ++j) {
2628 MatchableInfo &A = *Info.Matchables[i];
2629 MatchableInfo &B = *Info.Matchables[j];
2631 if (A.couldMatchAmbiguouslyWith(B)) {
2632 errs() << "warning: ambiguous matchables:\n";
2634 errs() << "\nis incomparable with:\n";
2642 errs() << "warning: " << NumAmbiguous
2643 << " ambiguous matchables!\n";
2646 // Compute the information on the custom operand parsing.
2647 Info.buildOperandMatchInfo();
2649 // Write the output.
2651 // Information for the class declaration.
2652 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2653 OS << "#undef GET_ASSEMBLER_HEADER\n";
2654 OS << " // This should be included into the middle of the declaration of\n";
2655 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2656 OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
2657 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2658 << "unsigned Opcode,\n"
2659 << " const SmallVectorImpl<MCParsedAsmOperand*> "
2661 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2662 OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands);\n";
2663 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);\n";
2664 OS << " unsigned MatchInstructionImpl(\n";
2666 OS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n"
2667 << " MCInst &Inst,\n"
2668 << " unsigned &ErrorInfo,"
2669 << " bool matchingInlineAsm,\n"
2670 << " unsigned VariantID = 0);\n";
2672 if (Info.OperandMatchInfo.size()) {
2673 OS << "\n enum OperandMatchResultTy {\n";
2674 OS << " MatchOperand_Success, // operand matched successfully\n";
2675 OS << " MatchOperand_NoMatch, // operand did not match\n";
2676 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2678 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2679 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2680 OS << " StringRef Mnemonic);\n";
2682 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2683 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2684 OS << " unsigned MCK);\n\n";
2687 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2689 // Emit the operand match diagnostic enum names.
2690 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2691 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2692 emitOperandDiagnosticTypes(Info, OS);
2693 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2696 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2697 OS << "#undef GET_REGISTER_MATCHER\n\n";
2699 // Emit the subtarget feature enumeration.
2700 emitSubtargetFeatureFlagEnumeration(Info, OS);
2702 // Emit the function to match a register name to number.
2703 // This should be omitted for Mips target
2704 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2705 emitMatchRegisterName(Target, AsmParser, OS);
2707 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2709 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2710 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2712 // Generate the helper function to get the names for subtarget features.
2713 emitGetSubtargetFeatureName(Info, OS);
2715 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2717 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2718 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2720 // Generate the function that remaps for mnemonic aliases.
2721 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
2723 // Generate the convertToMCInst function to convert operands into an MCInst.
2724 // Also, generate the convertToMapAndConstraints function for MS-style inline
2725 // assembly. The latter doesn't actually generate a MCInst.
2726 emitConvertFuncs(Target, ClassName, Info.Matchables, OS);
2728 // Emit the enumeration for classes which participate in matching.
2729 emitMatchClassEnumeration(Target, Info.Classes, OS);
2731 // Emit the routine to match token strings to their match class.
2732 emitMatchTokenString(Target, Info.Classes, OS);
2734 // Emit the subclass predicate routine.
2735 emitIsSubclass(Target, Info.Classes, OS);
2737 // Emit the routine to validate an operand against a match class.
2738 emitValidateOperandClass(Info, OS);
2740 // Emit the available features compute function.
2741 emitComputeAvailableFeatures(Info, OS);
2744 StringToOffsetTable StringTable;
2746 size_t MaxNumOperands = 0;
2747 unsigned MaxMnemonicIndex = 0;
2748 for (std::vector<MatchableInfo*>::const_iterator it =
2749 Info.Matchables.begin(), ie = Info.Matchables.end();
2751 MatchableInfo &II = **it;
2752 MaxNumOperands = std::max(MaxNumOperands, II.AsmOperands.size());
2754 // Store a pascal-style length byte in the mnemonic.
2755 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2756 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2757 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2760 OS << "static const char *const MnemonicTable =\n";
2761 StringTable.EmitString(OS);
2764 // Emit the static match table; unused classes get initalized to 0 which is
2765 // guaranteed to be InvalidMatchClass.
2767 // FIXME: We can reduce the size of this table very easily. First, we change
2768 // it so that store the kinds in separate bit-fields for each index, which
2769 // only needs to be the max width used for classes at that index (we also need
2770 // to reject based on this during classification). If we then make sure to
2771 // order the match kinds appropriately (putting mnemonics last), then we
2772 // should only end up using a few bits for each class, especially the ones
2773 // following the mnemonic.
2774 OS << "namespace {\n";
2775 OS << " struct MatchEntry {\n";
2776 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2778 OS << " uint16_t Opcode;\n";
2779 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2781 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2782 << " RequiredFeatures;\n";
2783 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2784 << " Classes[" << MaxNumOperands << "];\n";
2785 OS << " StringRef getMnemonic() const {\n";
2786 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2787 OS << " MnemonicTable[Mnemonic]);\n";
2791 OS << " // Predicate for searching for an opcode.\n";
2792 OS << " struct LessOpcode {\n";
2793 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2794 OS << " return LHS.getMnemonic() < RHS;\n";
2796 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2797 OS << " return LHS < RHS.getMnemonic();\n";
2799 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2800 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2804 OS << "} // end anonymous namespace.\n\n";
2806 unsigned VariantCount = Target.getAsmParserVariantCount();
2807 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2808 Record *AsmVariant = Target.getAsmParserVariant(VC);
2809 std::string CommentDelimiter =
2810 AsmVariant->getValueAsString("CommentDelimiter");
2811 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
2812 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2814 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
2816 for (std::vector<MatchableInfo*>::const_iterator it =
2817 Info.Matchables.begin(), ie = Info.Matchables.end();
2819 MatchableInfo &II = **it;
2820 if (II.AsmVariantID != AsmVariantNo)
2823 // Store a pascal-style length byte in the mnemonic.
2824 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2825 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2826 << " /* " << II.Mnemonic << " */, "
2827 << Target.getName() << "::"
2828 << II.getResultInst()->TheDef->getName() << ", "
2829 << II.ConversionFnKind << ", ";
2831 // Write the required features mask.
2832 if (!II.RequiredFeatures.empty()) {
2833 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2835 OS << II.RequiredFeatures[i]->getEnumName();
2841 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
2842 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
2845 OS << Op.Class->Name;
2853 // A method to determine if a mnemonic is in the list.
2854 OS << "bool " << Target.getName() << ClassName << "::\n"
2855 << "mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {\n";
2856 OS << " // Find the appropriate table for this asm variant.\n";
2857 OS << " const MatchEntry *Start, *End;\n";
2858 OS << " switch (VariantID) {\n";
2859 OS << " default: // unreachable\n";
2860 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2861 Record *AsmVariant = Target.getAsmParserVariant(VC);
2862 std::string CommentDelimiter =
2863 AsmVariant->getValueAsString("CommentDelimiter");
2864 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
2865 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2866 OS << " case " << AsmVariantNo << ": Start = MatchTable" << VC
2867 << "; End = array_endof(MatchTable" << VC << "); break;\n";
2870 OS << " // Search the table.\n";
2871 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2872 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n";
2873 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2876 // Finally, build the match function.
2878 << Target.getName() << ClassName << "::\n"
2879 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
2881 OS << " MCInst &Inst,\n"
2882 << "unsigned &ErrorInfo, bool matchingInlineAsm, unsigned VariantID) {\n";
2884 OS << " // Eliminate obvious mismatches.\n";
2885 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2886 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2887 OS << " return Match_InvalidOperand;\n";
2890 // Emit code to get the available features.
2891 OS << " // Get the current feature set.\n";
2892 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2894 OS << " // Get the instruction mnemonic, which is the first token.\n";
2895 OS << " StringRef Mnemonic = ((" << Target.getName()
2896 << "Operand*)Operands[0])->getToken();\n\n";
2898 if (HasMnemonicAliases) {
2899 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2900 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
2903 // Emit code to compute the class list for this operand vector.
2904 OS << " // Some state to try to produce better error messages.\n";
2905 OS << " bool HadMatchOtherThanFeatures = false;\n";
2906 OS << " bool HadMatchOtherThanPredicate = false;\n";
2907 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2908 OS << " unsigned MissingFeatures = ~0U;\n";
2909 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2910 OS << " // wrong for all instances of the instruction.\n";
2911 OS << " ErrorInfo = ~0U;\n";
2913 // Emit code to search the table.
2914 OS << " // Find the appropriate table for this asm variant.\n";
2915 OS << " const MatchEntry *Start, *End;\n";
2916 OS << " switch (VariantID) {\n";
2917 OS << " default: // unreachable\n";
2918 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2919 Record *AsmVariant = Target.getAsmParserVariant(VC);
2920 std::string CommentDelimiter =
2921 AsmVariant->getValueAsString("CommentDelimiter");
2922 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
2923 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2924 OS << " case " << AsmVariantNo << ": Start = MatchTable" << VC
2925 << "; End = array_endof(MatchTable" << VC << "); break;\n";
2928 OS << " // Search the table.\n";
2929 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2930 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
2932 OS << " // Return a more specific error code if no mnemonics match.\n";
2933 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2934 OS << " return Match_MnemonicFail;\n\n";
2936 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2937 << "*ie = MnemonicRange.second;\n";
2938 OS << " it != ie; ++it) {\n";
2940 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2941 OS << " assert(Mnemonic == it->getMnemonic());\n";
2943 // Emit check that the subclasses match.
2944 OS << " bool OperandsValid = true;\n";
2945 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2946 OS << " if (i + 1 >= Operands.size()) {\n";
2947 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2948 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n";
2951 OS << " unsigned Diag = validateOperandClass(Operands[i+1],\n";
2953 OS << "(MatchClassKind)it->Classes[i]);\n";
2954 OS << " if (Diag == Match_Success)\n";
2955 OS << " continue;\n";
2956 OS << " // If the generic handler indicates an invalid operand\n";
2957 OS << " // failure, check for a special case.\n";
2958 OS << " if (Diag == Match_InvalidOperand) {\n";
2959 OS << " Diag = validateTargetOperandClass(Operands[i+1],\n";
2961 OS << "(MatchClassKind)it->Classes[i]);\n";
2962 OS << " if (Diag == Match_Success)\n";
2963 OS << " continue;\n";
2965 OS << " // If this operand is broken for all of the instances of this\n";
2966 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2967 OS << " // If we already had a match that only failed due to a\n";
2968 OS << " // target predicate, that diagnostic is preferred.\n";
2969 OS << " if (!HadMatchOtherThanPredicate &&\n";
2970 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n";
2971 OS << " ErrorInfo = i+1;\n";
2972 OS << " // InvalidOperand is the default. Prefer specificity.\n";
2973 OS << " if (Diag != Match_InvalidOperand)\n";
2974 OS << " RetCode = Diag;\n";
2976 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2977 OS << " OperandsValid = false;\n";
2981 OS << " if (!OperandsValid) continue;\n";
2983 // Emit check that the required features are available.
2984 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2985 << "!= it->RequiredFeatures) {\n";
2986 OS << " HadMatchOtherThanFeatures = true;\n";
2987 OS << " unsigned NewMissingFeatures = it->RequiredFeatures & "
2988 "~AvailableFeatures;\n";
2989 OS << " if (CountPopulation_32(NewMissingFeatures) <=\n"
2990 " CountPopulation_32(MissingFeatures))\n";
2991 OS << " MissingFeatures = NewMissingFeatures;\n";
2992 OS << " continue;\n";
2995 OS << " if (matchingInlineAsm) {\n";
2996 OS << " Inst.setOpcode(it->Opcode);\n";
2997 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
2998 OS << " return Match_Success;\n";
3000 OS << " // We have selected a definite instruction, convert the parsed\n"
3001 << " // operands into the appropriate MCInst.\n";
3002 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
3005 // Verify the instruction with the target-specific match predicate function.
3006 OS << " // We have a potential match. Check the target predicate to\n"
3007 << " // handle any context sensitive constraints.\n"
3008 << " unsigned MatchResult;\n"
3009 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
3010 << " Match_Success) {\n"
3011 << " Inst.clear();\n"
3012 << " RetCode = MatchResult;\n"
3013 << " HadMatchOtherThanPredicate = true;\n"
3017 // Call the post-processing function, if used.
3018 std::string InsnCleanupFn =
3019 AsmParser->getValueAsString("AsmParserInstCleanup");
3020 if (!InsnCleanupFn.empty())
3021 OS << " " << InsnCleanupFn << "(Inst);\n";
3023 OS << " return Match_Success;\n";
3026 OS << " // Okay, we had no match. Try to return a useful error code.\n";
3027 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
3028 OS << " return RetCode;\n\n";
3029 OS << " // Missing feature matches return which features were missing\n";
3030 OS << " ErrorInfo = MissingFeatures;\n";
3031 OS << " return Match_MissingFeature;\n";
3034 if (Info.OperandMatchInfo.size())
3035 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
3038 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
3043 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
3044 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
3045 AsmMatcherEmitter(RK).run(OS);
3048 } // End llvm namespace