1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures.
13 // The input to the target specific matcher is a list of literal tokens and
14 // operands. The target specific parser should generally eliminate any syntax
15 // which is not relevant for matching; for example, comma tokens should have
16 // already been consumed and eliminated by the parser. Most instructions will
17 // end up with a single literal token (the instruction name) and some number of
20 // Some example inputs, for X86:
21 // 'addl' (immediate ...) (register ...)
22 // 'add' (immediate ...) (memory ...)
25 // The assembly matcher is responsible for converting this input into a precise
26 // machine instruction (i.e., an instruction with a well defined encoding). This
27 // mapping has several properties which complicate matching:
29 // - It may be ambiguous; many architectures can legally encode particular
30 // variants of an instruction in different ways (for example, using a smaller
31 // encoding for small immediates). Such ambiguities should never be
32 // arbitrarily resolved by the assembler, the assembler is always responsible
33 // for choosing the "best" available instruction.
35 // - It may depend on the subtarget or the assembler context. Instructions
36 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
37 // an SSE instruction in a file being assembled for i486) should be accepted
38 // and rejected by the assembler front end. However, if the proper encoding
39 // for an instruction is dependent on the assembler context then the matcher
40 // is responsible for selecting the correct machine instruction for the
43 // The core matching algorithm attempts to exploit the regularity in most
44 // instruction sets to quickly determine the set of possibly matching
45 // instructions, and the simplify the generated code. Additionally, this helps
46 // to ensure that the ambiguities are intentionally resolved by the user.
48 // The matching is divided into two distinct phases:
50 // 1. Classification: Each operand is mapped to the unique set which (a)
51 // contains it, and (b) is the largest such subset for which a single
52 // instruction could match all members.
54 // For register classes, we can generate these subgroups automatically. For
55 // arbitrary operands, we expect the user to define the classes and their
56 // relations to one another (for example, 8-bit signed immediates as a
57 // subset of 32-bit immediates).
59 // By partitioning the operands in this way, we guarantee that for any
60 // tuple of classes, any single instruction must match either all or none
61 // of the sets of operands which could classify to that tuple.
63 // In addition, the subset relation amongst classes induces a partial order
64 // on such tuples, which we use to resolve ambiguities.
66 // FIXME: What do we do if a crazy case shows up where this is the wrong
69 // 2. The input can now be treated as a tuple of classes (static tokens are
70 // simple singleton sets). Each such tuple should generally map to a single
71 // instruction (we currently ignore cases where this isn't true, whee!!!),
72 // which we can emit a simple matcher for.
74 //===----------------------------------------------------------------------===//
76 #include "AsmMatcherEmitter.h"
77 #include "CodeGenTarget.h"
79 #include "StringMatcher.h"
80 #include "llvm/ADT/OwningPtr.h"
81 #include "llvm/ADT/SmallPtrSet.h"
82 #include "llvm/ADT/SmallVector.h"
83 #include "llvm/ADT/STLExtras.h"
84 #include "llvm/ADT/StringExtras.h"
85 #include "llvm/Support/CommandLine.h"
86 #include "llvm/Support/Debug.h"
92 static cl::opt<std::string>
93 MatchPrefix("match-prefix", cl::init(""),
94 cl::desc("Only match instructions with the given prefix"));
99 struct SubtargetFeatureInfo;
101 /// ClassInfo - Helper class for storing the information about a particular
102 /// class of operands which can be matched.
105 /// Invalid kind, for use as a sentinel value.
108 /// The class for a particular token.
111 /// The (first) register class, subsequent register classes are
112 /// RegisterClass0+1, and so on.
115 /// The (first) user defined class, subsequent user defined classes are
116 /// UserClass0+1, and so on.
120 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
121 /// N) for the Nth user defined class.
124 /// SuperClasses - The super classes of this class. Note that for simplicities
125 /// sake user operands only record their immediate super class, while register
126 /// operands include all superclasses.
127 std::vector<ClassInfo*> SuperClasses;
129 /// Name - The full class name, suitable for use in an enum.
132 /// ClassName - The unadorned generic name for this class (e.g., Token).
133 std::string ClassName;
135 /// ValueName - The name of the value this class represents; for a token this
136 /// is the literal token string, for an operand it is the TableGen class (or
137 /// empty if this is a derived class).
138 std::string ValueName;
140 /// PredicateMethod - The name of the operand method to test whether the
141 /// operand matches this class; this is not valid for Token or register kinds.
142 std::string PredicateMethod;
144 /// RenderMethod - The name of the operand method to add this operand to an
145 /// MCInst; this is not valid for Token or register kinds.
146 std::string RenderMethod;
148 /// For register classes, the records for all the registers in this class.
149 std::set<Record*> Registers;
152 /// isRegisterClass() - Check if this is a register class.
153 bool isRegisterClass() const {
154 return Kind >= RegisterClass0 && Kind < UserClass0;
157 /// isUserClass() - Check if this is a user defined class.
158 bool isUserClass() const {
159 return Kind >= UserClass0;
162 /// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes
163 /// are related if they are in the same class hierarchy.
164 bool isRelatedTo(const ClassInfo &RHS) const {
165 // Tokens are only related to tokens.
166 if (Kind == Token || RHS.Kind == Token)
167 return Kind == Token && RHS.Kind == Token;
169 // Registers classes are only related to registers classes, and only if
170 // their intersection is non-empty.
171 if (isRegisterClass() || RHS.isRegisterClass()) {
172 if (!isRegisterClass() || !RHS.isRegisterClass())
175 std::set<Record*> Tmp;
176 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
177 std::set_intersection(Registers.begin(), Registers.end(),
178 RHS.Registers.begin(), RHS.Registers.end(),
184 // Otherwise we have two users operands; they are related if they are in the
185 // same class hierarchy.
187 // FIXME: This is an oversimplification, they should only be related if they
188 // intersect, however we don't have that information.
189 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
190 const ClassInfo *Root = this;
191 while (!Root->SuperClasses.empty())
192 Root = Root->SuperClasses.front();
194 const ClassInfo *RHSRoot = &RHS;
195 while (!RHSRoot->SuperClasses.empty())
196 RHSRoot = RHSRoot->SuperClasses.front();
198 return Root == RHSRoot;
201 /// isSubsetOf - Test whether this class is a subset of \arg RHS;
202 bool isSubsetOf(const ClassInfo &RHS) const {
203 // This is a subset of RHS if it is the same class...
207 // ... or if any of its super classes are a subset of RHS.
208 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
209 ie = SuperClasses.end(); it != ie; ++it)
210 if ((*it)->isSubsetOf(RHS))
216 /// operator< - Compare two classes.
217 bool operator<(const ClassInfo &RHS) const {
221 // Unrelated classes can be ordered by kind.
222 if (!isRelatedTo(RHS))
223 return Kind < RHS.Kind;
227 assert(0 && "Invalid kind!");
229 // Tokens are comparable by value.
231 // FIXME: Compare by enum value.
232 return ValueName < RHS.ValueName;
235 // This class preceeds the RHS if it is a proper subset of the RHS.
238 if (RHS.isSubsetOf(*this))
241 // Otherwise, order by name to ensure we have a total ordering.
242 return ValueName < RHS.ValueName;
247 /// MatchableInfo - Helper class for storing the necessary information for an
248 /// instruction or alias which is capable of being matched.
249 struct MatchableInfo {
251 /// Token - This is the token that the operand came from.
254 /// The unique class instance this operand should match.
257 /// The original operand this corresponds to, if any.
258 const CGIOperandList::OperandInfo *OperandInfo;
260 explicit Operand(StringRef T) : Token(T), Class(0), OperandInfo(0) {}
263 /// InstrName - The target name for this instruction.
264 std::string InstrName;
266 /// TheDef - This is the definition of the instruction or InstAlias that this
267 /// matchable came from.
268 Record *const TheDef;
270 /// OperandList - This is the operand list that came from the (ins) and (outs)
271 /// list of the alias or instruction.
272 const CGIOperandList &OperandList;
274 /// AsmString - The assembly string for this instruction (with variants
275 /// removed), e.g. "movsx $src, $dst".
276 std::string AsmString;
278 /// Mnemonic - This is the first token of the matched instruction, its
282 /// AsmOperands - The textual operands that this instruction matches,
283 /// annotated with a class and where in the OperandList they were defined.
284 /// This directly corresponds to the tokenized AsmString after the mnemonic is
286 SmallVector<Operand, 4> AsmOperands;
288 /// Predicates - The required subtarget features to match this instruction.
289 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
291 /// ConversionFnKind - The enum value which is passed to the generated
292 /// ConvertToMCInst to convert parsed operands into an MCInst for this
294 std::string ConversionFnKind;
296 MatchableInfo(const CodeGenInstruction &CGI)
297 : TheDef(CGI.TheDef), OperandList(CGI.Operands), AsmString(CGI.AsmString) {
298 InstrName = TheDef->getName();
301 MatchableInfo(const CodeGenInstAlias *Alias)
302 : TheDef(Alias->TheDef), OperandList(Alias->Operands),
303 AsmString(Alias->AsmString) {
306 DefInit *DI = dynamic_cast<DefInit*>(Alias->Result->getOperator());
309 InstrName = DI->getDef()->getName();
312 void Initialize(const AsmMatcherInfo &Info,
313 SmallPtrSet<Record*, 16> &SingletonRegisters);
315 /// Validate - Return true if this matchable is a valid thing to match against
316 /// and perform a bunch of validity checking.
317 bool Validate(StringRef CommentDelimiter, bool Hack) const;
319 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
320 /// register, return the Record for it, otherwise return null.
321 Record *getSingletonRegisterForAsmOperand(unsigned i,
322 const AsmMatcherInfo &Info) const;
324 /// operator< - Compare two matchables.
325 bool operator<(const MatchableInfo &RHS) const {
326 // The primary comparator is the instruction mnemonic.
327 if (Mnemonic != RHS.Mnemonic)
328 return Mnemonic < RHS.Mnemonic;
330 if (AsmOperands.size() != RHS.AsmOperands.size())
331 return AsmOperands.size() < RHS.AsmOperands.size();
333 // Compare lexicographically by operand. The matcher validates that other
334 // orderings wouldn't be ambiguous using \see CouldMatchAmiguouslyWith().
335 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
336 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
338 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
345 /// CouldMatchAmiguouslyWith - Check whether this matchable could
346 /// ambiguously match the same set of operands as \arg RHS (without being a
347 /// strictly superior match).
348 bool CouldMatchAmiguouslyWith(const MatchableInfo &RHS) {
349 // The primary comparator is the instruction mnemonic.
350 if (Mnemonic != RHS.Mnemonic)
353 // The number of operands is unambiguous.
354 if (AsmOperands.size() != RHS.AsmOperands.size())
357 // Otherwise, make sure the ordering of the two instructions is unambiguous
358 // by checking that either (a) a token or operand kind discriminates them,
359 // or (b) the ordering among equivalent kinds is consistent.
361 // Tokens and operand kinds are unambiguous (assuming a correct target
363 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
364 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
365 AsmOperands[i].Class->Kind == ClassInfo::Token)
366 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
367 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
370 // Otherwise, this operand could commute if all operands are equivalent, or
371 // there is a pair of operands that compare less than and a pair that
372 // compare greater than.
373 bool HasLT = false, HasGT = false;
374 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
375 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
377 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
381 return !(HasLT ^ HasGT);
387 void TokenizeAsmString(const AsmMatcherInfo &Info);
390 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
391 /// feature which participates in instruction matching.
392 struct SubtargetFeatureInfo {
393 /// \brief The predicate record for this feature.
396 /// \brief An unique index assigned to represent this feature.
399 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
401 /// \brief The name of the enumerated constant identifying this feature.
402 std::string getEnumName() const {
403 return "Feature_" + TheDef->getName();
407 class AsmMatcherInfo {
409 /// The tablegen AsmParser record.
412 /// Target - The target information.
413 CodeGenTarget &Target;
415 /// The AsmParser "RegisterPrefix" value.
416 std::string RegisterPrefix;
418 /// The classes which are needed for matching.
419 std::vector<ClassInfo*> Classes;
421 /// The information on the matchables to match.
422 std::vector<MatchableInfo*> Matchables;
424 /// Map of Register records to their class information.
425 std::map<Record*, ClassInfo*> RegisterClasses;
427 /// Map of Predicate records to their subtarget information.
428 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
431 /// Map of token to class information which has already been constructed.
432 std::map<std::string, ClassInfo*> TokenClasses;
434 /// Map of RegisterClass records to their class information.
435 std::map<Record*, ClassInfo*> RegisterClassClasses;
437 /// Map of AsmOperandClass records to their class information.
438 std::map<Record*, ClassInfo*> AsmOperandClasses;
441 /// getTokenClass - Lookup or create the class for the given token.
442 ClassInfo *getTokenClass(StringRef Token);
444 /// getOperandClass - Lookup or create the class for the given operand.
445 ClassInfo *getOperandClass(StringRef Token,
446 const CGIOperandList::OperandInfo &OI);
448 /// BuildRegisterClasses - Build the ClassInfo* instances for register
450 void BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
452 /// BuildOperandClasses - Build the ClassInfo* instances for user defined
454 void BuildOperandClasses();
457 AsmMatcherInfo(Record *AsmParser, CodeGenTarget &Target);
459 /// BuildInfo - Construct the various tables used during matching.
462 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
464 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
465 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
466 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
467 SubtargetFeatures.find(Def);
468 return I == SubtargetFeatures.end() ? 0 : I->second;
474 void MatchableInfo::dump() {
475 errs() << InstrName << " -- " << "flattened:\"" << AsmString << "\"\n";
477 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
478 Operand &Op = AsmOperands[i];
479 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
480 if (Op.Class->Kind == ClassInfo::Token) {
481 errs() << '\"' << Op.Token << "\"\n";
485 if (!Op.OperandInfo) {
486 errs() << "(singleton register)\n";
490 const CGIOperandList::OperandInfo &OI = *Op.OperandInfo;
491 errs() << OI.Name << " " << OI.Rec->getName()
492 << " (" << OI.MIOperandNo << ", " << OI.MINumOperands << ")\n";
496 void MatchableInfo::Initialize(const AsmMatcherInfo &Info,
497 SmallPtrSet<Record*, 16> &SingletonRegisters) {
498 // TODO: Eventually support asmparser for Variant != 0.
499 AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0);
501 TokenizeAsmString(Info);
503 // Compute the require features.
504 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
505 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
506 if (SubtargetFeatureInfo *Feature =
507 Info.getSubtargetFeature(Predicates[i]))
508 RequiredFeatures.push_back(Feature);
510 // Collect singleton registers, if used.
511 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
512 if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info))
513 SingletonRegisters.insert(Reg);
517 /// TokenizeAsmString - Tokenize a simplified assembly string.
518 void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) {
519 StringRef String = AsmString;
522 for (unsigned i = 0, e = String.size(); i != e; ++i) {
532 AsmOperands.push_back(Operand(String.slice(Prev, i)));
535 if (!isspace(String[i]) && String[i] != ',')
536 AsmOperands.push_back(Operand(String.substr(i, 1)));
542 AsmOperands.push_back(Operand(String.slice(Prev, i)));
546 assert(i != String.size() && "Invalid quoted character");
547 AsmOperands.push_back(Operand(String.substr(i, 1)));
552 // If this isn't "${", treat like a normal token.
553 if (i + 1 == String.size() || String[i + 1] != '{') {
555 AsmOperands.push_back(Operand(String.slice(Prev, i)));
563 AsmOperands.push_back(Operand(String.slice(Prev, i)));
567 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
568 assert(End != String.end() && "Missing brace in operand reference!");
569 size_t EndPos = End - String.begin();
570 AsmOperands.push_back(Operand(String.slice(i, EndPos+1)));
578 AsmOperands.push_back(Operand(String.slice(Prev, i)));
587 if (InTok && Prev != String.size())
588 AsmOperands.push_back(Operand(String.substr(Prev)));
590 // The first token of the instruction is the mnemonic, which must be a
591 // simple string, not a $foo variable or a singleton register.
592 assert(!AsmOperands.empty() && "Instruction has no tokens?");
593 Mnemonic = AsmOperands[0].Token;
594 if (Mnemonic[0] == '$' || getSingletonRegisterForAsmOperand(0, Info))
595 throw TGError(TheDef->getLoc(),
596 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
598 // Remove the first operand, it is tracked in the mnemonic field.
599 AsmOperands.erase(AsmOperands.begin());
604 /// getRegisterRecord - Get the register record for \arg name, or 0.
605 static Record *getRegisterRecord(CodeGenTarget &Target, StringRef Name) {
606 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
607 const CodeGenRegister &Reg = Target.getRegisters()[i];
608 if (Name == Reg.TheDef->getValueAsString("AsmName"))
615 bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const {
616 // Reject matchables with no .s string.
617 if (AsmString.empty())
618 throw TGError(TheDef->getLoc(), "instruction with empty asm string");
620 // Reject any matchables with a newline in them, they should be marked
621 // isCodeGenOnly if they are pseudo instructions.
622 if (AsmString.find('\n') != std::string::npos)
623 throw TGError(TheDef->getLoc(),
624 "multiline instruction is not valid for the asmparser, "
625 "mark it isCodeGenOnly");
627 // Remove comments from the asm string. We know that the asmstring only
629 if (!CommentDelimiter.empty() &&
630 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
631 throw TGError(TheDef->getLoc(),
632 "asmstring for instruction has comment character in it, "
633 "mark it isCodeGenOnly");
635 // Reject matchables with operand modifiers, these aren't something we can
636 /// handle, the target should be refactored to use operands instead of
639 // Also, check for instructions which reference the operand multiple times;
640 // this implies a constraint we would not honor.
641 std::set<std::string> OperandNames;
642 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
643 StringRef Tok = AsmOperands[i].Token;
644 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
645 throw TGError(TheDef->getLoc(),
646 "matchable with operand modifier '" + Tok.str() +
647 "' not supported by asm matcher. Mark isCodeGenOnly!");
649 // Verify that any operand is only mentioned once.
650 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
652 throw TGError(TheDef->getLoc(),
653 "ERROR: matchable with tied operand '" + Tok.str() +
654 "' can never be matched!");
655 // FIXME: Should reject these. The ARM backend hits this with $lane in a
656 // bunch of instructions. It is unclear what the right answer is.
658 errs() << "warning: '" << InstrName << "': "
659 << "ignoring instruction with tied operand '"
660 << Tok.str() << "'\n";
670 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
671 /// register, return the register name, otherwise return a null StringRef.
672 Record *MatchableInfo::
673 getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{
674 StringRef Tok = AsmOperands[i].Token;
675 if (!Tok.startswith(Info.RegisterPrefix))
678 StringRef RegName = Tok.substr(Info.RegisterPrefix.size());
679 if (Record *Rec = getRegisterRecord(Info.Target, RegName))
682 // If there is no register prefix (i.e. "%" in "%eax"), then this may
683 // be some random non-register token, just ignore it.
684 if (Info.RegisterPrefix.empty())
687 std::string Err = "unable to find register for '" + RegName.str() +
688 "' (which matches register prefix)";
689 throw TGError(TheDef->getLoc(), Err);
693 static std::string getEnumNameForToken(StringRef Str) {
696 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
698 case '*': Res += "_STAR_"; break;
699 case '%': Res += "_PCT_"; break;
700 case ':': Res += "_COLON_"; break;
705 Res += "_" + utostr((unsigned) *it) + "_";
712 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
713 ClassInfo *&Entry = TokenClasses[Token];
716 Entry = new ClassInfo();
717 Entry->Kind = ClassInfo::Token;
718 Entry->ClassName = "Token";
719 Entry->Name = "MCK_" + getEnumNameForToken(Token);
720 Entry->ValueName = Token;
721 Entry->PredicateMethod = "<invalid>";
722 Entry->RenderMethod = "<invalid>";
723 Classes.push_back(Entry);
730 AsmMatcherInfo::getOperandClass(StringRef Token,
731 const CGIOperandList::OperandInfo &OI) {
732 if (OI.Rec->isSubClassOf("RegisterClass")) {
733 ClassInfo *CI = RegisterClassClasses[OI.Rec];
736 throw TGError(OI.Rec->getLoc(), "register class has no class info!");
741 assert(OI.Rec->isSubClassOf("Operand") && "Unexpected operand!");
742 Record *MatchClass = OI.Rec->getValueAsDef("ParserMatchClass");
743 ClassInfo *CI = AsmOperandClasses[MatchClass];
746 throw TGError(OI.Rec->getLoc(), "operand has no match class!");
751 void AsmMatcherInfo::
752 BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
753 std::vector<CodeGenRegisterClass> RegisterClasses;
754 std::vector<CodeGenRegister> Registers;
756 RegisterClasses = Target.getRegisterClasses();
757 Registers = Target.getRegisters();
759 // The register sets used for matching.
760 std::set< std::set<Record*> > RegisterSets;
762 // Gather the defined sets.
763 for (std::vector<CodeGenRegisterClass>::iterator it = RegisterClasses.begin(),
764 ie = RegisterClasses.end(); it != ie; ++it)
765 RegisterSets.insert(std::set<Record*>(it->Elements.begin(),
766 it->Elements.end()));
768 // Add any required singleton sets.
769 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
770 ie = SingletonRegisters.end(); it != ie; ++it) {
772 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
775 // Introduce derived sets where necessary (when a register does not determine
776 // a unique register set class), and build the mapping of registers to the set
777 // they should classify to.
778 std::map<Record*, std::set<Record*> > RegisterMap;
779 for (std::vector<CodeGenRegister>::iterator it = Registers.begin(),
780 ie = Registers.end(); it != ie; ++it) {
781 CodeGenRegister &CGR = *it;
782 // Compute the intersection of all sets containing this register.
783 std::set<Record*> ContainingSet;
785 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
786 ie = RegisterSets.end(); it != ie; ++it) {
787 if (!it->count(CGR.TheDef))
790 if (ContainingSet.empty()) {
793 std::set<Record*> Tmp;
794 std::swap(Tmp, ContainingSet);
795 std::insert_iterator< std::set<Record*> > II(ContainingSet,
796 ContainingSet.begin());
797 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(),
802 if (!ContainingSet.empty()) {
803 RegisterSets.insert(ContainingSet);
804 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
808 // Construct the register classes.
809 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
811 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
812 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
813 ClassInfo *CI = new ClassInfo();
814 CI->Kind = ClassInfo::RegisterClass0 + Index;
815 CI->ClassName = "Reg" + utostr(Index);
816 CI->Name = "MCK_Reg" + utostr(Index);
818 CI->PredicateMethod = ""; // unused
819 CI->RenderMethod = "addRegOperands";
821 Classes.push_back(CI);
822 RegisterSetClasses.insert(std::make_pair(*it, CI));
825 // Find the superclasses; we could compute only the subgroup lattice edges,
826 // but there isn't really a point.
827 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
828 ie = RegisterSets.end(); it != ie; ++it) {
829 ClassInfo *CI = RegisterSetClasses[*it];
830 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
831 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
833 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
834 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
837 // Name the register classes which correspond to a user defined RegisterClass.
838 for (std::vector<CodeGenRegisterClass>::iterator it = RegisterClasses.begin(),
839 ie = RegisterClasses.end(); it != ie; ++it) {
840 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(it->Elements.begin(),
841 it->Elements.end())];
842 if (CI->ValueName.empty()) {
843 CI->ClassName = it->getName();
844 CI->Name = "MCK_" + it->getName();
845 CI->ValueName = it->getName();
847 CI->ValueName = CI->ValueName + "," + it->getName();
849 RegisterClassClasses.insert(std::make_pair(it->TheDef, CI));
852 // Populate the map for individual registers.
853 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
854 ie = RegisterMap.end(); it != ie; ++it)
855 this->RegisterClasses[it->first] = RegisterSetClasses[it->second];
857 // Name the register classes which correspond to singleton registers.
858 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
859 ie = SingletonRegisters.end(); it != ie; ++it) {
861 ClassInfo *CI = this->RegisterClasses[Rec];
862 assert(CI && "Missing singleton register class info!");
864 if (CI->ValueName.empty()) {
865 CI->ClassName = Rec->getName();
866 CI->Name = "MCK_" + Rec->getName();
867 CI->ValueName = Rec->getName();
869 CI->ValueName = CI->ValueName + "," + Rec->getName();
873 void AsmMatcherInfo::BuildOperandClasses() {
874 std::vector<Record*> AsmOperands =
875 Records.getAllDerivedDefinitions("AsmOperandClass");
877 // Pre-populate AsmOperandClasses map.
878 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
879 ie = AsmOperands.end(); it != ie; ++it)
880 AsmOperandClasses[*it] = new ClassInfo();
883 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
884 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
885 ClassInfo *CI = AsmOperandClasses[*it];
886 CI->Kind = ClassInfo::UserClass0 + Index;
888 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
889 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
890 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
892 PrintError((*it)->getLoc(), "Invalid super class reference!");
896 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
898 PrintError((*it)->getLoc(), "Invalid super class reference!");
900 CI->SuperClasses.push_back(SC);
902 CI->ClassName = (*it)->getValueAsString("Name");
903 CI->Name = "MCK_" + CI->ClassName;
904 CI->ValueName = (*it)->getName();
906 // Get or construct the predicate method name.
907 Init *PMName = (*it)->getValueInit("PredicateMethod");
908 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
909 CI->PredicateMethod = SI->getValue();
911 assert(dynamic_cast<UnsetInit*>(PMName) &&
912 "Unexpected PredicateMethod field!");
913 CI->PredicateMethod = "is" + CI->ClassName;
916 // Get or construct the render method name.
917 Init *RMName = (*it)->getValueInit("RenderMethod");
918 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
919 CI->RenderMethod = SI->getValue();
921 assert(dynamic_cast<UnsetInit*>(RMName) &&
922 "Unexpected RenderMethod field!");
923 CI->RenderMethod = "add" + CI->ClassName + "Operands";
926 AsmOperandClasses[*it] = CI;
927 Classes.push_back(CI);
931 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, CodeGenTarget &target)
932 : AsmParser(asmParser), Target(target),
933 RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) {
937 void AsmMatcherInfo::BuildInfo() {
938 // Build information about all of the AssemblerPredicates.
939 std::vector<Record*> AllPredicates =
940 Records.getAllDerivedDefinitions("Predicate");
941 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
942 Record *Pred = AllPredicates[i];
943 // Ignore predicates that are not intended for the assembler.
944 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
947 if (Pred->getName().empty())
948 throw TGError(Pred->getLoc(), "Predicate has no name!");
950 unsigned FeatureNo = SubtargetFeatures.size();
951 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
952 assert(FeatureNo < 32 && "Too many subtarget features!");
955 StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter");
957 // Parse the instructions; we need to do this first so that we can gather the
958 // singleton register classes.
959 SmallPtrSet<Record*, 16> SingletonRegisters;
960 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
961 E = Target.inst_end(); I != E; ++I) {
962 const CodeGenInstruction &CGI = **I;
964 // If the tblgen -match-prefix option is specified (for tblgen hackers),
965 // filter the set of instructions we consider.
966 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
969 // Ignore "codegen only" instructions.
970 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
973 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
975 II->Initialize(*this, SingletonRegisters);
977 // Ignore instructions which shouldn't be matched and diagnose invalid
978 // instruction definitions with an error.
979 if (!II->Validate(CommentDelimiter, true))
982 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
984 // FIXME: This is a total hack.
985 if (StringRef(II->InstrName).startswith("Int_") ||
986 StringRef(II->InstrName).endswith("_Int"))
989 Matchables.push_back(II.take());
992 // Parse all of the InstAlias definitions and stick them in the list of
994 std::vector<Record*> AllInstAliases =
995 Records.getAllDerivedDefinitions("InstAlias");
996 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
997 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i]);
999 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1001 II->Initialize(*this, SingletonRegisters);
1003 // Validate the alias definitions.
1004 II->Validate(CommentDelimiter, false);
1006 Matchables.push_back(II.take());
1009 // Build info for the register classes.
1010 BuildRegisterClasses(SingletonRegisters);
1012 // Build info for the user defined assembly operand classes.
1013 BuildOperandClasses();
1015 // Build the information about matchables.
1016 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1017 ie = Matchables.end(); it != ie; ++it) {
1018 MatchableInfo *II = *it;
1020 // Parse the tokens after the mnemonic.
1021 for (unsigned i = 0, e = II->AsmOperands.size(); i != e; ++i) {
1022 MatchableInfo::Operand &Op = II->AsmOperands[i];
1023 StringRef Token = Op.Token;
1025 // Check for singleton registers.
1026 if (Record *RegRecord = II->getSingletonRegisterForAsmOperand(i, *this)) {
1027 Op.Class = RegisterClasses[RegRecord];
1028 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1029 "Unexpected class for singleton register");
1033 // Check for simple tokens.
1034 if (Token[0] != '$') {
1035 Op.Class = getTokenClass(Token);
1039 // Otherwise this is an operand reference.
1040 StringRef OperandName;
1041 if (Token[1] == '{')
1042 OperandName = Token.substr(2, Token.size() - 3);
1044 OperandName = Token.substr(1);
1046 // Map this token to an operand. FIXME: Move elsewhere.
1048 if (!II->OperandList.hasOperandNamed(OperandName, Idx))
1049 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1050 OperandName.str() + "'");
1052 // FIXME: This is annoying, the named operand may be tied (e.g.,
1053 // XCHG8rm). What we want is the untied operand, which we now have to
1054 // grovel for. Only worry about this for single entry operands, we have to
1055 // clean this up anyway.
1056 const CGIOperandList::OperandInfo *OI = &II->OperandList[Idx];
1057 if (OI->Constraints[0].isTied()) {
1058 unsigned TiedOp = OI->Constraints[0].getTiedOperand();
1060 // The tied operand index is an MIOperand index, find the operand that
1062 for (unsigned i = 0, e = II->OperandList.size(); i != e; ++i) {
1063 if (II->OperandList[i].MIOperandNo == TiedOp) {
1064 OI = &II->OperandList[i];
1069 assert(OI && "Unable to find tied operand target!");
1072 Op.Class = getOperandClass(Token, *OI);
1073 Op.OperandInfo = OI;
1077 // Reorder classes so that classes preceed super classes.
1078 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1081 static std::pair<unsigned, unsigned> *
1082 GetTiedOperandAtIndex(SmallVectorImpl<std::pair<unsigned, unsigned> > &List,
1084 for (unsigned i = 0, e = List.size(); i != e; ++i)
1085 if (Index == List[i].first)
1091 static void EmitConvertToMCInst(CodeGenTarget &Target,
1092 std::vector<MatchableInfo*> &Infos,
1094 // Write the convert function to a separate stream, so we can drop it after
1096 std::string ConvertFnBody;
1097 raw_string_ostream CvtOS(ConvertFnBody);
1099 // Function we have already generated.
1100 std::set<std::string> GeneratedFns;
1102 // Start the unified conversion function.
1104 CvtOS << "static void ConvertToMCInst(ConversionKind Kind, MCInst &Inst, "
1105 << "unsigned Opcode,\n"
1106 << " const SmallVectorImpl<MCParsedAsmOperand*"
1107 << "> &Operands) {\n";
1108 CvtOS << " Inst.setOpcode(Opcode);\n";
1109 CvtOS << " switch (Kind) {\n";
1110 CvtOS << " default:\n";
1112 // Start the enum, which we will generate inline.
1114 OS << "// Unified function for converting operants to MCInst instances.\n\n";
1115 OS << "enum ConversionKind {\n";
1117 // TargetOperandClass - This is the target's operand class, like X86Operand.
1118 std::string TargetOperandClass = Target.getName() + "Operand";
1120 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1121 ie = Infos.end(); it != ie; ++it) {
1122 MatchableInfo &II = **it;
1124 // Order the (class) operands by the order to convert them into an MCInst.
1125 SmallVector<std::pair<unsigned, unsigned>, 4> MIOperandList;
1126 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1127 MatchableInfo::Operand &Op = II.AsmOperands[i];
1129 MIOperandList.push_back(std::make_pair(Op.OperandInfo->MIOperandNo, i));
1132 // Find any tied operands.
1133 SmallVector<std::pair<unsigned, unsigned>, 4> TiedOperands;
1134 for (unsigned i = 0, e = II.OperandList.size(); i != e; ++i) {
1135 const CGIOperandList::OperandInfo &OpInfo = II.OperandList[i];
1136 for (unsigned j = 0, e = OpInfo.Constraints.size(); j != e; ++j) {
1137 const CGIOperandList::ConstraintInfo &CI = OpInfo.Constraints[j];
1139 TiedOperands.push_back(std::make_pair(OpInfo.MIOperandNo + j,
1140 CI.getTiedOperand()));
1144 array_pod_sort(MIOperandList.begin(), MIOperandList.end());
1146 // Compute the total number of operands.
1147 unsigned NumMIOperands = 0;
1148 for (unsigned i = 0, e = II.OperandList.size(); i != e; ++i) {
1149 const CGIOperandList::OperandInfo &OI = II.OperandList[i];
1150 NumMIOperands = std::max(NumMIOperands,
1151 OI.MIOperandNo + OI.MINumOperands);
1154 // Build the conversion function signature.
1155 std::string Signature = "Convert";
1156 unsigned CurIndex = 0;
1157 for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) {
1158 MatchableInfo::Operand &Op = II.AsmOperands[MIOperandList[i].second];
1159 assert(CurIndex <= Op.OperandInfo->MIOperandNo &&
1160 "Duplicate match for instruction operand!");
1162 // Skip operands which weren't matched by anything, this occurs when the
1163 // .td file encodes "implicit" operands as explicit ones.
1165 // FIXME: This should be removed from the MCInst structure.
1166 for (; CurIndex != Op.OperandInfo->MIOperandNo; ++CurIndex) {
1167 std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands,
1170 Signature += "__Imp";
1172 Signature += "__Tie" + utostr(Tie->second);
1177 // Registers are always converted the same, don't duplicate the conversion
1178 // function based on them.
1180 // FIXME: We could generalize this based on the render method, if it
1182 if (Op.Class->isRegisterClass())
1185 Signature += Op.Class->ClassName;
1186 Signature += utostr(Op.OperandInfo->MINumOperands);
1187 Signature += "_" + utostr(MIOperandList[i].second);
1189 CurIndex += Op.OperandInfo->MINumOperands;
1192 // Add any trailing implicit operands.
1193 for (; CurIndex != NumMIOperands; ++CurIndex) {
1194 std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands,
1197 Signature += "__Imp";
1199 Signature += "__Tie" + utostr(Tie->second);
1202 II.ConversionFnKind = Signature;
1204 // Check if we have already generated this signature.
1205 if (!GeneratedFns.insert(Signature).second)
1208 // If not, emit it now.
1210 // Add to the enum list.
1211 OS << " " << Signature << ",\n";
1213 // And to the convert function.
1214 CvtOS << " case " << Signature << ":\n";
1216 for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) {
1217 MatchableInfo::Operand &Op = II.AsmOperands[MIOperandList[i].second];
1219 // Add the implicit operands.
1220 for (; CurIndex != Op.OperandInfo->MIOperandNo; ++CurIndex) {
1221 // See if this is a tied operand.
1222 std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands,
1226 // If not, this is some implicit operand. Just assume it is a register
1228 CvtOS << " Inst.addOperand(MCOperand::CreateReg(0));\n";
1230 // Copy the tied operand.
1231 assert(Tie->first>Tie->second && "Tied operand preceeds its target!");
1232 CvtOS << " Inst.addOperand(Inst.getOperand("
1233 << Tie->second << "));\n";
1237 CvtOS << " ((" << TargetOperandClass << "*)Operands["
1238 << MIOperandList[i].second
1239 << "+1])->" << Op.Class->RenderMethod
1240 << "(Inst, " << Op.OperandInfo->MINumOperands << ");\n";
1241 CurIndex += Op.OperandInfo->MINumOperands;
1244 // And add trailing implicit operands.
1245 for (; CurIndex != NumMIOperands; ++CurIndex) {
1246 std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands,
1250 // If not, this is some implicit operand. Just assume it is a register
1252 CvtOS << " Inst.addOperand(MCOperand::CreateReg(0));\n";
1254 // Copy the tied operand.
1255 assert(Tie->first>Tie->second && "Tied operand preceeds its target!");
1256 CvtOS << " Inst.addOperand(Inst.getOperand("
1257 << Tie->second << "));\n";
1261 CvtOS << " return;\n";
1264 // Finish the convert function.
1269 // Finish the enum, and drop the convert function after it.
1271 OS << " NumConversionVariants\n";
1277 /// EmitMatchClassEnumeration - Emit the enumeration for match class kinds.
1278 static void EmitMatchClassEnumeration(CodeGenTarget &Target,
1279 std::vector<ClassInfo*> &Infos,
1281 OS << "namespace {\n\n";
1283 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1284 << "/// instruction matching.\n";
1285 OS << "enum MatchClassKind {\n";
1286 OS << " InvalidMatchClass = 0,\n";
1287 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1288 ie = Infos.end(); it != ie; ++it) {
1289 ClassInfo &CI = **it;
1290 OS << " " << CI.Name << ", // ";
1291 if (CI.Kind == ClassInfo::Token) {
1292 OS << "'" << CI.ValueName << "'\n";
1293 } else if (CI.isRegisterClass()) {
1294 if (!CI.ValueName.empty())
1295 OS << "register class '" << CI.ValueName << "'\n";
1297 OS << "derived register class\n";
1299 OS << "user defined class '" << CI.ValueName << "'\n";
1302 OS << " NumMatchClassKinds\n";
1308 /// EmitClassifyOperand - Emit the function to classify an operand.
1309 static void EmitClassifyOperand(AsmMatcherInfo &Info,
1311 OS << "static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {\n"
1312 << " " << Info.Target.getName() << "Operand &Operand = *("
1313 << Info.Target.getName() << "Operand*)GOp;\n";
1316 OS << " if (Operand.isToken())\n";
1317 OS << " return MatchTokenString(Operand.getToken());\n\n";
1319 // Classify registers.
1321 // FIXME: Don't hardcode isReg, getReg.
1322 OS << " if (Operand.isReg()) {\n";
1323 OS << " switch (Operand.getReg()) {\n";
1324 OS << " default: return InvalidMatchClass;\n";
1325 for (std::map<Record*, ClassInfo*>::iterator
1326 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
1328 OS << " case " << Info.Target.getName() << "::"
1329 << it->first->getName() << ": return " << it->second->Name << ";\n";
1333 // Classify user defined operands.
1334 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
1335 ie = Info.Classes.end(); it != ie; ++it) {
1336 ClassInfo &CI = **it;
1338 if (!CI.isUserClass())
1341 OS << " // '" << CI.ClassName << "' class";
1342 if (!CI.SuperClasses.empty()) {
1343 OS << ", subclass of ";
1344 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) {
1346 OS << "'" << CI.SuperClasses[i]->ClassName << "'";
1347 assert(CI < *CI.SuperClasses[i] && "Invalid class relation!");
1352 OS << " if (Operand." << CI.PredicateMethod << "()) {\n";
1354 // Validate subclass relationships.
1355 if (!CI.SuperClasses.empty()) {
1356 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i)
1357 OS << " assert(Operand." << CI.SuperClasses[i]->PredicateMethod
1358 << "() && \"Invalid class relationship!\");\n";
1361 OS << " return " << CI.Name << ";\n";
1364 OS << " return InvalidMatchClass;\n";
1368 /// EmitIsSubclass - Emit the subclass predicate function.
1369 static void EmitIsSubclass(CodeGenTarget &Target,
1370 std::vector<ClassInfo*> &Infos,
1372 OS << "/// IsSubclass - Compute whether \\arg A is a subclass of \\arg B.\n";
1373 OS << "static bool IsSubclass(MatchClassKind A, MatchClassKind B) {\n";
1374 OS << " if (A == B)\n";
1375 OS << " return true;\n\n";
1377 OS << " switch (A) {\n";
1378 OS << " default:\n";
1379 OS << " return false;\n";
1380 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1381 ie = Infos.end(); it != ie; ++it) {
1382 ClassInfo &A = **it;
1384 if (A.Kind != ClassInfo::Token) {
1385 std::vector<StringRef> SuperClasses;
1386 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1387 ie = Infos.end(); it != ie; ++it) {
1388 ClassInfo &B = **it;
1390 if (&A != &B && A.isSubsetOf(B))
1391 SuperClasses.push_back(B.Name);
1394 if (SuperClasses.empty())
1397 OS << "\n case " << A.Name << ":\n";
1399 if (SuperClasses.size() == 1) {
1400 OS << " return B == " << SuperClasses.back() << ";\n";
1404 OS << " switch (B) {\n";
1405 OS << " default: return false;\n";
1406 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
1407 OS << " case " << SuperClasses[i] << ": return true;\n";
1417 /// EmitMatchTokenString - Emit the function to match a token string to the
1418 /// appropriate match class value.
1419 static void EmitMatchTokenString(CodeGenTarget &Target,
1420 std::vector<ClassInfo*> &Infos,
1422 // Construct the match list.
1423 std::vector<StringMatcher::StringPair> Matches;
1424 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1425 ie = Infos.end(); it != ie; ++it) {
1426 ClassInfo &CI = **it;
1428 if (CI.Kind == ClassInfo::Token)
1429 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
1430 "return " + CI.Name + ";"));
1433 OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n";
1435 StringMatcher("Name", Matches, OS).Emit();
1437 OS << " return InvalidMatchClass;\n";
1441 /// EmitMatchRegisterName - Emit the function to match a string to the target
1442 /// specific register enum.
1443 static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
1445 // Construct the match list.
1446 std::vector<StringMatcher::StringPair> Matches;
1447 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
1448 const CodeGenRegister &Reg = Target.getRegisters()[i];
1449 if (Reg.TheDef->getValueAsString("AsmName").empty())
1452 Matches.push_back(StringMatcher::StringPair(
1453 Reg.TheDef->getValueAsString("AsmName"),
1454 "return " + utostr(i + 1) + ";"));
1457 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
1459 StringMatcher("Name", Matches, OS).Emit();
1461 OS << " return 0;\n";
1465 /// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
1467 static void EmitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
1469 OS << "// Flags for subtarget features that participate in "
1470 << "instruction matching.\n";
1471 OS << "enum SubtargetFeatureFlag {\n";
1472 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1473 it = Info.SubtargetFeatures.begin(),
1474 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1475 SubtargetFeatureInfo &SFI = *it->second;
1476 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
1478 OS << " Feature_None = 0\n";
1482 /// EmitComputeAvailableFeatures - Emit the function to compute the list of
1483 /// available features given a subtarget.
1484 static void EmitComputeAvailableFeatures(AsmMatcherInfo &Info,
1486 std::string ClassName =
1487 Info.AsmParser->getValueAsString("AsmParserClassName");
1489 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
1490 << "ComputeAvailableFeatures(const " << Info.Target.getName()
1491 << "Subtarget *Subtarget) const {\n";
1492 OS << " unsigned Features = 0;\n";
1493 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1494 it = Info.SubtargetFeatures.begin(),
1495 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1496 SubtargetFeatureInfo &SFI = *it->second;
1497 OS << " if (" << SFI.TheDef->getValueAsString("CondString")
1499 OS << " Features |= " << SFI.getEnumName() << ";\n";
1501 OS << " return Features;\n";
1505 static std::string GetAliasRequiredFeatures(Record *R,
1506 const AsmMatcherInfo &Info) {
1507 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
1509 unsigned NumFeatures = 0;
1510 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
1511 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
1514 throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
1515 "' is not marked as an AssemblerPredicate!");
1520 Result += F->getEnumName();
1524 if (NumFeatures > 1)
1525 Result = '(' + Result + ')';
1529 /// EmitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
1530 /// emit a function for them and return true, otherwise return false.
1531 static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) {
1532 std::vector<Record*> Aliases =
1533 Records.getAllDerivedDefinitions("MnemonicAlias");
1534 if (Aliases.empty()) return false;
1536 OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, "
1537 "unsigned Features) {\n";
1539 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
1540 // iteration order of the map is stable.
1541 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
1543 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
1544 Record *R = Aliases[i];
1545 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
1548 // Process each alias a "from" mnemonic at a time, building the code executed
1549 // by the string remapper.
1550 std::vector<StringMatcher::StringPair> Cases;
1551 for (std::map<std::string, std::vector<Record*> >::iterator
1552 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
1554 const std::vector<Record*> &ToVec = I->second;
1556 // Loop through each alias and emit code that handles each case. If there
1557 // are two instructions without predicates, emit an error. If there is one,
1559 std::string MatchCode;
1560 int AliasWithNoPredicate = -1;
1562 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
1563 Record *R = ToVec[i];
1564 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
1566 // If this unconditionally matches, remember it for later and diagnose
1568 if (FeatureMask.empty()) {
1569 if (AliasWithNoPredicate != -1) {
1570 // We can't have two aliases from the same mnemonic with no predicate.
1571 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
1572 "two MnemonicAliases with the same 'from' mnemonic!");
1573 throw TGError(R->getLoc(), "this is the other MnemonicAlias.");
1576 AliasWithNoPredicate = i;
1580 if (!MatchCode.empty())
1581 MatchCode += "else ";
1582 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
1583 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
1586 if (AliasWithNoPredicate != -1) {
1587 Record *R = ToVec[AliasWithNoPredicate];
1588 if (!MatchCode.empty())
1589 MatchCode += "else\n ";
1590 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
1593 MatchCode += "return;";
1595 Cases.push_back(std::make_pair(I->first, MatchCode));
1599 StringMatcher("Mnemonic", Cases, OS).Emit();
1605 void AsmMatcherEmitter::run(raw_ostream &OS) {
1606 CodeGenTarget Target;
1607 Record *AsmParser = Target.getAsmParser();
1608 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
1610 // Compute the information on the instructions to match.
1611 AsmMatcherInfo Info(AsmParser, Target);
1614 // Sort the instruction table using the partial order on classes. We use
1615 // stable_sort to ensure that ambiguous instructions are still
1616 // deterministically ordered.
1617 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
1618 less_ptr<MatchableInfo>());
1620 DEBUG_WITH_TYPE("instruction_info", {
1621 for (std::vector<MatchableInfo*>::iterator
1622 it = Info.Matchables.begin(), ie = Info.Matchables.end();
1627 // Check for ambiguous matchables.
1628 DEBUG_WITH_TYPE("ambiguous_instrs", {
1629 unsigned NumAmbiguous = 0;
1630 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
1631 for (unsigned j = i + 1; j != e; ++j) {
1632 MatchableInfo &A = *Info.Matchables[i];
1633 MatchableInfo &B = *Info.Matchables[j];
1635 if (A.CouldMatchAmiguouslyWith(B)) {
1636 errs() << "warning: ambiguous matchables:\n";
1638 errs() << "\nis incomparable with:\n";
1646 errs() << "warning: " << NumAmbiguous
1647 << " ambiguous matchables!\n";
1650 // Write the output.
1652 EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
1654 // Information for the class declaration.
1655 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
1656 OS << "#undef GET_ASSEMBLER_HEADER\n";
1657 OS << " // This should be included into the middle of the declaration of \n";
1658 OS << " // your subclasses implementation of TargetAsmParser.\n";
1659 OS << " unsigned ComputeAvailableFeatures(const " <<
1660 Target.getName() << "Subtarget *Subtarget) const;\n";
1661 OS << " enum MatchResultTy {\n";
1662 OS << " Match_Success, Match_MnemonicFail, Match_InvalidOperand,\n";
1663 OS << " Match_MissingFeature\n";
1665 OS << " MatchResultTy MatchInstructionImpl(const "
1666 << "SmallVectorImpl<MCParsedAsmOperand*>"
1667 << " &Operands, MCInst &Inst, unsigned &ErrorInfo);\n\n";
1668 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
1673 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
1674 OS << "#undef GET_REGISTER_MATCHER\n\n";
1676 // Emit the subtarget feature enumeration.
1677 EmitSubtargetFeatureFlagEnumeration(Info, OS);
1679 // Emit the function to match a register name to number.
1680 EmitMatchRegisterName(Target, AsmParser, OS);
1682 OS << "#endif // GET_REGISTER_MATCHER\n\n";
1685 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
1686 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
1688 // Generate the function that remaps for mnemonic aliases.
1689 bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info);
1691 // Generate the unified function to convert operands into an MCInst.
1692 EmitConvertToMCInst(Target, Info.Matchables, OS);
1694 // Emit the enumeration for classes which participate in matching.
1695 EmitMatchClassEnumeration(Target, Info.Classes, OS);
1697 // Emit the routine to match token strings to their match class.
1698 EmitMatchTokenString(Target, Info.Classes, OS);
1700 // Emit the routine to classify an operand.
1701 EmitClassifyOperand(Info, OS);
1703 // Emit the subclass predicate routine.
1704 EmitIsSubclass(Target, Info.Classes, OS);
1706 // Emit the available features compute function.
1707 EmitComputeAvailableFeatures(Info, OS);
1710 size_t MaxNumOperands = 0;
1711 for (std::vector<MatchableInfo*>::const_iterator it =
1712 Info.Matchables.begin(), ie = Info.Matchables.end();
1714 MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size());
1717 // Emit the static match table; unused classes get initalized to 0 which is
1718 // guaranteed to be InvalidMatchClass.
1720 // FIXME: We can reduce the size of this table very easily. First, we change
1721 // it so that store the kinds in separate bit-fields for each index, which
1722 // only needs to be the max width used for classes at that index (we also need
1723 // to reject based on this during classification). If we then make sure to
1724 // order the match kinds appropriately (putting mnemonics last), then we
1725 // should only end up using a few bits for each class, especially the ones
1726 // following the mnemonic.
1727 OS << "namespace {\n";
1728 OS << " struct MatchEntry {\n";
1729 OS << " unsigned Opcode;\n";
1730 OS << " const char *Mnemonic;\n";
1731 OS << " ConversionKind ConvertFn;\n";
1732 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1733 OS << " unsigned RequiredFeatures;\n";
1736 OS << "// Predicate for searching for an opcode.\n";
1737 OS << " struct LessOpcode {\n";
1738 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
1739 OS << " return StringRef(LHS.Mnemonic) < RHS;\n";
1741 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
1742 OS << " return LHS < StringRef(RHS.Mnemonic);\n";
1744 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
1745 OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n";
1749 OS << "} // end anonymous namespace.\n\n";
1751 OS << "static const MatchEntry MatchTable["
1752 << Info.Matchables.size() << "] = {\n";
1754 for (std::vector<MatchableInfo*>::const_iterator it =
1755 Info.Matchables.begin(), ie = Info.Matchables.end();
1757 MatchableInfo &II = **it;
1759 OS << " { " << Target.getName() << "::" << II.InstrName
1760 << ", \"" << II.Mnemonic << "\""
1761 << ", " << II.ConversionFnKind << ", { ";
1762 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1763 MatchableInfo::Operand &Op = II.AsmOperands[i];
1766 OS << Op.Class->Name;
1770 // Write the required features mask.
1771 if (!II.RequiredFeatures.empty()) {
1772 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
1774 OS << II.RequiredFeatures[i]->getEnumName();
1784 // Finally, build the match function.
1785 OS << Target.getName() << ClassName << "::MatchResultTy "
1786 << Target.getName() << ClassName << "::\n"
1787 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
1789 OS << " MCInst &Inst, unsigned &ErrorInfo) {\n";
1791 // Emit code to get the available features.
1792 OS << " // Get the current feature set.\n";
1793 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
1795 OS << " // Get the instruction mnemonic, which is the first token.\n";
1796 OS << " StringRef Mnemonic = ((" << Target.getName()
1797 << "Operand*)Operands[0])->getToken();\n\n";
1799 if (HasMnemonicAliases) {
1800 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
1801 OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n";
1804 // Emit code to compute the class list for this operand vector.
1805 OS << " // Eliminate obvious mismatches.\n";
1806 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
1807 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
1808 OS << " return Match_InvalidOperand;\n";
1811 OS << " // Compute the class list for this operand vector.\n";
1812 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1813 OS << " for (unsigned i = 1, e = Operands.size(); i != e; ++i) {\n";
1814 OS << " Classes[i-1] = ClassifyOperand(Operands[i]);\n\n";
1816 OS << " // Check for invalid operands before matching.\n";
1817 OS << " if (Classes[i-1] == InvalidMatchClass) {\n";
1818 OS << " ErrorInfo = i;\n";
1819 OS << " return Match_InvalidOperand;\n";
1823 OS << " // Mark unused classes.\n";
1824 OS << " for (unsigned i = Operands.size()-1, e = " << MaxNumOperands << "; "
1825 << "i != e; ++i)\n";
1826 OS << " Classes[i] = InvalidMatchClass;\n\n";
1828 OS << " // Some state to try to produce better error messages.\n";
1829 OS << " bool HadMatchOtherThanFeatures = false;\n\n";
1830 OS << " // Set ErrorInfo to the operand that mismatches if it is \n";
1831 OS << " // wrong for all instances of the instruction.\n";
1832 OS << " ErrorInfo = ~0U;\n";
1834 // Emit code to search the table.
1835 OS << " // Search the table.\n";
1836 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
1837 OS << " std::equal_range(MatchTable, MatchTable+"
1838 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n";
1840 OS << " // Return a more specific error code if no mnemonics match.\n";
1841 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
1842 OS << " return Match_MnemonicFail;\n\n";
1844 OS << " for (const MatchEntry *it = MnemonicRange.first, "
1845 << "*ie = MnemonicRange.second;\n";
1846 OS << " it != ie; ++it) {\n";
1848 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
1849 OS << " assert(Mnemonic == it->Mnemonic);\n";
1851 // Emit check that the subclasses match.
1852 OS << " bool OperandsValid = true;\n";
1853 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
1854 OS << " if (IsSubclass(Classes[i], it->Classes[i]))\n";
1855 OS << " continue;\n";
1856 OS << " // If this operand is broken for all of the instances of this\n";
1857 OS << " // mnemonic, keep track of it so we can report loc info.\n";
1858 OS << " if (it == MnemonicRange.first || ErrorInfo == i+1)\n";
1859 OS << " ErrorInfo = i+1;\n";
1861 OS << " ErrorInfo = ~0U;";
1862 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
1863 OS << " OperandsValid = false;\n";
1867 OS << " if (!OperandsValid) continue;\n";
1869 // Emit check that the required features are available.
1870 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
1871 << "!= it->RequiredFeatures) {\n";
1872 OS << " HadMatchOtherThanFeatures = true;\n";
1873 OS << " continue;\n";
1877 OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
1879 // Call the post-processing function, if used.
1880 std::string InsnCleanupFn =
1881 AsmParser->getValueAsString("AsmParserInstCleanup");
1882 if (!InsnCleanupFn.empty())
1883 OS << " " << InsnCleanupFn << "(Inst);\n";
1885 OS << " return Match_Success;\n";
1888 OS << " // Okay, we had no match. Try to return a useful error code.\n";
1889 OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n";
1890 OS << " return Match_InvalidOperand;\n";
1893 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";